x86: crownbay: Add MP initialization

Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y")

x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y")
Bin Meng · Simon Glass
1 parent 63d54a6705
Showing 2 changed files with 24 additions and 0 deletions Side-by-side Diff
arch/x86/dts/crownbay.dts
configs/crownbay_defconfig
@@ -23,6 +23,26 @@
 		silent_console = <0>;
 	};
  
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <1>;
+			intel,apic-id = <1>;
+		};
+
+	};
+
 	gpioa {
 		compatible = "intel,ich6-gpio";
 		u-boot,dm-pre-reloc;
@@ -2,7 +2,10 @@
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="crownbay"
 CONFIG_TARGET_CROWNBAY=y
+CONFIG_SMP=y
+CONFIG_MAX_CPUS=2
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
@@ -11,6 +14,7 @@
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y
...	...	@@ -23,6 +23,26 @@
23	23	silent_console = <0>;
24	24	};
25	25
	26	+ cpus {
	27	+ #address-cells = <1>;
	28	+ #size-cells = <0>;
	29	+
	30	+ cpu@0 {
	31	+ device_type = "cpu";
	32	+ compatible = "cpu-x86";
	33	+ reg = <0>;
	34	+ intel,apic-id = <0>;
	35	+ };
	36	+
	37	+ cpu@1 {
	38	+ device_type = "cpu";
	39	+ compatible = "cpu-x86";
	40	+ reg = <1>;
	41	+ intel,apic-id = <1>;
	42	+ };
	43	+
	44	+ };
	45	+
26	46	gpioa {
27	47	compatible = "intel,ich6-gpio";
28	48	u-boot,dm-pre-reloc;
...	...	@@ -2,7 +2,10 @@
2	2	CONFIG_VENDOR_INTEL=y
3	3	CONFIG_DEFAULT_DEVICE_TREE="crownbay"
4	4	CONFIG_TARGET_CROWNBAY=y
	5	+CONFIG_SMP=y
	6	+CONFIG_MAX_CPUS=2
5	7	CONFIG_GENERATE_PIRQ_TABLE=y
	8	+CONFIG_CMD_CPU=y
6	9	# CONFIG_CMD_IMLS is not set
7	10	# CONFIG_CMD_FLASH is not set
8	11	# CONFIG_CMD_SETEXPR is not set
...	...	@@ -11,6 +14,7 @@
11	14	CONFIG_BOOTSTAGE_REPORT=y
12	15	CONFIG_CMD_BOOTSTAGE=y
13	16	CONFIG_OF_CONTROL=y
	17	+CONFIG_CPU=y
14	18	CONFIG_SPI_FLASH=y
15	19	CONFIG_USE_PRIVATE_LIBGCC=y
16	20	CONFIG_SYS_VSNPRINTF=y