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Commit 99977a1152981247a84252dba1d1cf55c0406b08

Authored by Ye.Li
Committed by Ye Li
1 parent e0cfa88953
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

ENGR00315894-78 vadc: Add vadc module 

Add vadc module.
Both PAL and NTSC mode can work.

Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 03c31ae30c1e81c99f6824221e4801433445e04a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b5d776ffc1519c16091736445b3217ffb7fcd7db)
(cherry picked from commit 2377eb9fd299b76888f11faf76383b68e77bcc8a)
(cherry picked from commit 808d447235bd0f9134c7d00fa480cd55b4e0426e)

Showing 2 changed files with 603 additions and 0 deletions Side-by-side Diff

drivers/video/mxc_vadc.c
Diff comments   View file @ 99977a1
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +
  9 +#include <asm/arch/imx-regs.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/arch/clock.h>
  12 +#include <linux/errno.h>
  13 +#include <asm/io.h>
  14 +
  15 +#include <linux/string.h>
  16 +#include <linux/list.h>
  17 +#include <gis.h>
  18 +
  19 +#include "mxc_vadc.h"
  20 +
  21 +#define reg32_write(addr, val) __raw_writel(val, addr)
  22 +#define reg32_read(addr) __raw_readl(addr)
  23 +#define reg32setbit(addr, bitpos) \
  24 + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
  25 +
  26 +#define reg32clrbit(addr, bitpos) \
  27 + reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
  28 +
  29 +void __iomem *vafe_regbase;
  30 +void __iomem *vdec_regbase;
  31 +
  32 +enum {
  33 + STD_NTSC = 0,
  34 + STD_PAL,
  35 +};
  36 +
  37 +/* Video format structure. */
  38 +struct video_fmt_t{
  39 + int v4l2_id; /* Video for linux ID. */
  40 + char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */
  41 + u16 active_width; /* Active width. */
  42 + u16 active_height; /* Active height. */
  43 +};
  44 +
  45 +/* Description of video formats supported.
  46 + *
  47 + * PAL: active=720x576.
  48 + * NTSC:active=720x480.
  49 + */
  50 +static struct video_fmt_t video_fmts[] = {
  51 + /* NTSC */
  52 + {
  53 + .v4l2_id = STD_NTSC,
  54 + .name = "NTSC",
  55 + .active_width = 720,
  56 + .active_height = 480,
  57 + },
  58 + /* (B, G, H, I, N) PAL */
  59 + {
  60 + .v4l2_id = STD_PAL,
  61 + .name = "PAL",
  62 + .active_width = 720,
  63 + .active_height = 576,
  64 + },
  65 +};
  66 +
  67 +static void afe_voltage_clampingmode(void)
  68 +{
  69 + reg32_write(AFE_CLAMP, 0x07);
  70 + reg32_write(AFE_CLMPAMP, 0x60);
  71 + reg32_write(AFE_CLMPDAT, 0xF0);
  72 +}
  73 +
  74 +static void afe_alwayson_clampingmode(void)
  75 +{
  76 + reg32_write(AFE_CLAMP, 0x15);
  77 + reg32_write(AFE_CLMPDAT, 0x08);
  78 + reg32_write(AFE_CLMPAMP, 0x00);
  79 +}
  80 +
  81 +static void afe_init(void)
  82 +{
  83 + reg32_write(AFE_PDBUF, 0x1f);
  84 + reg32_write(AFE_PDADC, 0x0f);
  85 + reg32_write(AFE_PDSARH, 0x01);
  86 + reg32_write(AFE_PDSARL, 0xff);
  87 + reg32_write(AFE_PDADCRFH, 0x01);
  88 + reg32_write(AFE_PDADCRFL, 0xff);
  89 + reg32_write(AFE_ICTRL, 0x3a);
  90 + reg32_write(AFE_ICTLSTG, 0x1e);
  91 +
  92 + reg32_write(AFE_RCTRLSTG, 0x1e);
  93 + reg32_write(AFE_INPBUF, 0x035);
  94 + reg32_write(AFE_INPFLT, 0x02);
  95 + reg32_write(AFE_ADCDGN, 0x40);
  96 + reg32_write(AFE_TSTSEL, 0x10);
  97 +
  98 + reg32_write(AFE_ACCTST, 0x07);
  99 +
  100 + reg32_write(AFE_BGREG, 0x08);
  101 +
  102 + reg32_write(AFE_ADCGN, 0x09);
  103 +
  104 + /* set current controlled clamping
  105 + * always on, low current */
  106 + reg32_write(AFE_CLAMP, 0x11);
  107 + reg32_write(AFE_CLMPAMP, 0x08);
  108 +}
  109 +
  110 +static void vdec_mode_timing_init(u32 std)
  111 +{
  112 + if (std == STD_NTSC) {
  113 + /* NTSC 720x480 */
  114 + printf("NTSC\n");
  115 + reg32_write(VDEC_HACTS, 0x66);
  116 + reg32_write(VDEC_HACTE, 0x24);
  117 +
  118 + reg32_write(VDEC_VACTS, 0x29);
  119 + reg32_write(VDEC_VACTE, 0x04);
  120 +
  121 + /* set V Position */
  122 + reg32_write(VDEC_VRTPOS, 0x2);
  123 + } else if (std == STD_PAL) {
  124 + /* PAL 720x576 */
  125 + printf("PAL\n");
  126 + reg32_write(VDEC_HACTS, 0x66);
  127 + reg32_write(VDEC_HACTE, 0x24);
  128 +
  129 + reg32_write(VDEC_VACTS, 0x29);
  130 + reg32_write(VDEC_VACTE, 0x04);
  131 +
  132 + /* set V Position */
  133 + reg32_write(VDEC_VRTPOS, 0x6);
  134 + } else
  135 + printf("Error not support video mode\n");
  136 +
  137 + /* set H Position */
  138 + reg32_write(VDEC_HZPOS, 0x60);
  139 +
  140 + /* set H ignore start */
  141 + reg32_write(VDEC_HSIGS, 0xf8);
  142 +
  143 + /* set H ignore end */
  144 + reg32_write(VDEC_HSIGE, 0x18);
  145 +}
  146 +
  147 +/*
  148 +* vdec_init()
  149 +* Initialises the VDEC registers
  150 +* Returns: nothing
  151 +*/
  152 +static void vdec_init(struct sensor_data *vadc)
  153 +{
  154 + /* Get work mode PAL or NTSC
  155 + * delay 500ms wait vdec detect input format*/
  156 + udelay(500*1000);
  157 + vadc_get_std(vadc);
  158 +
  159 + vdec_mode_timing_init(vadc->std_id);
  160 +
  161 + /* vcr detect threshold high, automatic detections */
  162 + reg32_write(VDEC_VSCON2, 0);
  163 +
  164 + reg32_write(VDEC_BASE + 0x110, 0x01);
  165 +
  166 + /* set the noramp mode on the Hloop PLL. */
  167 + reg32_write(VDEC_BASE+(0x14*4), 0x10);
  168 +
  169 + /* set the YC relative delay.*/
  170 + reg32_write(VDEC_YCDEL, 0x90);
  171 +
  172 + /* setup the Hpll */
  173 + reg32_write(VDEC_BASE+(0x13*4), 0x13);
  174 +
  175 + /* setup the 2d comb */
  176 + /* set the gain of the Hdetail output to 3
  177 + * set the notch alpha gain to 1 */
  178 + reg32_write(VDEC_CFC2, 0x34);
  179 +
  180 + /* setup various 2d comb bits.*/
  181 + reg32_write(VDEC_BASE+(0x02*4), 0x01);
  182 + reg32_write(VDEC_BASE+(0x03*4), 0x18);
  183 + reg32_write(VDEC_BASE+(0x04*4), 0x34);
  184 +
  185 + /* set the start of the burst gate */
  186 + reg32_write(VDEC_BRSTGT, 0x30);
  187 +
  188 + /* set 1f motion gain */
  189 + reg32_write(VDEC_BASE+(0x0f*4), 0x20);
  190 +
  191 + /* set the 1F chroma motion detector thresh for colour reverse detection */
  192 + reg32_write(VDEC_THSH1, 0x02);
  193 + reg32_write(VDEC_BASE+(0x4a*4), 0x20);
  194 + reg32_write(VDEC_BASE+(0x4b*4), 0x08);
  195 +
  196 + reg32_write(VDEC_BASE+(0x4c*4), 0x08);
  197 +
  198 + /* set the threshold for the narrow/wide adaptive chroma BW */
  199 + reg32_write(VDEC_BASE+(0x20*4), 0x20);
  200 +
  201 + /* turn up the colour with the new colour gain reg */
  202 + /* hue: */
  203 + reg32_write(VDEC_HUE, 0x00);
  204 +
  205 + /* cbgain: 22 B4 */
  206 + reg32_write(VDEC_CBGN, 0xb4);
  207 + /* cr gain 80 */
  208 + reg32_write(VDEC_CRGN, 0x80);
  209 + /* luma gain (contrast) */
  210 + reg32_write(VDEC_CNTR, 0x80);
  211 +
  212 + /* setup the signed black level register, brightness */
  213 + reg32_write(VDEC_BRT, 0x00);
  214 +
  215 + /* filter the standard detection
  216 + * enable the comb for the ntsc443 */
  217 + reg32_write(VDEC_STDDBG, 0x23);
  218 +
  219 + /* setup chroma kill thresh for no chroma */
  220 + reg32_write(VDEC_CHBTH, 0x0);
  221 +
  222 + /* set chroma loop to wider BW
  223 + * no set it to normal BW. i fixed the bw problem.*/
  224 + reg32_write(VDEC_YCDEL, 0x00);
  225 +
  226 + /* set the compensation in the chroma loop for the Hloop
  227 + * set the ratio for the nonarithmetic 3d comb modes.*/
  228 + reg32_write(VDEC_BASE + (0x1d*4), 0x90);
  229 +
  230 + /* set the threshold for the nonarithmetic mode for the 2d comb
  231 + * the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */
  232 + reg32_write(VDEC_BASE + (0x33*4), 0xa0);
  233 +
  234 + /* setup the bluescreen output colour */
  235 + reg32_write(VDEC_BASE + (0x3d*4), 35);
  236 + reg32_write(VDEC_BLSCRCR, 114);
  237 + reg32_write(VDEC_BLSCRCB, 212);
  238 +
  239 + /* disable the active blanking */
  240 + reg32_write(VDEC_BASE + (0x15*4), 0x02);
  241 +
  242 + /* setup the luma agc for automatic gain. */
  243 + reg32_write(VDEC_LMAGC2, 0x5e);
  244 + reg32_write(VDEC_BASE + (0x40*4), 0x81);
  245 +
  246 + /* setup chroma agc */
  247 + reg32_write(VDEC_CHAGC2, 0xa0);
  248 + reg32_write(VDEC_CHAGC1, 0x01);
  249 +
  250 + /* setup the MV thresh lower nibble
  251 + * setup the sync top cap, upper nibble */
  252 + reg32_write(VDEC_BASE + (0x3a*4), 0x80);
  253 + reg32_write(VDEC_SHPIMP, 0x00);
  254 +
  255 + /* setup the vsync block */
  256 + reg32_write(VDEC_VSCON1, 0x87);
  257 +
  258 + /* set the nosignal threshold
  259 + * set the vsync threshold */
  260 + reg32_write(VDEC_VSSGTH, 0x35);
  261 +
  262 + /* set length for min hphase filter (or saturate limit if saturate is chosen) */
  263 + reg32_write(VDEC_BASE + (0x45*4), 0x40);
  264 +
  265 + /* enable the internal resampler,
  266 + * select min filter not saturate for hphase noise filter for vcr detect.
  267 + * enable vcr pause mode different field lengths */
  268 + reg32_write(VDEC_BASE + (0x46*4), 0x90);
  269 +
  270 + /* disable VCR detection, lock to the Hsync rather than the Vsync */
  271 + reg32_write(VDEC_VSCON2, 0x04);
  272 +
  273 + /* set tiplevel goal for dc clamp. */
  274 + reg32_write(VDEC_BASE + (0x3c*4), 0xB0);
  275 +
  276 + /* override SECAM detection and force SECAM off */
  277 + reg32_write(VDEC_BASE + (0x2f*4), 0x20);
  278 +
  279 + /* Set r3d_hardblend in 3D control2 reg */
  280 + reg32_write(VDEC_BASE + (0x0c*4), 0x04);
  281 +}
  282 +
  283 +/* set Input selector & input pull-downs */
  284 +static void vadc_select_input(int vadc_in)
  285 +{
  286 + switch (vadc_in) {
  287 + case 0:
  288 + reg32_write(AFE_INPFLT, 0x02);
  289 + reg32_write(AFE_OFFDRV, 0x00);
  290 + reg32_write(AFE_INPCONFIG, 0x1e);
  291 + break;
  292 + case 1:
  293 + reg32_write(AFE_INPFLT, 0x02);
  294 + reg32_write(AFE_OFFDRV, 0x00);
  295 + reg32_write(AFE_INPCONFIG, 0x2d);
  296 + break;
  297 + case 2:
  298 + reg32_write(AFE_INPFLT, 0x02);
  299 + reg32_write(AFE_OFFDRV, 0x00);
  300 + reg32_write(AFE_INPCONFIG, 0x4b);
  301 + break;
  302 + case 3:
  303 + reg32_write(AFE_INPFLT, 0x02);
  304 + reg32_write(AFE_OFFDRV, 0x00);
  305 + reg32_write(AFE_INPCONFIG, 0x87);
  306 + break;
  307 + default:
  308 + printf("error video input %d\n", vadc_in);
  309 + }
  310 +}
  311 +
  312 +/*!
  313 + * Return attributes of current video standard.
  314 + * Since this device autodetects the current standard, this function also
  315 + * sets the values that need to be changed if the standard changes.
  316 + * There is no set std equivalent function.
  317 + *
  318 + * @return None.
  319 + */
  320 +void vadc_get_std(struct sensor_data *vadc)
  321 +{
  322 + int tmp;
  323 + int idx;
  324 +
  325 + /* Read PAL mode detected result */
  326 + tmp = reg32_read(VDEC_VIDMOD);
  327 + tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK);
  328 +
  329 + if (tmp)
  330 + idx = STD_PAL;
  331 + else
  332 + idx = STD_NTSC;
  333 +
  334 + vadc->std_id = idx;
  335 + vadc->pixel_fmt = FMT_YUV444;
  336 + vadc->width = video_fmts[idx].active_width;
  337 + vadc->height = video_fmts[idx].active_height;
  338 +}
  339 +
  340 +void vadc_config(u32 vadc_in)
  341 +{
  342 + struct sensor_data vadc;
  343 +
  344 + /* map vafe,vdec,gpr,gpc address */
  345 + vafe_regbase = (u32 *)VADC_BASE_ADDR;
  346 + vdec_regbase = (u32 *)VDEC_BASE_ADDR;
  347 +
  348 + vadc_power_up();
  349 +
  350 + /* clock config for vadc */
  351 + reg32_write(VDEC_BASE + 0x320, 0xe3);
  352 + reg32_write(VDEC_BASE + 0x324, 0x38);
  353 + reg32_write(VDEC_BASE + 0x328, 0x8e);
  354 + reg32_write(VDEC_BASE + 0x32c, 0x23);
  355 + mxs_set_vadcclk();
  356 +
  357 + afe_init();
  358 +
  359 + /* select Video Input 0-3 */
  360 + vadc_select_input(vadc_in);
  361 +
  362 + afe_voltage_clampingmode();
  363 +
  364 + vdec_init(&vadc);
  365 +
  366 + /*
  367 + * current control loop will move sinewave input off below
  368 + * the bottom of the signal range visible when the testbus is viewed as magnitude,
  369 + * so have to break before this point while capturing ENOB data:
  370 + */
  371 + afe_alwayson_clampingmode();
  372 +}
drivers/video/mxc_vadc.h
Diff comments   View file @ 99977a1
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef MXC_VADC_H
  8 +#define MXC_VADC_H
  9 +
  10 +/*** define base address ***/
  11 +#define VDEC_BASE vdec_regbase
  12 +#define AFE_BASE vafe_regbase
  13 +
  14 +/* AFE - Register offsets */
  15 +#define AFE_BLOCK_ID_OFFSET 0x00000000
  16 +#define AFE_PDBUF_OFFSET 0x00000004
  17 +#define AFE_SWRST_OFFSET 0x00000008
  18 +#define AFE_TSTSEL_OFFSET 0x0000000c
  19 +#define AFE_TSTMSC_OFFSET 0x00000010
  20 +#define AFE_ENPADIO_OFFSET 0x00000014
  21 +#define AFE_BGREG_OFFSET 0x00000018
  22 +#define AFE_ACCESSAR_ID_OFFSET 0x00000400
  23 +#define AFE_PDADC_OFFSET 0x00000404
  24 +#define AFE_PDSARH_OFFSET 0x00000408
  25 +#define AFE_PDSARL_OFFSET 0x0000040C
  26 +#define AFE_PDADCRFH_OFFSET 0x00000410
  27 +#define AFE_PDADCRFL_OFFSET 0x00000414
  28 +#define AFE_ACCTST_OFFSET 0x00000418
  29 +#define AFE_ADCGN_OFFSET 0x0000041C
  30 +#define AFE_ICTRL_OFFSET 0x00000420
  31 +#define AFE_ICTLSTG_OFFSET 0x00000424
  32 +#define AFE_RCTRLSTG_OFFSET 0x00000428
  33 +#define AFE_TCTRLSTG_OFFSET 0x0000042c
  34 +#define AFE_REFMOD_OFFSET 0x00000430
  35 +#define AFE_REFTRIML_OFFSET 0x00000434
  36 +#define AFE_REFTRIMH_OFFSET 0x00000438
  37 +#define AFE_ADCR_OFFSET 0x0000043c
  38 +#define AFE_DUMMY0_OFFSET 0x00000440
  39 +#define AFE_DUMMY1_OFFSET 0x00000444
  40 +#define AFE_DUMMY2_OFFSET 0x00000448
  41 +#define AFE_DACAMP_OFFSET 0x0000044c
  42 +#define AFE_CLMPTST_OFFSET 0x00000450
  43 +#define AFE_CLMPDAT_OFFSET 0x00000454
  44 +#define AFE_CLMPAMP_OFFSET 0x00000458
  45 +#define AFE_CLAMP_OFFSET 0x0000045c
  46 +#define AFE_INPBUF_OFFSET 0x00000460
  47 +#define AFE_INPFLT_OFFSET 0x00000464
  48 +#define AFE_ADCDGN_OFFSET 0x00000468
  49 +#define AFE_OFFDRV_OFFSET 0x0000046c
  50 +#define AFE_INPCONFIG_OFFSET 0x00000470
  51 +#define AFE_PROGDELAY_OFFSET 0x00000474
  52 +#define AFE_ADCOMT_OFFSET 0x00000478
  53 +#define AFE_ALGDELAY_OFFSET 0x0000047c
  54 +#define AFE_ACC_ID_OFFSET 0x00000800
  55 +#define AFE_ACCSTA_OFFSET 0x00000804
  56 +#define AFE_ACCNOSLI_OFFSET 0x00000808
  57 +#define AFE_ACCCALCON_OFFSET 0x0000080c
  58 +#define AFE_BWEWRICTRL_OFFSET 0x00000810
  59 +#define AFE_SELSLI_OFFSET 0x00000814
  60 +#define AFE_SELBYT_OFFSET 0x00000818
  61 +#define AFE_REDVAL_OFFSET 0x00000820
  62 +#define AFE_WRIBYT_OFFSET 0x00000824
  63 +
  64 +/* AFE Register per module */
  65 +#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET)
  66 +#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET)
  67 +#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET)
  68 +#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET)
  69 +#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET)
  70 +#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET)
  71 +#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET)
  72 +#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET)
  73 +#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET)
  74 +#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET)
  75 +#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET)
  76 +#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET)
  77 +#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET)
  78 +#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET)
  79 +#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET)
  80 +#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET)
  81 +#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET)
  82 +#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET)
  83 +#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET)
  84 +#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET)
  85 +#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET)
  86 +#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET)
  87 +#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET)
  88 +#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET)
  89 +#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET)
  90 +#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET)
  91 +#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET)
  92 +#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET)
  93 +#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET)
  94 +#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET)
  95 +#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET)
  96 +#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET)
  97 +#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET)
  98 +#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET)
  99 +#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET)
  100 +#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET)
  101 +#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET)
  102 +#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET)
  103 +#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET)
  104 +#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET)
  105 +#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET)
  106 +#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET)
  107 +#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET)
  108 +#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET)
  109 +#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET)
  110 +#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET)
  111 +#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET)
  112 +#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET)
  113 +
  114 +/* VDEC - Register offsets */
  115 +#define VDEC_CFC1_OFFSET 0x00000000
  116 +#define VDEC_CFC2_OFFSET 0x00000004
  117 +#define VDEC_BRSTGT_OFFSET 0x00000024
  118 +#define VDEC_HZPOS_OFFSET 0x00000040
  119 +#define VDEC_VRTPOS_OFFSET 0x00000044
  120 +#define VDEC_HVSHIFT_OFFSET 0x00000054
  121 +#define VDEC_HSIGS_OFFSET 0x00000058
  122 +#define VDEC_HSIGE_OFFSET 0x0000005C
  123 +#define VDEC_VSCON1_OFFSET 0x00000060
  124 +#define VDEC_VSCON2_OFFSET 0x00000064
  125 +#define VDEC_YCDEL_OFFSET 0x0000006C
  126 +#define VDEC_AFTCLP_OFFSET 0x00000070
  127 +#define VDEC_DCOFF_OFFSET 0x00000078
  128 +#define VDEC_CSID_OFFSET 0x00000084
  129 +#define VDEC_CBGN_OFFSET 0x00000088
  130 +#define VDEC_CRGN_OFFSET 0x0000008C
  131 +#define VDEC_CNTR_OFFSET 0x00000090
  132 +#define VDEC_BRT_OFFSET 0x00000094
  133 +#define VDEC_HUE_OFFSET 0x00000098
  134 +#define VDEC_CHBTH_OFFSET 0x0000009C
  135 +#define VDEC_SHPIMP_OFFSET 0x000000A4
  136 +#define VDEC_CHPLLIM_OFFSET 0x000000A8
  137 +#define VDEC_VIDMOD_OFFSET 0x000000AC
  138 +#define VDEC_VIDSTS_OFFSET 0x000000B0
  139 +#define VDEC_NOISE_OFFSET 0x000000B4
  140 +#define VDEC_STDDBG_OFFSET 0x000000B8
  141 +#define VDEC_MANOVR_OFFSET 0x000000BC
  142 +#define VDEC_VSSGTH_OFFSET 0x000000C8
  143 +#define VDEC_DBGFBH_OFFSET 0x000000D0
  144 +#define VDEC_DBGFBL_OFFSET 0x000000D4
  145 +#define VDEC_HACTS_OFFSET 0x000000D8
  146 +#define VDEC_HACTE_OFFSET 0x000000DC
  147 +#define VDEC_VACTS_OFFSET 0x000000E0
  148 +#define VDEC_VACTE_OFFSET 0x000000E4
  149 +#define VDEC_HSTIP_OFFSET 0x000000EC
  150 +#define VDEC_BLSCRY_OFFSET 0x000000F4
  151 +#define VDEC_BLSCRCR_OFFSET 0x000000F8
  152 +#define VDEC_BLSCRCB_OFFSET 0x000000FC
  153 +#define VDEC_LMAGC2_OFFSET 0x00000104
  154 +#define VDEC_CHAGC1_OFFSET 0x00000108
  155 +#define VDEC_CHAGC2_OFFSET 0x0000010C
  156 +#define VDEC_MINTH_OFFSET 0x00000114
  157 +#define VDEC_VFRQOH_OFFSET 0x0000011C
  158 +#define VDEC_VFRQOL_OFFSET 0x00000120
  159 +#define VDEC_THSH1_OFFSET 0x00000124
  160 +#define VDEC_THSH2_OFFSET 0x00000128
  161 +#define VDEC_NCHTH_OFFSET 0x0000012C
  162 +#define VDEC_TH1F_OFFSET 0x00000130
  163 +
  164 +/* VDEC Register per module */
  165 +#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET)
  166 +#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET)
  167 +#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET)
  168 +#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET)
  169 +#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET)
  170 +#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET)
  171 +#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET)
  172 +#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET)
  173 +#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET)
  174 +#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET)
  175 +#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET)
  176 +#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET)
  177 +#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET)
  178 +#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET)
  179 +#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET)
  180 +#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET)
  181 +#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET)
  182 +#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET)
  183 +#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET)
  184 +#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET)
  185 +#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET)
  186 +#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET)
  187 +#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET)
  188 +#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET)
  189 +#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET)
  190 +#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET)
  191 +#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET)
  192 +#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET)
  193 +#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET)
  194 +#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET)
  195 +#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET)
  196 +#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET)
  197 +#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET)
  198 +#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET)
  199 +#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET)
  200 +#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET)
  201 +#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET)
  202 +#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET)
  203 +#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET)
  204 +#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET)
  205 +#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET)
  206 +#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET)
  207 +#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET)
  208 +#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET)
  209 +#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET)
  210 +#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET)
  211 +#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET)
  212 +#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET)
  213 +
  214 +#define VDEC_VIDMOD_M625_SHIFT 4
  215 +#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT)
  216 +
  217 +#define VDEC_VIDMOD_PAL_SHIFT 7
  218 +#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT)
  219 +
  220 +struct sensor_data {
  221 + u32 width;
  222 + u32 height;
  223 + u32 pixel_fmt;
  224 + u32 std_id;
  225 +};
  226 +
  227 +void vadc_config(u32 vadc_in);
  228 +void vadc_get_std(struct sensor_data *vadc);
  229 +
  230 +#endif