Eric Lee / smarc-uboot

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Commit 99b47c25d0e2bdc9ebbd685a87456e175581c695

Authored by York Sun
1 parent 5e3f763a4b
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1046ardb: Make NET independent of FMan 

This allows using PCIe NIC without enabling DPAA FMan.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Mingkai Hu <mingkai.hu@nxp.com>

Showing 2 changed files with 10 additions and 7 deletions Side-by-side Diff

board/freescale/ls1046ardb/Makefile
Diff comments   View file @ 99b47c2
... ... @@ -7,7 +7,7 @@
7 7 obj-y += ddr.o
8 8 obj-y += ls1046ardb.o
9 9 ifndef CONFIG_SPL_BUILD
10   -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
  10 +obj-$(CONFIG_NET) += eth.o
11 11 obj-y += cpld.o
12 12 endif
include/configs/ls1046ardb.h
Diff comments   View file @ 99b47c2
... ... @@ -178,18 +178,20 @@
178 178 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
179 179 #endif
180 180  
  181 +#define AQR105_IRQ_MASK 0x80000000
181 182 /* FMan */
182 183 #ifndef SPL_NO_FMAN
183   -#ifdef CONFIG_SYS_DPAA_FMAN
184   -#define CONFIG_FMAN_ENET
  184 +
  185 +#ifdef CONFIG_NET
185 186 #define CONFIG_PHYLIB
186   -#define CONFIG_PHYLIB_10G
187 187 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
188   -
189 188 #define CONFIG_PHY_REALTEK
190   -#define CONFIG_PHY_AQUANTIA
191   -#define AQR105_IRQ_MASK 0x80000000
  189 +#endif
192 190  
  191 +#ifdef CONFIG_SYS_DPAA_FMAN
  192 +#define CONFIG_FMAN_ENET
  193 +#define CONFIG_PHY_AQUANTIA
  194 +#define CONFIG_PHYLIB_10G
193 195 #define RGMII_PHY1_ADDR 0x1
194 196 #define RGMII_PHY2_ADDR 0x2
195 197  
... ... @@ -200,6 +202,7 @@
200 202  
201 203 #define CONFIG_ETHPRIME "FM1@DTSEC3"
202 204 #endif
  205 +
203 206 #endif
204 207  
205 208 /* QSPI device */