Commit 99b97106f3d2ff89af70559fdfa0360ac22c536c

Authored by Pavel Machek
Committed by Tom Rini
1 parent 3ab019e1dc

socfpga: initialize designware ethernet

Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.

Signed-off-by: Pavel Machek <pavel@denx.de>

Showing 4 changed files with 51 additions and 9 deletions Side-by-side Diff

arch/arm/cpu/armv7/socfpga/misc.c
... ... @@ -6,6 +6,8 @@
6 6  
7 7 #include <common.h>
8 8 #include <asm/io.h>
  9 +#include <miiphy.h>
  10 +#include <netdev.h>
9 11  
10 12 DECLARE_GLOBAL_DATA_PTR;
11 13  
... ... @@ -37,5 +39,20 @@
37 39 int misc_init_r(void)
38 40 {
39 41 return 0;
  42 +}
  43 +
  44 +
  45 +/*
  46 + * DesignWare Ethernet initialization
  47 + */
  48 +int cpu_eth_init(bd_t *bis)
  49 +{
  50 +#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
  51 + /* initialize and register the emac */
  52 + return designware_initialize(CONFIG_EMAC_BASE,
  53 + CONFIG_PHY_INTERFACE_MODE);
  54 +#else
  55 + return 0;
  56 +#endif
40 57 }
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
... ... @@ -16,6 +16,8 @@
16 16 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
17 17 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
18 18 #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
  19 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000
  20 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000
19 21  
20 22 #endif /* _SOCFPGA_BASE_ADDRS_H_ */
board/altera/socfpga/socfpga_cyclone5.c
... ... @@ -37,13 +37,4 @@
37 37 icache_enable();
38 38 return 0;
39 39 }
40   -
41   -/*
42   - * DesignWare Ethernet initialization
43   - */
44   -/* We know all the init functions have been run now */
45   -int board_eth_init(bd_t *bis)
46   -{
47   - return 0;
48   -}
include/configs/socfpga_cyclone5.h
... ... @@ -208,6 +208,38 @@
208 208 #define CONFIG_ENV_IS_NOWHERE
209 209  
210 210 /*
  211 + * network support
  212 + */
  213 +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  214 +#define CONFIG_DESIGNWARE_ETH 1
  215 +#endif
  216 +
  217 +#ifdef CONFIG_DESIGNWARE_ETH
  218 +#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
  219 +#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
  220 +/* console support for network */
  221 +#define CONFIG_CMD_DHCP
  222 +#define CONFIG_CMD_MII
  223 +#define CONFIG_CMD_NET
  224 +#define CONFIG_CMD_PING
  225 +/* designware */
  226 +#define CONFIG_NET_MULTI
  227 +#define CONFIG_DW_ALTDESCRIPTOR
  228 +#define CONFIG_DW_SEARCH_PHY
  229 +#define CONFIG_MII
  230 +#define CONFIG_PHY_GIGE
  231 +#define CONFIG_DW_AUTONEG
  232 +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
  233 +#define CONFIG_PHYLIB
  234 +#define CONFIG_PHY_MICREL
  235 +#define CONFIG_PHY_MICREL_KSZ9021
  236 +/* EMAC controller and PHY used */
  237 +#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
  238 +#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
  239 +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
  240 +#endif /* CONFIG_DESIGNWARE_ETH */
  241 +
  242 +/*
211 243 * L4 Watchdog
212 244 */
213 245 #define CONFIG_HW_WATCHDOG