Commit 99d7b0a43ddec619739f38dc6a92777a4595182c

Authored by Xulei
Committed by Andy Fleming
1 parent 57966101c8

powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)

On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.

In formal release document, the errata number should be USB14 instead of USB138.

Signed-off-by: xulei <Lei.Xu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: xulei <B33228@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Showing 4 changed files with 30 additions and 1 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/cmd_errata.c
... ... @@ -255,6 +255,9 @@
255 255 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
256 256 puts("Work-around for Erratum PCIe-A003 enabled\n");
257 257 #endif
  258 +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
  259 + puts("Work-around for Erratum USB14 enabled\n");
  260 +#endif
258 261 return 0;
259 262 }
260 263  
arch/powerpc/cpu/mpc85xx/cpu_init.c
... ... @@ -623,6 +623,20 @@
623 623 }
624 624 #endif
625 625  
  626 +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
  627 + /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
  628 + * multi-bit ECC errors which has impact on performance, so software
  629 + * should disable all ECC reporting from USB1 and USB2.
  630 + */
  631 + if (IS_SVR_REV(get_svr(), 1, 0)) {
  632 + struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
  633 + (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
  634 + setbits_be32(&dcfg->ecccr1,
  635 + (DCSR_DCFG_ECC_DISABLE_USB1 |
  636 + DCSR_DCFG_ECC_DISABLE_USB2));
  637 + }
  638 +#endif
  639 +
626 640 #ifdef CONFIG_FMAN_ENET
627 641 fman_enet_init();
628 642 #endif
arch/powerpc/include/asm/config_mpc85xx.h
... ... @@ -333,6 +333,7 @@
333 333 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
334 334 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
335 335 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  336 +#define CONFIG_SYS_FSL_ERRATUM_USB14
336 337 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
337 338 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
338 339 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
... ... @@ -365,6 +366,7 @@
365 366 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
366 367 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
367 368 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  369 +#define CONFIG_SYS_FSL_ERRATUM_USB14
368 370 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
369 371 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
370 372 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
... ... @@ -442,6 +444,7 @@
442 444 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
443 445 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
444 446 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  447 +#define CONFIG_SYS_FSL_ERRATUM_USB14
445 448 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
446 449 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
447 450 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
... ... @@ -473,7 +476,7 @@
473 476 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
474 477 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
475 478 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
476   -#define CONFIG_SYS_FSL_ERRATUM_USB138
  479 +#define CONFIG_SYS_FSL_ERRATUM_USB14
477 480 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
478 481 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
479 482 #define CONFIG_SYS_FSL_ERRATUM_A004699
arch/powerpc/include/asm/immap_85xx.h
... ... @@ -3161,5 +3161,14 @@
3161 3161 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3162 3162 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3163 3163 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  3164 +
  3165 +#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
  3166 +struct dcsr_dcfg_regs {
  3167 + u8 res_0[0x520];
  3168 + u32 ecccr1;
  3169 +#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
  3170 +#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
  3171 + u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
  3172 +};
3164 3173 #endif /*__IMMAP_85xx__*/