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Commit 99d9c07edc6e0b7b35694992f1cc40b540eec3ce

Authored by Kumar Gala
1 parent 1f82ff4777
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h 

Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 15 changed files with 20 additions and 49 deletions Side-by-side Diff

arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 99d9c07
... ... @@ -2060,8 +2060,17 @@
2060 2060 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2061 2061 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
2062 2062 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
  2063 +#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2063 2064 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
  2065 +#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2064 2066 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
  2067 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
  2068 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
  2069 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
  2070 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
  2071 +#else
  2072 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
  2073 +#endif
2065 2074 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2066 2075 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2067 2076 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
... ... @@ -2137,6 +2146,17 @@
2137 2146 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
2138 2147 #define CONFIG_SYS_FSL_SEC_ADDR \
2139 2148 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  2149 +
  2150 +#define CONFIG_SYS_PCI1_ADDR \
  2151 + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
  2152 +#define CONFIG_SYS_PCI2_ADDR \
  2153 + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
  2154 +#define CONFIG_SYS_PCIE1_ADDR \
  2155 + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
  2156 +#define CONFIG_SYS_PCIE2_ADDR \
  2157 + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
  2158 +#define CONFIG_SYS_PCIE3_ADDR \
  2159 + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
2140 2160  
2141 2161 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
2142 2162 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
include/configs/ATUM8548.h
Diff comments   View file @ 99d9c07
... ... @@ -91,9 +91,6 @@
91 91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
92 92  
93 93 #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
94   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
95   -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
96   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
97 94  
98 95 /* DDR Setup */
99 96 #define CONFIG_FSL_DDR2
include/configs/MPC8536DS.h
Diff comments   View file @ 99d9c07
... ... @@ -125,11 +125,6 @@
125 125 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
126 126 #endif
127 127  
128   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
129   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
130   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
131   -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
132   -
133 128 /* DDR Setup */
134 129 #define CONFIG_VERY_BIG_RAM
135 130 #define CONFIG_FSL_DDR2
include/configs/MPC8544DS.h
Diff comments   View file @ 99d9c07
... ... @@ -79,11 +79,6 @@
79 79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
80 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
81 81  
82   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
83   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
84   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
85   -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
86   -
87 82 /* DDR Setup */
88 83 #define CONFIG_FSL_DDR2
89 84 #undef CONFIG_FSL_DDR_INTERACTIVE
include/configs/MPC8548CDS.h
Diff comments   View file @ 99d9c07
... ... @@ -80,10 +80,6 @@
80 80 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
81 81 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
82 82  
83   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
84   -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
85   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
86   -
87 83 /* DDR Setup */
88 84 #define CONFIG_FSL_DDR2
89 85 #undef CONFIG_FSL_DDR_INTERACTIVE
include/configs/MPC8568MDS.h
Diff comments   View file @ 99d9c07
... ... @@ -75,9 +75,6 @@
75 75 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
76 76 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
77 77  
78   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
79   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
80   -
81 78 /* DDR Setup */
82 79 #define CONFIG_FSL_DDR2
83 80 #undef CONFIG_FSL_DDR_INTERACTIVE
include/configs/MPC8569MDS.h
Diff comments   View file @ 99d9c07
... ... @@ -103,9 +103,6 @@
103 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
104 104 #endif
105 105  
106   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
107   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
108   -
109 106 /* DDR Setup */
110 107 #define CONFIG_FSL_DDR3
111 108 #undef CONFIG_FSL_DDR_INTERACTIVE
include/configs/MPC8572DS.h
Diff comments   View file @ 99d9c07
... ... @@ -89,10 +89,6 @@
89 89 #endif
90 90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
91 91  
92   -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
93   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
94   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
95   -
96 92 /* DDR Setup */
97 93 #define CONFIG_VERY_BIG_RAM
98 94 #define CONFIG_FSL_DDR2
include/configs/P1022DS.h
Diff comments   View file @ 99d9c07
... ... @@ -60,10 +60,6 @@
60 60 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
61 61 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
62 62  
63   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */
64   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */
65   -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */
66   -
67 63 /* DDR Setup */
68 64 #define CONFIG_DDR_SPD
69 65 #define CONFIG_VERY_BIG_RAM
include/configs/P1_P2_RDB.h
Diff comments   View file @ 99d9c07
... ... @@ -129,9 +129,6 @@
129 129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
130 130 #endif
131 131  
132   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
133   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
134   -
135 132 /* DDR Setup */
136 133 #define CONFIG_FSL_DDR2
137 134 #undef CONFIG_FSL_DDR_INTERACTIVE
include/configs/P2020DS.h
Diff comments   View file @ 99d9c07
... ... @@ -90,10 +90,6 @@
90 90 #endif
91 91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
92 92  
93   -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
94   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
95   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
96   -
97 93 /* DDR Setup */
98 94 #define CONFIG_VERY_BIG_RAM
99 95 #define CONFIG_FSL_DDR3 1
include/configs/TQM85xx.h
Diff comments   View file @ 99d9c07
... ... @@ -137,10 +137,6 @@
137 137 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
138 138 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
139 139  
140   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
141   -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
142   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
143   -
144 140 /*
145 141 * DDR Setup
146 142 */
include/configs/XPEDITE5200.h
Diff comments   View file @ 99d9c07
... ... @@ -81,7 +81,6 @@
81 81 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
82 82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
83 83 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
84   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
85 84  
86 85 /*
87 86 * Diagnostics
include/configs/XPEDITE5370.h
Diff comments   View file @ 99d9c07
... ... @@ -99,8 +99,6 @@
99 99 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
100 100 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
101 101 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
102   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
103   -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
104 102  
105 103 /*
106 104 * Diagnostics
include/configs/sbc8548.h
Diff comments   View file @ 99d9c07
... ... @@ -109,10 +109,6 @@
109 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
110 110 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
111 111  
112   -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
113   -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
114   -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
115   -
116 112 /* DDR Setup */
117 113 #define CONFIG_FSL_DDR2
118 114 #undef CONFIG_FSL_DDR_INTERACTIVE