Eric Lee / smarc-uboot | Embedian Git Server

Commit 99e516295f4fae7bc0a1d7efaf3106c5ddd43fad

Authored by Ajay Kumar 2013-01-11 05:06:10 +0800

Committed by Minkyu Kang 2013-01-11 16:15:04 +0800

Exists in master and in 54 other branches

EXYNOS5: Make all display related code dependent on CONFIG_LCD

u-boot compilation fails for smdk5250 when we deselect CONFIG_LCD
from the main config file.

Following error was observed:
drivers/video/libvideo.o: In function `exynos_lcd_init':
/home/ajay/u-boot-samsung/drivers/video/exynos_fb.c:68: undefined reference to `lcd_set_flush_dcache'

This is because exynos video drivers have dependency on CONFIG_LCD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Showing 2 changed files with 4 additions and 0 deletions Inline Diff

board/samsung/smdk5250/smdk5250.c
include/configs/exynos5250-dt.h

board/samsung/smdk5250/smdk5250.c

Diff comments View file @ 99e5162

 /*
  * Copyright (C) 2012 Samsung Electronics
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <i2c.h>
 #include <lcd.h>
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
 #include <asm/arch/sromc.h>
 #include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_USB_EHCI_EXYNOS
 int board_usb_vbus_init(void)
 {
 	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
 						samsung_get_base_gpio_part1();
 	/* Enable VBUS power switch */
 	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
 	/* VBUS turn ON time */
 	mdelay(3);
 	return 0;
 }
 #endif
 int board_init(void)
 {
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 #ifdef CONFIG_EXYNOS_SPI
 	spi_init();
 #endif
 #ifdef CONFIG_USB_EHCI_EXYNOS
 	board_usb_vbus_init();
 #endif
 	return 0;
 }
 int dram_init(void)
 {
 	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
 			+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
 	return 0;
 }
 #if defined(CONFIG_POWER)
 int power_init_board(void)
 {
 	if (pmic_init(I2C_PMIC))
 		return -1;
 	else
 		return 0;
 }
 #endif
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 							PHYS_SDRAM_1_SIZE);
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 							PHYS_SDRAM_2_SIZE);
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 							PHYS_SDRAM_3_SIZE);
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 							PHYS_SDRAM_4_SIZE);
 	gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
 	gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
 							PHYS_SDRAM_5_SIZE);
 	gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
 	gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
 							PHYS_SDRAM_6_SIZE);
 	gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
 	gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
 							PHYS_SDRAM_7_SIZE);
 	gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
 	gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
 							PHYS_SDRAM_8_SIZE);
 }
 #ifdef CONFIG_OF_CONTROL
 static int decode_sromc(const void *blob, struct fdt_sromc *config)
 {
 	int err;
 	int node;
 	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
 	if (node < 0) {
 		debug("Could not find SROMC node\n");
 		return node;
 	}
 	config->bank = fdtdec_get_int(blob, node, "bank", 0);
 	config->width = fdtdec_get_int(blob, node, "width", 2);
 	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
 			FDT_SROM_TIMING_COUNT);
 	if (err < 0) {
 		debug("Could not decode SROMC configuration\n");
 		return -FDT_ERR_NOTFOUND;
 	}
 	return 0;
 }
 #endif
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_SMC911X
 	u32 smc_bw_conf, smc_bc_conf;
 	struct fdt_sromc config;
 	fdt_addr_t base_addr;
 	int node;
 #ifdef CONFIG_OF_CONTROL
 	node = decode_sromc(gd->fdt_blob, &config);
 	if (node < 0) {
 		debug("%s: Could not find sromc configuration\n", __func__);
 		return 0;
 	}
 	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
 	if (node < 0) {
 		debug("%s: Could not find lan9215 configuration\n", __func__);
 		return 0;
 	}
 	/* We now have a node, so any problems from now on are errors */
 	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
 	if (base_addr == FDT_ADDR_T_NONE) {
 		debug("%s: Could not find lan9215 address\n", __func__);
 		return -1;
 	}
 #else
 	/* Non-FDT configuration - bank number and timing parameters*/
 	config.bank = CONFIG_ENV_SROM_BANK;
 	config.width = 2;
 	config.timing[FDT_SROM_TACS] = 0x01;
 	config.timing[FDT_SROM_TCOS] = 0x01;
 	config.timing[FDT_SROM_TACC] = 0x06;
 	config.timing[FDT_SROM_TCOH] = 0x01;
 	config.timing[FDT_SROM_TAH] = 0x0C;
 	config.timing[FDT_SROM_TACP] = 0x09;
 	config.timing[FDT_SROM_PMC] = 0x01;
 	base_addr = CONFIG_SMC911X_BASE;
 #endif
 	/* Ethernet needs data bus width of 16 bits */
 	if (config.width != 2) {
 		debug("%s: Unsupported bus width %d\n", __func__,
 			config.width);
 		return -1;
 	}
 	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 			| SROMC_BYTE_ENABLE(config.bank);
 	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 	/* Select and configure the SROMC bank */
 	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 	return smc911x_initialize(0, base_addr);
 #endif
 	return 0;
 }
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
 	printf("\nBoard: SMDK5250\n");
 	return 0;
 }
 #endif
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
 	int err;
 	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 	if (err) {
 		debug("SDMMC0 not configured\n");
 		return err;
 	}
 	err = s5p_mmc_init(0, 8);
 	return err;
 }
 #endif
 static int board_uart_init(void)
 {
 	int err;
 	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
 	if (err) {
 		debug("UART0 not configured\n");
 		return err;
 	}
 	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
 	if (err) {
 		debug("UART1 not configured\n");
 		return err;
 	}
 	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
 	if (err) {
 		debug("UART2 not configured\n");
 		return err;
 	}
 	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 	if (err) {
 		debug("UART3 not configured\n");
 		return err;
 	}
 	return 0;
 }
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
 	int err;
 	err = board_uart_init();
 	if (err) {
 		debug("UART init failed\n");
 		return err;
 	}
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 	board_i2c_init(gd->fdt_blob);
 #endif
 	return err;
 }
 #endif
+#ifdef CONFIG_LCD
 void cfg_lcd_gpio(void)
 {
 	struct exynos5_gpio_part1 *gpio1 =
 		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	/* For Backlight */
 	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 	s5p_gpio_set_value(&gpio1->b2, 0, 1);
 	/* LCD power on */
 	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 	s5p_gpio_set_value(&gpio1->x1, 5, 1);
 	/* Set Hotplug detect for DP */
 	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 }
 vidinfo_t panel_info = {
 	.vl_freq	= 60,
 	.vl_col		= 2560,
 	.vl_row		= 1600,
 	.vl_width	= 2560,
 	.vl_height	= 1600,
 	.vl_clkp	= CONFIG_SYS_LOW,
 	.vl_hsp		= CONFIG_SYS_LOW,
 	.vl_vsp		= CONFIG_SYS_LOW,
 	.vl_dp		= CONFIG_SYS_LOW,
 	.vl_bpix	= 4,	/* LCD_BPP = 2^4, for output conosle on LCD */
 	/* wDP panel timing infomation */
 	.vl_hspw	= 32,
 	.vl_hbpd	= 80,
 	.vl_hfpd	= 48,
 	.vl_vspw	= 6,
 	.vl_vbpd	= 37,
 	.vl_vfpd	= 3,
 	.vl_cmd_allow_len = 0xf,
 	.win_id		= 3,
 	.cfg_gpio	= cfg_lcd_gpio,
 	.backlight_on	= NULL,
 	.lcd_power_on	= NULL,
 	.reset_lcd	= NULL,
 	.dual_lcd_enabled = 0,
 	.init_delay	= 0,
 	.power_on_delay = 0,
 	.reset_delay	= 0,
 	.interface_mode = FIMD_RGB_INTERFACE,
 	.dp_enabled	= 1,
 };
 static struct edp_device_info edp_info = {
 	.disp_info = {
 		.h_res = 2560,
 		.h_sync_width = 32,
 		.h_back_porch = 80,
 		.h_front_porch = 48,
 		.v_res = 1600,
 		.v_sync_width  = 6,
 		.v_back_porch = 37,
 		.v_front_porch = 3,
 		.v_sync_rate = 60,
 	},
 	.lt_info = {
 		.lt_status = DP_LT_NONE,
 	},
 	.video_info = {
 		.master_mode = 0,
 		.bist_mode = DP_DISABLE,
 		.bist_pattern = NO_PATTERN,
 		.h_sync_polarity = 0,
 		.v_sync_polarity = 0,
 		.interlaced = 0,
 		.color_space = COLOR_RGB,
 		.dynamic_range = VESA,
 		.ycbcr_coeff = COLOR_YCBCR601,
 		.color_depth = COLOR_8,
 	},
 };
 static struct exynos_dp_platform_data dp_platform_data = {
 	.phy_enable	= set_dp_phy_ctrl,
 	.edp_dev_info	= &edp_info,
 };
 void init_panel_info(vidinfo_t *vid)
 {
 	vid->rgb_mode   = MODE_RGB_P,
 	exynos_set_dp_platform_data(&dp_platform_data);
 }
+#endif

include/configs/exynos5250-dt.h

Diff comments View file @ 99e5162

 /*
  * Copyright (C) 2012 Samsung Electronics
  *
  * Configuration settings for the SAMSUNG EXYNOS5250 board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
 #define CONFIG_SAMSUNG			/* in a SAMSUNG core */
 #define CONFIG_S5P			/* S5P Family */
 #define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
 #define CONFIG_SMDK5250			/* which is in a SMDK5250 */
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 /* Enable fdt support for Exynos5250 */
 #define CONFIG_ARCH_DEVICE_TREE		exynos5250
 #define CONFIG_OF_CONTROL
 #define CONFIG_OF_SEPARATE
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_TEXT_BASE		0x43E00000
 /* input clock of PLL: SMDK5250 has 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
 #define MACH_TYPE_SMDK5250		3774
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
 /* Power Down Modes */
 #define S5P_CHECK_SLEEP			0x00000BAD
 #define S5P_CHECK_DIDLE			0xBAD00000
 #define S5P_CHECK_LPA			0xABAD0000
 /* Offset for inform registers */
 #define INFORM0_OFFSET			0x800
 #define INFORM1_OFFSET			0x804
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
 /* select serial console configuration */
 #define CONFIG_SERIAL3			/* use SERIAL 3 */
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
 #define TZPC_BASE_OFFSET		0x10000
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_S5P_SDHCI
 #define CONFIG_BOARD_EARLY_INIT_F
 /* PWM */
 #define CONFIG_PWM
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 /* Command definition*/
 #include <config_cmd_default.h>
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NET
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 /* USB */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
 #define CONFIG_USB_STORAGE
 /* MMC SPL */
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 /* specific .lds file */
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
 #define CONFIG_SPL_TEXT_BASE	0x02023400
 #define CONFIG_SPL_MAX_SIZE	(14 * 1024)
 #define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_PROMPT		"SMDK5250 # "
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_RD_LVL
 #define CONFIG_NR_DRAM_BANKS	8
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
 #define CONFIG_SYS_MONITOR_BASE	0x00000000
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for SMDK5250"
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SECURE_BL1_ONLY
 /* Secure FW size configuration */
 #ifdef	CONFIG_SECURE_BL1_ONLY
 #define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
 #else
 #define	CONFIG_SEC_FW_SIZE		0
 #endif
 /* Configuration of BL1, BL2, ENV Blocks on mmc */
 #define CONFIG_RES_BLOCK_SIZE	(512)
 #define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
 #define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
 #define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
 /* U-boot copy size from boot Media to DRAM.*/
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 #define OM_STAT				(0x1f << 1)
 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
 #define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 #define CONFIG_DOS_PARTITION
 #define CONFIG_IRAM_STACK	0x02050000
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_HARD_I2C
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
 #define CONFIG_DRIVER_S3C24X0_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_MAX_I2C_NUM	8
 #define CONFIG_SYS_I2C_SLAVE    0x0
 #define CONFIG_I2C_EDID
 /* PMIC */
 #define CONFIG_PMIC
 #define CONFIG_PMIC_I2C
 #define CONFIG_PMIC_MAX77686
 /* SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SPI_FLASH
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_EXYNOS_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		50000000
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
 #endif
 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
 #define CONFIG_ENV_SPI_BUS	1
 #define CONFIG_ENV_SPI_MAX_HZ	50000000
 #endif
 /* PMIC */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX77686
 /* SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SPI_FLASH
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_EXYNOS_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		50000000
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
 #endif
 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
 #define CONFIG_ENV_SPI_BUS	1
 #define CONFIG_ENV_SPI_MAX_HZ	50000000
 #endif
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_BASE		0x5000000
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_ENV_SROM_BANK		1
 #endif /*CONFIG_CMD_NET*/
 /* Enable PXE Support */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_CMD_PXE
 #define CONFIG_MENU
 #endif
 /* Sound */
 #define CONFIG_CMD_SOUND
 #ifdef CONFIG_CMD_SOUND
 #define CONFIG_SOUND
 #define CONFIG_I2S
 #define CONFIG_SOUND_WM8994
 #endif
 /* Enable devicetree support */
 #define CONFIG_OF_LIBFDT
 /* SHA hashing */
 #define CONFIG_CMD_HASH
 #define CONFIG_HASH_VERIFY
 #define CONFIG_SHA1
 #define CONFIG_SHA256
 /* Display */
 #define CONFIG_LCD
+#ifdef CONFIG_LCD
 #define CONFIG_EXYNOS_FB
 #define CONFIG_EXYNOS_DP
 #define LCD_XRES			2560
 #define LCD_YRES			1600
 #define LCD_BPP			LCD_COLOR16
+#endif
 #endif	/* __CONFIG_H */