drivers/pci/pci_mvebu: Fix for boards with X4 lanes

Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>

drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Phil Sutter · Stefan Roese
1 parent 7e1e59a7b7
Showing 2 changed files with 16 additions and 0 deletions Side-by-side Diff
arch/arm/mach-mvebu/include/mach/soc.h
drivers/pci/pci_mvebu.c
@@ -96,6 +96,8 @@
 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
  
+#define COMPHY_REFCLK_ALIGNMENT	(MVEBU_REGISTER(0x182f8))
+
 /* BootROM error register (also includes some status infos) */
 #define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
 #define BOOTROM_ERR_MODE_OFFS	28
@@ -155,6 +155,14 @@
 }
 #endif
  
+static int mvebu_pex_unit_is_x4(int pex_idx)
+{
+	int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
+	u32 mask = (0x0f << (pex_unit * 8));
+
+	return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
+}
+
 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
 {
 	u32 val;
@@ -419,6 +427,12 @@
 		writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
  
 		bus = hose->last_busno + 1;
+
+		/* need to skip more for X4 links, otherwise scan will hang */
+		if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+			if (mvebu_pex_unit_is_x4(i))
+				i += 3;
+		}
 	}
 }
...	...	@@ -96,6 +96,8 @@
96	96	#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
97	97	#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
98	98
	99	+#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
	100	+
99	101	/* BootROM error register (also includes some status infos) */
100	102	#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
101	103	#define BOOTROM_ERR_MODE_OFFS 28
...	...	@@ -155,6 +155,14 @@
155	155	}
156	156	#endif
157	157
	158	+static int mvebu_pex_unit_is_x4(int pex_idx)
	159	+{
	160	+ int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
	161	+ u32 mask = (0x0f << (pex_unit * 8));
	162	+
	163	+ return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
	164	+}
	165	+
158	166	static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
159	167	{
160	168	u32 val;
...	...	@@ -419,6 +427,12 @@
419	427	writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
420	428
421	429	bus = hose->last_busno + 1;
	430	+
	431	+ /* need to skip more for X4 links, otherwise scan will hang */
	432	+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
	433	+ if (mvebu_pex_unit_is_x4(i))
	434	+ i += 3;
	435	+ }
422	436	}
423	437	}