NAND boot: MPC8536DS support

MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu · Kumar Gala
1 parent 0735570052
Showing 7 changed files with 307 additions and 18 deletions Side-by-side Diff
MAKEALL
Makefile
board/freescale/mpc8536ds/config.mk
board/freescale/mpc8536ds/tlb.c
include/configs/MPC8536DS.h
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8536ds/nand_boot.c
@@ -387,6 +387,7 @@
 LIST_85xx="		\
 	ATUM8548	\
 	MPC8536DS	\
+	MPC8536DS_NAND	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
@@ -2446,6 +2446,7 @@
 ATUM8548_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
  
+MPC8536DS_NAND_config \
 MPC8536DS_36BIT_config \
 MPC8536DS_config:       unconfig
 	@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
@@ -23,6 +23,13 @@
 #
 # mpc8536ds board
 #
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff80000
 endif
@@ -71,6 +71,17 @@
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 };
  
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
@@ -31,6 +31,12 @@
 #define CONFIG_PHYS_64BIT	1
 #endif
  
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
  
@@ -91,10 +97,21 @@
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
  
 /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CCSRBAR_PHYS	0xfffe00000ull /* physical addr of CCSRBAR */
@@ -103,6 +120,12 @@
 #endif
 #define CONFIG_SYS_IMMR	CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
  
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR + 0x8000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
  
@@ -190,10 +213,10 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
  
-#define CONFIG_SYS_BR0_PRELIM \
+#define CONFIG_FLASH_BR_PRELIM \
 		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 		 | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
  
 #define CONFIG_SYS_BR1_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
@@ -213,6 +236,12 @@
  
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
  
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -265,6 +294,8 @@
 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
 #define PIXIS_LED		0x25    /* LED Register */
  
+#define PIXIS_SPD_SYSCLK	0x7	/* SYSCLK option */
+
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
  
@@ -282,12 +313,21 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
  
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000, \
@@ -298,6 +338,16 @@
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
  
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  
@@ -314,8 +364,17 @@
 		| OR_FCM_TRLX \
 		| OR_FCM_EHTR)
  
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#endif
  
 #define CONFIG_SYS_BR4_PRELIM \
 		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
@@ -536,15 +595,6 @@
 #define CONFIG_CMD_EXT2
 #endif
  
-/*
- * USB
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
 #if defined(CONFIG_TSEC_ENET)
  
 #ifndef CONFIG_NET_MULTI
  
  
@@ -579,14 +629,23 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR		0xfff80000
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
 #else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+	#define CONFIG_ENV_ADDR		0xfff80000
+	#else
+	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#endif
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
  
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+TEXT_BASE := 0xfff00000
+PAD_TO := 0xfff01000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o resetvec.o
+COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+	@rm -f $(obj)cpu_init_early.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+	@rm -f $(obj)cpu_init_nand.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+	@rm -f $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+	@rm -f $(obj)law.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+	@rm -f $(obj)fixed_ivor.S
+	ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+	@rm -f $(obj)start.S
+	ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+	@rm -f $(obj)tlb.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+	@rm -f $(obj)tlb_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+
+u32 sysclk_tbl[] = {
+	33333000, 39999600, 49999500, 66666000,
+	83332500, 99999000, 133332000, 166665000
+};
+
+void board_init_f(ulong bootflag)
+{
+	int px_spd;
+	u32 plat_ratio, bus_clk, sys_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
+
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+	/* for FPGA */
+	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+#else
+#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK];
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	bus_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
...	...	@@ -387,6 +387,7 @@
387	387	LIST_85xx=" \
388	388	ATUM8548 \
389	389	MPC8536DS \
	390	+ MPC8536DS_NAND \
390	391	MPC8540ADS \
391	392	MPC8540EVAL \
392	393	MPC8541CDS \
...	...	@@ -2446,6 +2446,7 @@
2446	2446	ATUM8548_config: unconfig
2447	2447	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
2448	2448
	2449	+MPC8536DS_NAND_config \
2449	2450	MPC8536DS_36BIT_config \
2450	2451	MPC8536DS_config: unconfig
2451	2452	@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
...	...	@@ -23,6 +23,13 @@
23	23	#
24	24	# mpc8536ds board
25	25	#
	26	+ifndef NAND_SPL
	27	+ifeq ($(CONFIG_MK_NAND), y)
	28	+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
	29	+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
	30	+endif
	31	+endif
	32	+
26	33	ifndef TEXT_BASE
27	34	TEXT_BASE = 0xeff80000
28	35	endif
...	...	@@ -71,6 +71,17 @@
71	71	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
72	72	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
73	73	0, 4, BOOKE_PAGESZ_1M, 1),
	74	+
	75	+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	76	+ /* IG - L2SRAM */
	77	+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
	78	+ MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	79	+ 0, 5, BOOKE_PAGESZ_256K, 1),
	80	+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
	81	+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
	82	+ MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	83	+ 0, 6, BOOKE_PAGESZ_256K, 1),
	84	+#endif
74	85	};
75	86
76	87	int num_tlb_entries = ARRAY_SIZE(tlb_table);
...	...	@@ -31,6 +31,12 @@
31	31	#define CONFIG_PHYS_64BIT 1
32	32	#endif
33	33
	34	+#ifdef CONFIG_MK_NAND
	35	+#define CONFIG_NAND_U_BOOT 1
	36	+#define CONFIG_RAMBOOT_NAND 1
	37	+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
	38	+#endif
	39	+
34	40	/* High Level Configuration Options */
35	41	#define CONFIG_BOOKE 1 /* BOOKE */
36	42	#define CONFIG_E500 1 /* BOOKE e500 family */
37	43
...	...	@@ -91,10 +97,21 @@
91	97	#define CONFIG_PANIC_HANG /* do not reset board on panic */
92	98
93	99	/*
	100	+ * Config the L2 Cache as L2 SRAM
	101	+ */
	102	+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	103	+#ifdef CONFIG_PHYS_64BIT
	104	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
	105	+#else
	106	+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	107	+#endif
	108	+#define CONFIG_SYS_L2_SIZE (512 << 10)
	109	+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	110	+
	111	+/*
94	112	* Base addresses -- Note these are effective addresses where the
95	113	* actual resources get mapped (not physical addresses)
96	114	*/
97		-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
98	115	#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
99	116	#ifdef CONFIG_PHYS_64BIT
100	117	#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
...	...	@@ -103,6 +120,12 @@
103	120	#endif
104	121	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
105	122
	123	+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
	124	+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
	125	+#else
	126	+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	127	+#endif
	128	+
106	129	#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
107	130	#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
108	131	#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
109	132
...	...	@@ -190,10 +213,10 @@
190	213	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
191	214	#endif
192	215
193		-#define CONFIG_SYS_BR0_PRELIM \
	216	+#define CONFIG_FLASH_BR_PRELIM \
194	217	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
195	218	\| BR_PS_16 \| BR_V)
196		-#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
	219	+#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
197	220
198	221	#define CONFIG_SYS_BR1_PRELIM \
199	222	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
...	...	@@ -213,6 +236,12 @@
213	236
214	237	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
215	238
	239	+#if defined(CONFIG_SYS_SPL) \|\| defined(CONFIG_RAMBOOT_NAND)
	240	+#define CONFIG_SYS_RAMBOOT
	241	+#else
	242	+#undef CONFIG_SYS_RAMBOOT
	243	+#endif
	244	+
216	245	#define CONFIG_FLASH_CFI_DRIVER
217	246	#define CONFIG_SYS_FLASH_CFI
218	247	#define CONFIG_SYS_FLASH_EMPTY_INFO
...	...	@@ -265,6 +294,8 @@
265	294	#define PIXIS_VWATCH 0x24 /* Watchdog Register */
266	295	#define PIXIS_LED 0x25 /* LED Register */
267	296
	297	+#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
	298	+
268	299	/* old pixis referenced names */
269	300	#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
270	301	#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
271	302
...	...	@@ -282,12 +313,21 @@
282	313	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
283	314	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
284	315
	316	+#ifndef CONFIG_NAND_SPL
285	317	#define CONFIG_SYS_NAND_BASE 0xffa00000
286	318	#ifdef CONFIG_PHYS_64BIT
287	319	#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
288	320	#else
289	321	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
290	322	#endif
	323	+#else
	324	+#define CONFIG_SYS_NAND_BASE 0xfff00000
	325	+#ifdef CONFIG_PHYS_64BIT
	326	+#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
	327	+#else
	328	+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	329	+#endif
	330	+#endif
291	331	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
292	332	CONFIG_SYS_NAND_BASE + 0x40000, \
293	333	CONFIG_SYS_NAND_BASE + 0x80000, \
...	...	@@ -298,6 +338,16 @@
298	338	#define CONFIG_NAND_FSL_ELBC 1
299	339	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
300	340
	341	+/* NAND boot: 4K NAND loader config */
	342	+#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
	343	+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
	344	+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
	345	+#define CONFIG_SYS_NAND_U_BOOT_START \
	346	+ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
	347	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
	348	+#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
	349	+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
	350	+
301	351	/* NAND flash config */
302	352	#define CONFIG_NAND_BR_PRELIM \
303	353	(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
304	354
...	...	@@ -314,8 +364,17 @@
314	364	\| OR_FCM_TRLX \
315	365	\| OR_FCM_EHTR)
316	366
	367	+#ifdef CONFIG_RAMBOOT_NAND
	368	+#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
	369	+#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
	370	+#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	371	+#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	372	+#else
	373	+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	374	+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
317	375	#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
318	376	#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
	377	+#endif
319	378
320	379	#define CONFIG_SYS_BR4_PRELIM \
321	380	(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
...	...	@@ -536,15 +595,6 @@
536	595	#define CONFIG_CMD_EXT2
537	596	#endif
538	597
539		-/*
540		- * USB
541		- */
542		-#define CONFIG_CMD_USB
543		-#define CONFIG_USB_STORAGE
544		-#define CONFIG_USB_EHCI
545		-#define CONFIG_USB_EHCI_FSL
546		-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
547		-
548	598	#if defined(CONFIG_TSEC_ENET)
549	599
550	600	#ifndef CONFIG_NET_MULTI
551	601
552	602
...	...	@@ -579,14 +629,23 @@
579	629	/*
580	630	* Environment
581	631	*/
582		-#define CONFIG_ENV_IS_IN_FLASH 1
583		-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
584		-#define CONFIG_ENV_ADDR 0xfff80000
	632	+
	633	+#if defined(CONFIG_SYS_RAMBOOT)
	634	+#if defined(CONFIG_RAMBOOT_NAND)
	635	+ #define CONFIG_ENV_IS_IN_NAND 1
	636	+ #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	637	+ #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
	638	+#endif
585	639	#else
586		-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	640	+ #define CONFIG_ENV_IS_IN_FLASH 1
	641	+ #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
	642	+ #define CONFIG_ENV_ADDR 0xfff80000
	643	+ #else
	644	+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	645	+ #endif
	646	+ #define CONFIG_ENV_SIZE 0x2000
	647	+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
587	648	#endif
588		-#define CONFIG_ENV_SIZE 0x2000
589		-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
590	649
591	650	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
592	651	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	1	+#
	2	+# (C) Copyright 2007
	3	+# Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	+#
	5	+# Copyright 2009 Freescale Semiconductor, Inc.
	6	+#
	7	+# See file CREDITS for list of people who contributed to this
	8	+# project.
	9	+#
	10	+# This program is free software; you can redistribute it and/or
	11	+# modify it under the terms of the GNU General Public License as
	12	+# published by the Free Software Foundation; either version 2 of
	13	+# the License, or (at your option) any later version.
	14	+#
	15	+# This program is distributed in the hope that it will be useful,
	16	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+# GNU General Public License for more details.
	19	+#
	20	+# You should have received a copy of the GNU General Public License
	21	+# along with this program; if not, write to the Free Software
	22	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+# MA 02111-1307 USA
	24	+#
	25	+
	26	+NAND_SPL := y
	27	+TEXT_BASE := 0xfff00000
	28	+PAD_TO := 0xfff01000
	29	+
	30	+include $(TOPDIR)/config.mk
	31	+
	32	+LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
	33	+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
	34	+AFLAGS += -DCONFIG_NAND_SPL
	35	+CFLAGS += -DCONFIG_NAND_SPL
	36	+
	37	+SOBJS = start.o resetvec.o
	38	+COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
	39	+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
	40	+
	41	+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
	42	+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
	43	+__OBJS := $(SOBJS) $(COBJS)
	44	+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
	45	+
	46	+nandobj := $(OBJTREE)/nand_spl/
	47	+
	48	+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
	49	+
	50	+all: $(obj).depend $(ALL)
	51	+
	52	+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
	53	+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
	54	+
	55	+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
	56	+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
	57	+
	58	+$(nandobj)u-boot-spl: $(OBJS)
	59	+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
	60	+ -Map $(nandobj)u-boot-spl.map \
	61	+ -o $(nandobj)u-boot-spl
	62	+
	63	+# create symbolic links for common files
	64	+
	65	+$(obj)cache.c:
	66	+ @rm -f $(obj)cache.c
	67	+ ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
	68	+
	69	+$(obj)cpu_init_early.c:
	70	+ @rm -f $(obj)cpu_init_early.c
	71	+ ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
	72	+
	73	+$(obj)cpu_init_nand.c:
	74	+ @rm -f $(obj)cpu_init_nand.c
	75	+ ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
	76	+
	77	+$(obj)fsl_law.c:
	78	+ @rm -f $(obj)fsl_law.c
	79	+ ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
	80	+
	81	+$(obj)law.c:
	82	+ @rm -f $(obj)law.c
	83	+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
	84	+
	85	+$(obj)nand_boot_fsl_elbc.c:
	86	+ @rm -f $(obj)nand_boot_fsl_elbc.c
	87	+ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
	88	+ $(obj)nand_boot_fsl_elbc.c
	89	+
	90	+$(obj)ns16550.c:
	91	+ @rm -f $(obj)ns16550.c
	92	+ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
	93	+
	94	+$(obj)resetvec.S:
	95	+ @rm -f $(obj)resetvec.S
	96	+ ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
	97	+
	98	+$(obj)fixed_ivor.S:
	99	+ @rm -f $(obj)fixed_ivor.S
	100	+ ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
	101	+
	102	+$(obj)start.S: $(obj)fixed_ivor.S
	103	+ @rm -f $(obj)start.S
	104	+ ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
	105	+
	106	+$(obj)tlb.c:
	107	+ @rm -f $(obj)tlb.c
	108	+ ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
	109	+
	110	+$(obj)tlb_table.c:
	111	+ @rm -f $(obj)tlb_table.c
	112	+ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
	113	+
	114	+#########################################################################
	115	+
	116	+$(obj)%.o: $(obj)%.S
	117	+ $(CC) $(AFLAGS) -c -o $@ $<
	118	+
	119	+$(obj)%.o: $(obj)%.c
	120	+ $(CC) $(CFLAGS) -c -o $@ $<
	121	+
	122	+# defines $(obj).depend target
	123	+include $(SRCTREE)/rules.mk
	124	+
	125	+sinclude $(obj).depend
	126	+
	127	+#########################################################################
	1	+/*
	2	+ * Copyright 2009 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License as
	6	+ * published by the Free Software Foundation; either version 2 of
	7	+ * the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ *
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ *
	20	+ */
	21	+
	22	+#include <common.h>
	23	+#include <ns16550.h>
	24	+#include <asm/io.h>
	25	+#include <nand.h>
	26	+
	27	+u32 sysclk_tbl[] = {
	28	+ 33333000, 39999600, 49999500, 66666000,
	29	+ 83332500, 99999000, 133332000, 166665000
	30	+};
	31	+
	32	+void board_init_f(ulong bootflag)
	33	+{
	34	+ int px_spd;
	35	+ u32 plat_ratio, bus_clk, sys_clk;
	36	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	37	+ ccsr_lbc_t lbc = (void )CONFIG_SYS_MPC85xx_LBC_ADDR;
	38	+
	39	+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
	40	+ /* for FPGA */
	41	+ out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
	42	+ out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
	43	+#else
	44	+#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
	45	+#endif
	46	+
	47	+ /* initialize selected port with appropriate baud rate */
	48	+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
	49	+ sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK];
	50	+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
	51	+ bus_clk = sys_clk * plat_ratio / 2;
	52	+
	53	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	54	+ bus_clk / 16 / CONFIG_BAUDRATE);
	55	+
	56	+ puts("\nNAND boot... ");
	57	+
	58	+ /* copy code to RAM and jump to it - this should not return */
	59	+ /* NOTE - code has to be copied out of NAND buffer before
	60	+ * other blocks can be read.
	61	+ */
	62	+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
	63	+ CONFIG_SYS_NAND_U_BOOT_RELOC);
	64	+}
	65	+
	66	+void board_init_r(gd_t *gd, ulong dest_addr)
	67	+{
	68	+ nand_boot();
	69	+}
	70	+
	71	+void putc(char c)
	72	+{
	73	+ if (c == '\n')
	74	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
	75	+
	76	+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
	77	+}
	78	+
	79	+void puts(const char *str)
	80	+{
	81	+ while (*str)
	82	+ putc(*str++);
	83	+}