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Commit 9a4018e09a2f2845b509145959deb08e599e87d6

Authored by Matthias Fuchs
Committed by Tom Rini
1 parent 3705726010
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ppc4xx: remove DP405 board 

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

Showing 9 changed files with 2 additions and 481 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 9a4018e
... ... @@ -125,9 +125,6 @@
125 125 config TARGET_CPCI405DT
126 126 bool "Support CPCI405DT"
127 127  
128   -config TARGET_DP405
129   - bool "Support DP405"
130   -
131 128 config TARGET_DU405
132 129 bool "Support DU405"
133 130  
... ... @@ -244,7 +241,6 @@
244 241 source "board/dave/PPChameleonEVB/Kconfig"
245 242 source "board/esd/cpci2dp/Kconfig"
246 243 source "board/esd/cpci405/Kconfig"
247   -source "board/esd/dp405/Kconfig"
248 244 source "board/esd/du405/Kconfig"
249 245 source "board/esd/du440/Kconfig"
250 246 source "board/esd/hh405/Kconfig"
board/esd/dp405/Kconfig
View file @ 9a4018e
1   -if TARGET_DP405
2   -
3   -config SYS_BOARD
4   - default "dp405"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "DP405"
11   -
12   -endif
board/esd/dp405/MAINTAINERS
View file @ 9a4018e
1   -DP405 BOARD
2   -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/dp405/
5   -F: include/configs/DP405.h
6   -F: configs/DP405_defconfig
board/esd/dp405/Makefile
View file @ 9a4018e
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -# Objects for Xilinx JTAG programming (CPLD)
9   -CPLD = ../common/xilinx_jtag/lenval.o \
10   - ../common/xilinx_jtag/micro.o \
11   - ../common/xilinx_jtag/ports.o
12   -
13   -obj-y = dp405.o flash.o ../common/misc.o $(CPLD)
board/esd/dp405/dp405.c
View file @ 9a4018e
1   -/*
2   - * (C) Copyright 2001-2003
3   - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/processor.h>
10   -#include <asm/io.h>
11   -#include <command.h>
12   -#include <malloc.h>
13   -
14   -DECLARE_GLOBAL_DATA_PTR;
15   -
16   -int board_early_init_f (void)
17   -{
18   - /*
19   - * IRQ 0-15 405GP internally generated; active high; level sensitive
20   - * IRQ 16 405GP internally generated; active low; level sensitive
21   - * IRQ 17-24 RESERVED
22   - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
23   - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
24   - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
25   - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
26   - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
27   - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
28   - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
29   - */
30   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
31   - mtdcr(UIC0ER, 0x00000000); /* disable all ints */
32   - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
33   - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
34   - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
35   - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
36   - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
37   -
38   - /*
39   - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
40   - */
41   - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
42   -
43   - /*
44   - * Reset CPLD via GPIO13 (CS4) pin
45   - */
46   - out_be32((void *)GPIO0_OR,
47   - in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
48   - udelay(1000); /* wait 1ms */
49   - out_be32((void *)GPIO0_OR,
50   - in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
51   - udelay(1000); /* wait 1ms */
52   -
53   - return 0;
54   -}
55   -
56   -int misc_init_r (void)
57   -{
58   - /* adjust flash start and offset */
59   - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
60   - gd->bd->bi_flashoffset = 0;
61   -
62   - return (0);
63   -}
64   -
65   -
66   -/*
67   - * Check Board Identity:
68   - */
69   -
70   -int checkboard (void)
71   -{
72   - char str[64];
73   - int i = getenv_f("serial#", str, sizeof(str));
74   - unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
75   - 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
76   - unsigned char id1, id2, rev;
77   -
78   - puts ("Board: ");
79   -
80   - if (i == -1)
81   - puts ("### No HW ID - assuming DP405");
82   - else
83   - puts(str);
84   -
85   - id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
86   - id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
87   -
88   - rev = in_8((void *)0xf0001000);
89   - if (rev & 0x10) /* old DP405 compatibility */
90   - rev = in_8((void *)0xf0000800);
91   -
92   - switch (rev & 0xc0) {
93   - case 0x00:
94   - puts(" (HW=DP405");
95   - break;
96   - case 0x80:
97   - puts(" (HW=DP405/CO");
98   - break;
99   - case 0xc0:
100   - puts(" (HW=DN405");
101   - break;
102   - }
103   - printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
104   -
105   - if ((rev & 0xc0) == 0xc0) {
106   - printf(", C5V=%s",
107   - in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
108   - }
109   - puts(")\n");
110   -
111   - return 0;
112   -}
board/esd/dp405/flash.c
View file @ 9a4018e
1   -/*
2   - * (C) Copyright 2001
3   - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/ppc4xx.h>
10   -#include <asm/processor.h>
11   -
12   -/*
13   - * include common flash code (for esd boards)
14   - */
15   -#include "../common/flash.c"
16   -
17   -/*-----------------------------------------------------------------------
18   - * Functions
19   - */
20   -static ulong flash_get_size (vu_long * addr, flash_info_t * info);
21   -static void flash_get_offsets (ulong base, flash_info_t * info);
22   -
23   -/*-----------------------------------------------------------------------
24   - */
25   -
26   -unsigned long flash_init (void)
27   -{
28   - unsigned long size_b0;
29   - int i;
30   - uint pbcr;
31   - unsigned long base_b0;
32   - int size_val = 0;
33   -
34   - /* Init: no FLASHes known */
35   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
36   - flash_info[i].flash_id = FLASH_UNKNOWN;
37   - }
38   -
39   - /* Static FLASH Bank configuration here - FIXME XXX */
40   -
41   - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
42   -
43   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
44   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
45   - size_b0, size_b0<<20);
46   - }
47   -
48   - /* Setup offsets */
49   - flash_get_offsets (-size_b0, &flash_info[0]);
50   -
51   - /* Re-do sizing to get full correct info */
52   - mtdcr(EBC0_CFGADDR, PB0CR);
53   - pbcr = mfdcr(EBC0_CFGDATA);
54   - mtdcr(EBC0_CFGADDR, PB0CR);
55   - base_b0 = -size_b0;
56   - switch (size_b0) {
57   - case 1 << 20:
58   - size_val = 0;
59   - break;
60   - case 2 << 20:
61   - size_val = 1;
62   - break;
63   - case 4 << 20:
64   - size_val = 2;
65   - break;
66   - case 8 << 20:
67   - size_val = 3;
68   - break;
69   - case 16 << 20:
70   - size_val = 4;
71   - break;
72   - }
73   - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
74   - mtdcr(EBC0_CFGDATA, pbcr);
75   -
76   - /* Monitor protection ON by default */
77   - (void)flash_protect(FLAG_PROTECT_SET,
78   - -CONFIG_SYS_MONITOR_LEN,
79   - 0xffffffff,
80   - &flash_info[0]);
81   -
82   - flash_info[0].size = size_b0;
83   -
84   - return (size_b0);
85   -}
configs/DP405_defconfig
View file @ 9a4018e
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_DP405=y
doc/README.scrapyard
Diff comments   View file @ 9a4018e
... ... @@ -12,6 +12,8 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
  16 +CPCIISER4 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
15 17 CMS700 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
16 18 ASH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
17 19 AR405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
include/configs/DP405.h
View file @ 9a4018e
1   -/*
2   - * (C) Copyright 2001-2003
3   - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_405EP 1 /* This is a PPC405 CPU */
21   -#define CONFIG_DP405 1 /* ...on a DP405 board */
22   -
23   -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
24   -
25   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26   -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
27   -
28   -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
29   -
30   -#define CONFIG_BAUDRATE 9600
31   -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
32   -
33   -#undef CONFIG_BOOTARGS
34   -#undef CONFIG_BOOTCOMMAND
35   -
36   -#define CONFIG_PREBOOT /* enable preboot variable */
37   -
38   -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
39   -
40   -/*
41   - * Command line configuration.
42   - */
43   -#include <config_cmd_default.h>
44   -
45   -#define CONFIG_CMD_BSP
46   -#define CONFIG_CMD_ELF
47   -#define CONFIG_CMD_I2C
48   -#define CONFIG_CMD_EEPROM
49   -
50   -#undef CONFIG_CMD_NET
51   -#undef CONFIG_CMD_NFS
52   -
53   -#undef CONFIG_WATCHDOG /* watchdog disabled */
54   -
55   -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
56   -
57   -#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */
58   -
59   -/*
60   - * Miscellaneous configurable options
61   - */
62   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
63   -
64   -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
65   -
66   -#if defined(CONFIG_CMD_KGDB)
67   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
68   -#else
69   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
70   -#endif
71   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
72   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
73   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
74   -
75   -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
76   -
77   -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
78   -
79   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
80   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
81   -
82   -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
83   -#define CONFIG_SYS_NS16550
84   -#define CONFIG_SYS_NS16550_SERIAL
85   -#define CONFIG_SYS_NS16550_REG_SIZE 1
86   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
87   -
88   -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
89   -#define CONFIG_SYS_BASE_BAUD 691200
90   -
91   -/* The following table includes the supported baudrates */
92   -#define CONFIG_SYS_BAUDRATE_TABLE \
93   - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
94   - 57600, 115200, 230400, 460800, 921600 }
95   -
96   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
97   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
98   -
99   -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
100   -
101   -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
102   -
103   -/*
104   - * For booting Linux, the board info and command line data
105   - * have to be in the first 8 MB of memory, since this is
106   - * the maximum mapped by the Linux kernel during initialization.
107   - */
108   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
109   -/*-----------------------------------------------------------------------
110   - * FLASH organization
111   - */
112   -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
113   -
114   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
115   -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
116   -
117   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
118   -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
119   -
120   -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
121   -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
122   -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
123   -/*
124   - * The following defines are added for buggy IOP480 byte interface.
125   - * All other boards should use the standard values (CPCI405 etc.)
126   - */
127   -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
128   -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
129   -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
130   -
131   -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
132   -
133   -/*-----------------------------------------------------------------------
134   - * Start addresses for the final memory configuration
135   - * (Set up by the startup code)
136   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
137   - */
138   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
139   -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
140   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
141   -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
142   -#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
143   -
144   -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
145   -# define CONFIG_SYS_RAMBOOT 1
146   -#else
147   -# undef CONFIG_SYS_RAMBOOT
148   -#endif
149   -
150   -/*-----------------------------------------------------------------------
151   - * Environment Variable setup
152   - */
153   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
154   -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
155   -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
156   - /* total size of a CAT24WC16 is 2048 bytes */
157   -
158   -/*-----------------------------------------------------------------------
159   - * I2C EEPROM (CAT24WC16) for environment
160   - */
161   -#define CONFIG_SYS_I2C
162   -#define CONFIG_SYS_I2C_PPC4XX
163   -#define CONFIG_SYS_I2C_PPC4XX_CH0
164   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
165   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
166   -
167   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
168   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
169   -/* mask of address bits that overflow into the "EEPROM chip address" */
170   -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
171   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
172   - /* 16 byte page write mode using*/
173   - /* last 4 bits of the address */
174   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
175   -
176   -/*-----------------------------------------------------------------------
177   - * External Bus Controller (EBC) Setup
178   - */
179   -
180   -#define CAN_BA 0xF0000000 /* CAN Base Address */
181   -
182   -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
183   -#define CONFIG_SYS_EBC_PB0AP 0x92015480
184   -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
185   -
186   -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
187   -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
188   -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
189   -
190   -/*-----------------------------------------------------------------------
191   - * FPGA stuff
192   - */
193   -/* FPGA program pin configuration */
194   -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
195   -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
196   -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
197   -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
198   -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
199   -
200   -/*-----------------------------------------------------------------------
201   - * Definitions for initial stack pointer and data area (in data cache)
202   - */
203   -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
204   -#define CONFIG_SYS_TEMP_STACK_OCM 1
205   -
206   -/* On Chip Memory location */
207   -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
208   -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
209   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
210   -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
211   -
212   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
213   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
214   -
215   -/*-----------------------------------------------------------------------
216   - * Definitions for GPIO setup (PPC405EP specific)
217   - *
218   - * GPIO0[0] - External Bus Controller BLAST output
219   - * GPIO0[1-9] - Instruction trace outputs -> GPIO
220   - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
221   - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
222   - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
223   - * GPIO0[24-27] - UART0 control signal inputs/outputs
224   - * GPIO0[28-29] - UART1 data signal input/output
225   - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
226   - */
227   -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
228   -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
229   -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
230   -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
231   -#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */
232   -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
233   -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
234   -#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
235   -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
236   -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
237   -#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
238   -
239   -/*
240   - * Default speed selection (cpu_plb_opb_ebc) in mhz.
241   - * This value will be set if iic boot eprom is disabled.
242   - */
243   -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
244   -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
245   -
246   -#endif /* __CONFIG_H */