Eric Lee / smarc-uboot

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Commit 9a59a130162120551ba8e1b89ebcb37aa8fe3c3a

Authored by Ye.Li
1 parent 5047d3e58d
Exists in smarc-imx-l5.0.0_1.0.0-ga

MLK-9733 imx: mx6sxsabreauto/mx6sxarm2: Fix nand clock glitch 

Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk,
before switching the parent of qspi2_clk_root, we must gate off it.

Signed-off-by: Ye.Li <B37916@freescale.com>

Showing 3 changed files with 18 additions and 3 deletions Side-by-side Diff

board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
Diff comments   View file @ 9a59a13
... ... @@ -500,6 +500,10 @@
500 500 /* config gpmi nand iomux */
501 501 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
502 502  
  503 + /* Disable the QSPI2 root clock */
  504 + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
  505 + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  506 +
503 507 /* config gpmi and bch clock to 100 MHz */
504 508 clrsetbits_le32(&mxc_ccm->cs2cdr,
505 509 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
... ... @@ -515,7 +519,8 @@
515 519 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
516 520 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
517 521 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
518   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  522 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
  523 + MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
519 524  
520 525 /* enable apbh clock gating */
521 526 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c
Diff comments   View file @ 9a59a13
... ... @@ -541,6 +541,10 @@
541 541 /* config gpmi nand iomux */
542 542 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
543 543  
  544 + /* Disable the QSPI2 root clock */
  545 + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
  546 + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  547 +
544 548 /* config gpmi and bch clock to 100 MHz */
545 549 clrsetbits_le32(&mxc_ccm->cs2cdr,
546 550 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
... ... @@ -556,7 +560,8 @@
556 560 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
557 561 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
558 562 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
559   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  563 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
  564 + MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
560 565  
561 566 /* enable apbh clock gating */
562 567 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
Diff comments   View file @ 9a59a13
... ... @@ -288,6 +288,10 @@
288 288 /* config gpmi nand iomux */
289 289 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
290 290  
  291 + /* Disable the QSPI2 root clock */
  292 + clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
  293 + | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  294 +
291 295 /* config gpmi and bch clock to 100 MHz */
292 296 clrsetbits_le32(&mxc_ccm->cs2cdr,
293 297 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
... ... @@ -303,7 +307,8 @@
303 307 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
304 308 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
305 309 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
306   - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  310 + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
  311 + MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
307 312  
308 313 /* enable apbh clock gating */
309 314 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);