Eric Lee / smarc-uboot

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Commit 9acb626fc145e7327f94fd77f927dce08dd978a8

Authored by Heiko Schocher
1 parent 8419c01304
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add MCF5282 support (without preloader) 

relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005

Showing 23 changed files with 2421 additions and 103 deletions Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes since U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Add MCF5282 support (without preloader)
  6 + relocate ichache_State to ram
  7 + u-boot can run from internal flash
  8 + Add EB+MCF-EV123 board support.
  9 + Add m68k Boards to MAKEALL
  10 + Patch from Jens Scharsig, 08 Aug 2005
  11 +
5 12 * MPC5200: enable snooping of DMA transactions on XLB even if no PCI
6 13 is configured; othrwise DMA accesses aren't cache coherent which
7 14 causes for example USB to fail.
... ... @@ -273,6 +273,17 @@
273 273  
274 274 LIST_microblaze="suzaku"
275 275  
  276 +#########################################################################
  277 +## M68K Systems
  278 +#########################################################################
  279 +
  280 +LIST_m68k="\
  281 + cobra5272 \
  282 + EB+MCF-EV123 EB+MCF-EV123_internal \
  283 + M5272C3 M5282EVB \
  284 + TASREG \
  285 +"
  286 +
276 287 #-----------------------------------------------------------------------
277 288  
278 289 #----- for now, just run PPC by default -----
... ... @@ -286,7 +297,7 @@
286 297 ${MAKE} distclean >/dev/null
287 298 ${MAKE} ${target}_config
288 299 ${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
289   - ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
  300 +# ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
290 301 }
291 302  
292 303 #-----------------------------------------------------------------------
... ... @@ -300,6 +311,7 @@
300 311 microblaze| \
301 312 mips|mips_el| \
302 313 nios|nios2| \
  314 + m68k| \
303 315 x86|I486)
304 316 for target in `eval echo '$LIST_'${arg}`
305 317 do
... ... @@ -1313,6 +1313,20 @@
1313 1313 @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds
1314 1314  
1315 1315 #########################################################################
  1316 +# BuS
  1317 +#########################################################################
  1318 +
  1319 +EB+MCF-EV123_config : unconfig
  1320 + @ >include/config.h
  1321 + @echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
  1322 + @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
  1323 +
  1324 +EB+MCF-EV123_internal_config : unconfig
  1325 + @ >include/config.h
  1326 + @echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
  1327 + @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
  1328 +
  1329 +#########################################################################
1316 1330 ## MPC85xx Systems
1317 1331 #########################################################################
1318 1332  
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
Diff comments   View file @ 9acb626
  1 +/*
  2 + * (C) Copyright 2005
  3 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  4 + *
  5 + * (C) Copyright 2000-2003
  6 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <command.h>
  29 +#include "asm/m5282.h"
  30 +#include "VCxK.h"
  31 +
  32 +int checkboard (void)
  33 +{
  34 + puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
  35 +#if (TEXT_BASE == CFG_INT_FLASH_BASE)
  36 + puts (" Boot from Internal FLASH\n");
  37 +#endif
  38 +
  39 + return 0;
  40 +}
  41 +
  42 +long int initdram (int board_type)
  43 +{
  44 + int size,i;
  45 +
  46 + size = 0;
  47 + MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
  48 + | MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4);
  49 + #ifdef CFG_SDRAM_BASE0
  50 +
  51 + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
  52 + | MCFSDRAMC_DACR_CASL(1)
  53 + | MCFSDRAMC_DACR_CBM(3)
  54 + | MCFSDRAMC_DACR_PS_16);
  55 +
  56 + MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M
  57 + | MCFSDRAMC_DMR_V;
  58 +
  59 + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
  60 +
  61 + *(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
  62 + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
  63 + for (i=0; i < 2000; i++)
  64 + asm(" nop");
  65 + mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0)
  66 + | MCFSDRAMC_DACR_IMRS);
  67 + *(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
  68 + size += CFG_SDRAM_SIZE * 1024 * 1024;
  69 + #endif
  70 + #ifdef CFG_SDRAM_BASE1
  71 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
  72 + | MCFSDRAMC_DACR_CASL(1)
  73 + | MCFSDRAMC_DACR_CBM(3)
  74 + | MCFSDRAMC_DACR_PS_16;
  75 +
  76 + MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M
  77 + | MCFSDRAMC_DMR_V;
  78 +
  79 + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
  80 +
  81 + *(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5;
  82 + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
  83 + for (i=0; i < 2000; i++)
  84 + asm(" nop");
  85 + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
  86 + *(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
  87 + size += CFG_SDRAM_SIZE1 * 1024 * 1024;
  88 + #endif
  89 + return size;
  90 +}
  91 +
  92 +
  93 +#if defined(CFG_DRAM_TEST)
  94 +int testdram (void)
  95 +{
  96 + uint *pstart = (uint *) CFG_MEMTEST_START;
  97 + uint *pend = (uint *) CFG_MEMTEST_END;
  98 + uint *p;
  99 +
  100 + printf("SDRAM test phase 1:\n");
  101 + for (p = pstart; p < pend; p++)
  102 + *p = 0xaaaaaaaa;
  103 +
  104 + for (p = pstart; p < pend; p++) {
  105 + if (*p != 0xaaaaaaaa) {
  106 + printf ("SDRAM test fails at: %08x\n", (uint) p);
  107 + return 1;
  108 + }
  109 + }
  110 +
  111 + printf("SDRAM test phase 2:\n");
  112 + for (p = pstart; p < pend; p++)
  113 + *p = 0x55555555;
  114 +
  115 + for (p = pstart; p < pend; p++) {
  116 + if (*p != 0x55555555) {
  117 + printf ("SDRAM test fails at: %08x\n", (uint) p);
  118 + return 1;
  119 + }
  120 + }
  121 +
  122 + printf("SDRAM test passed.\n");
  123 + return 0;
  124 +}
  125 +#endif
  126 +
  127 +int misc_init_r(void)
  128 +{
  129 + init_vcxk();
  130 + return 1;
  131 +}
  132 +
  133 +/*---------------------------------------------------------------------------*/
  134 +
  135 +int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  136 +{
  137 + int rcode = 0;
  138 + ulong source;
  139 +
  140 + switch (argc) {
  141 + case 2:
  142 + source = simple_strtoul(argv[1],NULL,16);
  143 + vcxk_loadimage(source);
  144 + rcode = 0;
  145 + break;
  146 + default:
  147 + printf ("Usage:\n%s\n", cmdtp->usage);
  148 + rcode = 1;
  149 + break;
  150 + }
  151 + return rcode;
  152 +}
  153 +
  154 +/***************************************************/
  155 +
  156 +U_BOOT_CMD(
  157 + vcimage, 2, 0, do_vcimage,
  158 + "vcimage - loads an image to Display\n",
  159 + "vcimage addr\n"
  160 +);
  161 +
  162 +/* EOF EB+MCF-EV123c */
board/BuS/EB+MCF-EV123/Makefile
Diff comments   View file @ 9acb626
  1 +#
  2 +# (C) Copyright 2000-2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
  29 +
  30 +$(LIB): .depend $(OBJS)
  31 + $(AR) crv $@ $(OBJS)
  32 +
  33 +#########################################################################
  34 +
  35 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  36 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  37 +
  38 +sinclude .depend
  39 +
  40 +#########################################################################
board/BuS/EB+MCF-EV123/VCxK.c
Diff comments   View file @ 9acb626
  1 +/*
  2 + * (C) Copyright 2005
  3 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/m5282.h>
  26 +#include "VCxK.h"
  27 +
  28 +vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
  29 +#define VCXK_BWS vcxk_bws
  30 +
  31 +static ulong vcxk_driver;
  32 +
  33 +
  34 +ulong search_vcxk_driver(void);
  35 +void vcxk_cls(void);
  36 +void vcxk_setbrightness(short brightness);
  37 +int vcxk_request(void);
  38 +int vcxk_acknowledge_wait(void);
  39 +void vcxk_clear(void);
  40 +
  41 +int init_vcxk(void)
  42 +{
  43 + VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
  44 + VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
  45 + VIDEO_INVERT_DDR |= VIDEO_INVERT_PIN;
  46 +
  47 + VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
  48 + VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
  49 +
  50 + VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
  51 +
  52 + vcxk_driver = search_vcxk_driver();
  53 + if (vcxk_driver)
  54 + {
  55 + /* use flash resist driver */
  56 + }
  57 + else
  58 + {
  59 + vcxk_cls();
  60 + vcxk_cls();
  61 + vcxk_setbrightness(1000);
  62 + }
  63 + VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
  64 + VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
  65 + VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
  66 + return 1;
  67 +}
  68 +
  69 +void vcxk_loadimage(ulong source)
  70 +{
  71 + int cnt;
  72 + vcxk_acknowledge_wait();
  73 + for (cnt=0; cnt<16384; cnt++)
  74 + {
  75 + VCXK_BWS[cnt*2] = (*(vu_char*) source);
  76 + source++;
  77 + }
  78 + vcxk_request();
  79 +}
  80 +
  81 +void vcxk_cls(void)
  82 +{
  83 + vcxk_acknowledge_wait();
  84 + vcxk_clear();
  85 + vcxk_request();
  86 +}
  87 +
  88 +void vcxk_clear(void)
  89 +{
  90 + int cnt;
  91 + for (cnt=0; cnt<16384; cnt++)
  92 + {
  93 + VCXK_BWS[cnt*2] = 0x00;
  94 + }
  95 +}
  96 +
  97 +void vcxk_setbrightness(short brightness)
  98 +{
  99 + VCXK_BWS[0x8000]=(brightness >> 4) +2;
  100 + VCXK_BWS[0xC000]= (brightness + 23) >> 8;
  101 + VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
  102 +}
  103 +
  104 +int vcxk_request(void)
  105 +{
  106 + if (vcxk_driver)
  107 + {
  108 + /* use flash resist driver */
  109 + }
  110 + else
  111 + {
  112 + VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
  113 + VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
  114 + }
  115 + return 1;
  116 +}
  117 +
  118 +int vcxk_acknowledge_wait(void)
  119 +{
  120 + if (vcxk_driver)
  121 + {
  122 + /* use flash resist driver */
  123 + }
  124 + else
  125 + {
  126 + while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
  127 + }
  128 + return 1;
  129 +}
  130 +
  131 +ulong search_vcxk_driver(void)
  132 +{
  133 + return 0;
  134 +}
  135 +
  136 +/* eof */
board/BuS/EB+MCF-EV123/VCxK.h
Diff comments   View file @ 9acb626
  1 +/*
  2 + * (C) Copyright 2005
  3 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __VCXK_H_
  25 +#define __VCXK_H_
  26 +
  27 +extern int init_vcxk(void);
  28 +void vcxk_loadimage(ulong source);
  29 +
  30 +#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
  31 +#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
  32 +#define VIDEO_ACKNOWLEDGE_PIN 0x0001
  33 +
  34 +#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
  35 +#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
  36 +#define VIDEO_ENABLE_PIN 0x0002
  37 +
  38 +#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
  39 +#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
  40 +#define VIDEO_REQUEST_PIN 0x0004
  41 +
  42 +#define VIDEO_Invert_CFG MCFGPIO_PEPAR
  43 +#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2
  44 +#define VIDEO_INVERT_PORT MCFGPIO_PORTE
  45 +#define VIDEO_INVERT_DDR MCFGPIO_DDRE
  46 +#define VIDEO_INVERT_PIN MCFGPIO_PORT2
  47 +
  48 +#endif
board/BuS/EB+MCF-EV123/cfm_flash.c
Diff comments   View file @ 9acb626
  1 +/*
  2 + * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
  3 + *
  4 + * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#include <common.h>
  26 +#include <asm/m5282.h>
  27 +#include "cfm_flash.h"
  28 +
  29 +#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
  30 +
  31 +#if (CFG_CLK>20000000)
  32 + #define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
  33 +#else
  34 + #define CFM_CLK ((long) CFG_CLK / 400000 + 1)
  35 +#endif
  36 +
  37 +#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
  38 + (CFG_MBAR & 0xC0000000))
  39 +
  40 +void cfm_flash_print_info (flash_info_t * info)
  41 +{
  42 + printf ("Freescale: ");
  43 + switch (info->flash_id & FLASH_TYPEMASK) {
  44 + case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
  45 + printf ("MCF5281 internal FLASH\n");
  46 + break;
  47 + case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
  48 + printf ("MCF5282 internal FLASH\n");
  49 + break;
  50 + default:
  51 + printf ("Unknown Chip Type\n");
  52 + break;
  53 + }
  54 +}
  55 +
  56 +void cfm_flash_init (flash_info_t * info)
  57 +{
  58 + int sector;
  59 + ulong protection;
  60 + MCFCFM_MCR = 0;
  61 + MCFCFM_CLKD = CFM_CLK;
  62 + debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
  63 + CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
  64 + CFG_CLK);
  65 + MCFCFM_SACC = 0;
  66 + MCFCFM_DACC = 0;
  67 +
  68 + if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
  69 + puts("CFM backdoor access is enabled\n");
  70 + if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
  71 + puts("CFM securety is enabled\n");
  72 +
  73 + #ifdef CONFIG_M5281
  74 + info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
  75 + (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
  76 + info->size = 256*1024;
  77 + info->sector_count = 16;
  78 + #else
  79 + info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
  80 + (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
  81 + info->size = 512*1024;
  82 + info->sector_count = 32;
  83 + #endif
  84 + protection = MCFCFM_PROT;
  85 + for (sector = 0; sector < info->sector_count; sector++)
  86 + {
  87 + if (sector == 0)
  88 + {
  89 + info->start[sector] = CFG_INT_FLASH_BASE;
  90 + }
  91 + else
  92 + {
  93 + info->start[sector] = info->start[sector-1] + 0x04000;
  94 + }
  95 + info->protect[sector] = protection & 1;
  96 + protection >>= 1;
  97 + }
  98 +}
  99 +
  100 +int cfm_flash_readycheck(int checkblank)
  101 +{
  102 + int rc;
  103 + unsigned char state;
  104 +
  105 + rc = ERR_OK;
  106 + while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
  107 + state = MCFCFM_USTAT;
  108 + if (state & MCFCFM_USTAT_ACCERR)
  109 + {
  110 + debug ("%s(): CFM access error",__FUNCTION__);
  111 + rc = ERR_PROG_ERROR;
  112 + }
  113 + if (state & MCFCFM_USTAT_PVIOL)
  114 + {
  115 + debug ("%s(): CFM protection violation",__FUNCTION__);
  116 + rc = ERR_PROTECTED;
  117 + }
  118 + if (checkblank)
  119 + {
  120 + if (!(state & MCFCFM_USTAT_BLANK))
  121 + {
  122 + debug ("%s(): CFM erras error",__FUNCTION__);
  123 + rc = ERR_NOT_ERASED;
  124 + }
  125 + }
  126 + MCFCFM_USTAT = state & 0x34; /* reset state */
  127 + return rc;
  128 +}
  129 +
  130 +/* Erase 16KiB = 8 2KiB pages */
  131 +
  132 +int cfm_flash_erase_sector (flash_info_t * info, int sector)
  133 +{
  134 + ulong address;
  135 + int page;
  136 + int rc;
  137 + rc= ERR_OK;
  138 + address = cmf_backdoor_address(info->start[sector]);
  139 + for (page=0; (page<8) && (rc==ERR_OK); page++)
  140 + {
  141 + *(volatile __u32*) address = 0;
  142 + MCFCFM_CMD = MCFCFM_CMD_PGERS;
  143 + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
  144 + rc = cfm_flash_readycheck(0);
  145 + if (rc==ERR_OK)
  146 + {
  147 + *(volatile __u32*) address = 0;
  148 + MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
  149 + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
  150 + rc = cfm_flash_readycheck(1);
  151 + }
  152 + address += 0x800;
  153 + }
  154 + return rc;
  155 +}
  156 +
  157 +int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  158 +{
  159 + int rc;
  160 + ulong dest, data;
  161 +
  162 + rc = ERR_OK;
  163 + if (addr & 3)
  164 + {
  165 + debug ("Byte and Word alignment not supported\n");
  166 + rc = ERR_ALIGN;
  167 + }
  168 + if (cnt & 3)
  169 + {
  170 + debug ("Byte and Word transfer not supported\n");
  171 + rc = ERR_ALIGN;
  172 + }
  173 + dest = cmf_backdoor_address(addr);
  174 + while ((cnt>=4) && (rc == ERR_OK))
  175 + {
  176 + data =*((volatile u32 *) src);
  177 + *(volatile u32*) dest = data;
  178 + MCFCFM_CMD = MCFCFM_CMD_PGM;
  179 + MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
  180 + rc = cfm_flash_readycheck(0);
  181 + if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
  182 + src +=4;
  183 + dest +=4;
  184 + addr +=4;
  185 + cnt -=4;
  186 + }
  187 + return rc;
  188 +}
  189 +
  190 +#ifdef CFG_FLASH_PROTECTION
  191 +
  192 +int cfm_flash_protect(flash_info_t * info,long sector,int prot)
  193 +{
  194 + int rc;
  195 +
  196 + rc= ERR_OK;
  197 + if (prot)
  198 + {
  199 + MCFCFM_PROT |= (1<<sector);
  200 + info->protect[sector]=1;
  201 + }
  202 + else
  203 + {
  204 + MCFCFM_PROT &= ~(1<<sector);
  205 + info->protect[sector]=0;
  206 + }
  207 + return rc;
  208 +}
  209 +
  210 +#endif
  211 +
  212 +#endif
board/BuS/EB+MCF-EV123/cfm_flash.h
Diff comments   View file @ 9acb626
  1 +/*
  2 + * Basic Flash Driver for Freescale MCF 5282 internal FLASH
  3 + *
  4 + * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#ifndef __CFM_FLASH_H_
  26 +#define __CFM_FLASH_H_
  27 +
  28 +#define FREESCALE_MANUFACT 0xFACFFACF
  29 +#define FREESCALE_ID_MCF5281 0x5281
  30 +#define FREESCALE_ID_MCF5282 0x5282
  31 +
  32 +extern void cfm_flash_print_info (flash_info_t * info);
  33 +extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
  34 +extern void cfm_flash_init (flash_info_t * info);
  35 +extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
  36 +#ifdef CFG_FLASH_PROTECTION
  37 +extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
  38 +#endif
  39 +
  40 +#endif
board/BuS/EB+MCF-EV123/config.mk
Diff comments   View file @ 9acb626
  1 +#
  2 +# (C) Copyright 2000-2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
  5 +#
  6 +# See file CREDITS for list of people who contributed to this
  7 +# project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or
  10 +# modify it under the terms of the GNU General Public License as
  11 +# published by the Free Software Foundation; either version 2 of
  12 +# the License, or (at your option) any later version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful,
  15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 +# GNU General Public License for more details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License
  20 +# along with this program; if not, write to the Free Software
  21 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 +# MA 02111-1307 USA
  23 +#
  24 +
  25 +sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
  26 +ifndef TEXT_BASE
  27 +TEXT_BASE = 0xFE000000
  28 +endif
board/BuS/EB+MCF-EV123/flash.c
Diff comments   View file @ 9acb626
  1 +/*
  2 + * (C) Copyright 2005
  3 + * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  4 + *
  5 + * Based On
  6 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include "cfm_flash.h"
  29 +
  30 +#define PHYS_FLASH_1 CFG_FLASH_BASE
  31 +#define FLASH_BANK_SIZE 0x200000
  32 +
  33 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  34 +
  35 +void flash_print_info (flash_info_t * info)
  36 +{
  37 + int i;
  38 +
  39 + switch (info->flash_id & FLASH_VENDMASK) {
  40 + case (AMD_MANUFACT & FLASH_VENDMASK):
  41 + printf ("AMD: ");
  42 + switch (info->flash_id & FLASH_TYPEMASK) {
  43 + case (AMD_ID_LV160B & FLASH_TYPEMASK):
  44 + printf ("AM29LV160B (16Bit)\n");
  45 + break;
  46 + default:
  47 + printf ("Unknown Chip Type\n");
  48 + break;
  49 + }
  50 + break;
  51 + case FREESCALE_MANUFACT & FLASH_VENDMASK:
  52 + cfm_flash_print_info (info);
  53 + break;
  54 + default:
  55 + printf ("Unknown Vendor ");
  56 + break;
  57 + }
  58 +
  59 + puts (" Size: ");
  60 + if ((info->size >> 20) > 0)
  61 + {
  62 + printf ("%ld MiB",info->size >> 20);
  63 + }
  64 + else
  65 + {
  66 + printf ("%ld KiB",info->size >> 10);
  67 + }
  68 + printf (" in %d Sectors\n", info->sector_count);
  69 +
  70 + printf (" Sector Start Addresses:");
  71 + for (i = 0; i < info->sector_count; i++) {
  72 + if ((i % 4) == 0) {
  73 + printf ("\n ");
  74 + }
  75 + printf ("%02d: %08lX%s ", i,info->start[i],
  76 + info->protect[i] ? " P" : " ");
  77 + }
  78 + printf ("\n\n");
  79 +}
  80 +
  81 +unsigned long flash_init (void)
  82 +{
  83 + int i, j;
  84 + ulong size = 0;
  85 +
  86 + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
  87 + ulong flashbase = 0;
  88 +
  89 + switch (i)
  90 + {
  91 + case 1:
  92 + flash_info[i].flash_id =
  93 + (AMD_MANUFACT & FLASH_VENDMASK) |
  94 + (AMD_ID_LV160B & FLASH_TYPEMASK);
  95 + flash_info[i].size = FLASH_BANK_SIZE;
  96 + flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
  97 + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
  98 + flashbase = PHYS_FLASH_1;
  99 + for (j = 0; j < flash_info[i].sector_count; j++) {
  100 + if (j == 0) {
  101 + /* 1st is 16 KiB */
  102 + flash_info[i].start[j] = flashbase;
  103 + }
  104 + if ((j >= 1) && (j <= 2)) {
  105 + /* 2nd and 3rd are 8 KiB */
  106 + flash_info[i].start[j] =
  107 + flashbase + 0x4000 + 0x2000 * (j - 1);
  108 + }
  109 + if (j == 3) {
  110 + /* 4th is 32 KiB */
  111 + flash_info[i].start[j] = flashbase + 0x8000;
  112 + }
  113 + if ((j >= 4) && (j <= 34)) {
  114 + /* rest is 256 KiB */
  115 + flash_info[i].start[j] =
  116 + flashbase + 0x10000 + 0x10000 * (j - 4);
  117 + }
  118 + }
  119 + break;
  120 + case 0:
  121 + cfm_flash_init (&flash_info[i]);
  122 + break;
  123 + default:
  124 + panic ("configured to many flash banks!\n");
  125 + }
  126 +
  127 + size += flash_info[i].size;
  128 + }
  129 +
  130 + flash_protect (FLAG_PROTECT_SET,
  131 + CFG_FLASH_BASE,
  132 + CFG_FLASH_BASE + 0xffff, &flash_info[0]);
  133 +
  134 + return size;
  135 +}
  136 +
  137 +#define CMD_READ_ARRAY 0x00F0
  138 +#define CMD_UNLOCK1 0x00AA
  139 +#define CMD_UNLOCK2 0x0055
  140 +#define CMD_ERASE_SETUP 0x0080
  141 +#define CMD_ERASE_CONFIRM 0x0030
  142 +#define CMD_PROGRAM 0x00A0
  143 +#define CMD_UNLOCK_BYPASS 0x0020
  144 +
  145 +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
  146 +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
  147 +
  148 +
  149 +#define BIT_ERASE_DONE 0x0080
  150 +#define BIT_RDY_MASK 0x0080
  151 +#define BIT_PROGRAM_ERROR 0x0020
  152 +#define BIT_TIMEOUT 0x80000000 /* our flag */
  153 +
  154 +#define ERR_READY -1
  155 +
  156 +int amd_flash_erase_sector(flash_info_t * info, int sector)
  157 +{
  158 + int state;
  159 + ulong result;
  160 +
  161 + volatile u16 *addr =
  162 + (volatile u16 *) (info->start[sector]);
  163 +
  164 + MEM_FLASH_ADDR1 = CMD_UNLOCK1;
  165 + MEM_FLASH_ADDR2 = CMD_UNLOCK2;
  166 + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
  167 +
  168 + MEM_FLASH_ADDR1 = CMD_UNLOCK1;
  169 + MEM_FLASH_ADDR2 = CMD_UNLOCK2;
  170 + *addr = CMD_ERASE_CONFIRM;
  171 +
  172 + /* wait until flash is ready */
  173 + state = 0;
  174 + set_timer (0);
  175 +
  176 + do {
  177 + result = *addr;
  178 +
  179 + /* check timeout */
  180 + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
  181 + MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
  182 + state = ERR_TIMOUT;
  183 + }
  184 +
  185 + if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
  186 + state = ERR_READY;
  187 + }
  188 + while (!state);
  189 + if (state == ERR_READY)
  190 + state = ERR_OK;
  191 +
  192 + MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
  193 +
  194 + return state;
  195 +}
  196 +
  197 +int flash_erase (flash_info_t * info, int s_first, int s_last)
  198 +{
  199 + int iflag, cflag;
  200 + int sector;
  201 + int rc;
  202 +
  203 + rc = ERR_OK;
  204 +
  205 + if (info->flash_id == FLASH_UNKNOWN)
  206 + {
  207 + rc = ERR_UNKNOWN_FLASH_TYPE;
  208 + } /* (info->flash_id == FLASH_UNKNOWN) */
  209 +
  210 + if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
  211 + {
  212 + rc = ERR_INVAL;
  213 + }
  214 +
  215 + cflag = icache_status ();
  216 + icache_disable ();
  217 + iflag = disable_interrupts ();
  218 +
  219 + for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
  220 +
  221 + if (info->protect[sector])
  222 + {
  223 + putc('P'); /* protected sector will not erase */
  224 + }
  225 + else
  226 + {
  227 + /* erase on unprotected sector */
  228 + puts("E\b");
  229 + switch (info->flash_id & FLASH_VENDMASK)
  230 + {
  231 + case (AMD_MANUFACT & FLASH_VENDMASK):
  232 + rc = amd_flash_erase_sector(info,sector);
  233 + break;
  234 + case (FREESCALE_MANUFACT & FLASH_VENDMASK):
  235 + rc = cfm_flash_erase_sector(info,sector);
  236 + break;
  237 + default:
  238 + return ERR_UNKNOWN_FLASH_VENDOR;
  239 + }
  240 + putc('.');
  241 + }
  242 + }
  243 + if (rc!=ERR_OK)
  244 + {
  245 + printf ("\n ");
  246 + flash_perror (rc);
  247 + }
  248 + else
  249 + {
  250 + printf (" done\n");
  251 + }
  252 +
  253 + udelay (10000); /* allow flash to settle - wait 10 ms */
  254 +
  255 + if (iflag)
  256 + enable_interrupts ();
  257 +
  258 + if (cflag)
  259 + icache_enable ();
  260 +
  261 + return rc;
  262 +}
  263 +
  264 +volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
  265 +{
  266 + volatile u16 *addr;
  267 + ulong result;
  268 + int cflag, iflag;
  269 + int state;
  270 +
  271 + /*
  272 + * Check if Flash is (sufficiently) erased
  273 + */
  274 + addr = (volatile u16 *) dest;
  275 +
  276 + result = *addr;
  277 + if ((result & data) != data)
  278 + return ERR_NOT_ERASED;
  279 +
  280 + /*
  281 + * Disable interrupts which might cause a timeout
  282 + * here. Remember that our exception vectors are
  283 + * at address 0 in the flash, and we don't want a
  284 + * (ticker) exception to happen while the flash
  285 + * chip is in programming mode.
  286 + */
  287 +
  288 + cflag = icache_status ();
  289 + icache_disable ();
  290 + iflag = disable_interrupts ();
  291 +
  292 + MEM_FLASH_ADDR1 = CMD_UNLOCK1;
  293 + MEM_FLASH_ADDR2 = CMD_UNLOCK2;
  294 + MEM_FLASH_ADDR1 = CMD_PROGRAM;
  295 + *addr = data;
  296 +
  297 + /* arm simple, non interrupt dependent timer */
  298 + set_timer (0);
  299 +
  300 + /* wait until flash is ready */
  301 + state = 0;
  302 + do {
  303 + result = *addr;
  304 +
  305 + /* check timeout */
  306 + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
  307 + state = ERR_TIMOUT;
  308 + }
  309 + if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
  310 + state = ERR_READY;
  311 +
  312 + } while (!state);
  313 +
  314 + *addr = CMD_READ_ARRAY;
  315 +
  316 + if (state == ERR_READY)
  317 + state = ERR_OK;
  318 + if ((*addr != data) && (state != ERR_TIMOUT))
  319 + state = ERR_PROG_ERROR;
  320 +
  321 + if (iflag)
  322 + enable_interrupts ();
  323 +
  324 + if (cflag)
  325 + icache_enable ();
  326 +
  327 + return state;
  328 +}
  329 +
  330 +int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  331 +{
  332 + int rc;
  333 + ulong dest;
  334 + u16 data;
  335 +
  336 + rc = ERR_OK;
  337 + if (addr & 1)
  338 + {
  339 + debug ("Byte alignment not supported\n");
  340 + rc = ERR_ALIGN;
  341 + }
  342 + if (cnt & 1)
  343 + {
  344 + debug ("Byte transfer not supported\n");
  345 + rc = ERR_ALIGN;
  346 + }
  347 +
  348 + dest = addr;
  349 + while ((cnt>=2) && (rc == ERR_OK))
  350 + {
  351 + data =*((volatile u16 *) src);
  352 + rc=amd_write_word (info,dest,data);
  353 + src +=2;
  354 + dest +=2;
  355 + cnt -=2;
  356 + }
  357 + return rc;
  358 +}
  359 +
  360 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  361 +{
  362 + int rc;
  363 +
  364 + switch (info->flash_id & FLASH_VENDMASK)
  365 + {
  366 + case (AMD_MANUFACT & FLASH_VENDMASK):
  367 + rc = amd_flash_write_buff(info,src,addr,cnt);
  368 + break;
  369 + case (FREESCALE_MANUFACT & FLASH_VENDMASK):
  370 + rc = cfm_flash_write_buff(info,src,addr,cnt);
  371 + break;
  372 + default:
  373 + rc = ERR_UNKNOWN_FLASH_VENDOR;
  374 + }
  375 + return rc;
  376 +
  377 +}
  378 +int amd_flash_protect(flash_info_t * info,long sector,int prot)
  379 +{
  380 + int rc;
  381 + rc= ERR_OK;
  382 + if (prot)
  383 + {
  384 + info->protect[sector]=1;
  385 + }
  386 + else
  387 + {
  388 + info->protect[sector]=0;
  389 + }
  390 + return rc;
  391 +}
  392 +
  393 +#ifdef CFG_FLASH_PROTECTION
  394 +
  395 +int flash_real_protect(flash_info_t * info,long sector,int prot)
  396 +{
  397 + int rc;
  398 +
  399 + switch (info->flash_id & FLASH_VENDMASK)
  400 + {
  401 + case (AMD_MANUFACT & FLASH_VENDMASK):
  402 + rc = amd_flash_protect(info,sector,prot);
  403 + break;
  404 + case (FREESCALE_MANUFACT & FLASH_VENDMASK):
  405 + rc = cfm_flash_protect(info,sector,prot);
  406 + break;
  407 + default:
  408 + rc = ERR_UNKNOWN_FLASH_VENDOR;
  409 + }
  410 + return rc;
  411 +}
  412 +
  413 +#endif
board/BuS/EB+MCF-EV123/textbase.mk
Diff comments   View file @ 9acb626
  1 +TEXT_BASE = 0xF0000000
board/BuS/EB+MCF-EV123/u-boot.lds
Diff comments   View file @ 9acb626
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(m68k)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + /* Read-only sections, merged into text segment: */
  31 + . = + SIZEOF_HEADERS;
  32 + .interp : { *(.interp) }
  33 + .hash : { *(.hash) }
  34 + .dynsym : { *(.dynsym) }
  35 + .dynstr : { *(.dynstr) }
  36 + .rel.text : { *(.rel.text) }
  37 + .rela.text : { *(.rela.text) }
  38 + .rel.data : { *(.rel.data) }
  39 + .rela.data : { *(.rela.data) }
  40 + .rel.rodata : { *(.rel.rodata) }
  41 + .rela.rodata : { *(.rela.rodata) }
  42 + .rel.got : { *(.rel.got) }
  43 + .rela.got : { *(.rela.got) }
  44 + .rel.ctors : { *(.rel.ctors) }
  45 + .rela.ctors : { *(.rela.ctors) }
  46 + .rel.dtors : { *(.rel.dtors) }
  47 + .rela.dtors : { *(.rela.dtors) }
  48 + .rel.bss : { *(.rel.bss) }
  49 + .rela.bss : { *(.rela.bss) }
  50 + .rel.plt : { *(.rel.plt) }
  51 + .rela.plt : { *(.rela.plt) }
  52 + .init : { *(.init) }
  53 + .plt : { *(.plt) }
  54 + .text :
  55 + {
  56 + /* WARNING - the following is hand-optimized to fit within */
  57 + /* the sector layout of our flash chips! XXX FIXME XXX */
  58 +
  59 + cpu/mcf52x2/start.o (.text)
  60 + common/dlmalloc.o (.text)
  61 + lib_generic/string.o (.text)
  62 + lib_generic/vsprintf.o (.text)
  63 + lib_generic/crc32.o (.text)
  64 + lib_generic/zlib.o (.text)
  65 +
  66 +/* . = env_offset; */
  67 + common/environment.o(.text)
  68 +
  69 + *(.text)
  70 + *(.fixup)
  71 + *(.got1)
  72 + }
  73 + _etext = .;
  74 + PROVIDE (etext = .);
  75 + .rodata :
  76 + {
  77 + *(.rodata)
  78 + *(.rodata1)
  79 + }
  80 + .fini : { *(.fini) } =0
  81 + .ctors : { *(.ctors) }
  82 + .dtors : { *(.dtors) }
  83 +
  84 + /* Read-write section, merged into data segment: */
  85 + . = (. + 0x00FF) & 0xFFFFFF00;
  86 + _erotext = .;
  87 + PROVIDE (erotext = .);
  88 + .reloc :
  89 + {
  90 + __got_start = .;
  91 + *(.got)
  92 + __got_end = .;
  93 + _GOT2_TABLE_ = .;
  94 + *(.got2)
  95 + _FIXUP_TABLE_ = .;
  96 + *(.fixup)
  97 + }
  98 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  99 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  100 +
  101 + .data :
  102 + {
  103 + *(.data)
  104 + *(.data1)
  105 + *(.sdata)
  106 + *(.sdata2)
  107 + *(.dynamic)
  108 + CONSTRUCTORS
  109 + }
  110 + _edata = .;
  111 + PROVIDE (edata = .);
  112 +
  113 + __u_boot_cmd_start = .;
  114 + .u_boot_cmd : { *(.u_boot_cmd) }
  115 + __u_boot_cmd_end = .;
  116 +
  117 + __start___ex_table = .;
  118 + __ex_table : { *(__ex_table) }
  119 + __stop___ex_table = .;
  120 +
  121 + . = ALIGN(256);
  122 + __init_begin = .;
  123 + .text.init : { *(.text.init) }
  124 + .data.init : { *(.data.init) }
  125 + . = ALIGN(256);
  126 + __init_end = .;
  127 +
  128 + __bss_start = .;
  129 + .bss :
  130 + {
  131 + _sbss = .;
  132 + *(.sbss) *(.scommon)
  133 + *(.dynbss)
  134 + *(.bss)
  135 + *(COMMON)
  136 + . = ALIGN(4);
  137 + _ebss = .;
  138 + }
  139 + _end = . ;
  140 + PROVIDE (end = .);
  141 +}
... ... @@ -112,7 +112,7 @@
112 112 RANLIB = $(CROSS_COMPILE)RANLIB
113 113  
114 114 RELFLAGS= $(PLATFORM_RELFLAGS)
115   -DBGFLAGS= -g #-DDEBUG
  115 +DBGFLAGS= -g # -DDEBUG
116 116 OPTFLAGS= -Os #-fomit-frame-pointer
117 117 ifndef LDSCRIPT
118 118 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
... ... @@ -2,6 +2,10 @@
2 2 * (C) Copyright 2003
3 3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 4 *
  5 + * MCF5282 additionals
  6 + * (C) Copyright 2005
  7 + * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  8 + *
5 9 * See file CREDITS for list of people who contributed to this
6 10 * project.
7 11 *
... ... @@ -31,7 +35,8 @@
31 35 #endif
32 36  
33 37 #ifdef CONFIG_M5282
34   -
  38 +#include <asm/m5282.h>
  39 +#include <asm/immap_5282.h>
35 40 #endif
36 41  
37 42 #ifdef CONFIG_M5249
... ... @@ -75,7 +80,6 @@
75 80 return 0;
76 81 };
77 82  
78   -
79 83 #if defined(CONFIG_WATCHDOG)
80 84 /* Called by macro WATCHDOG_RESET */
81 85 void watchdog_reset (void)
82 86  
... ... @@ -117,11 +121,26 @@
117 121 #ifdef CONFIG_M5282
118 122 int checkcpu (void)
119 123 {
120   - puts ("CPU: MOTOROLA Coldfire MCF5282\n");
  124 + unsigned char resetsource;
  125 +
  126 + printf ("CPU: MOTOROLA Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
  127 + MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
  128 + puts ("Reset: ");
  129 + resetsource = MCFRESET_RSR;
  130 + if (resetsource & MCFRESET_RSR_LOL) puts("Lose-of-lock ");
  131 + if (resetsource & MCFRESET_RSR_LOC) puts("Lose-of-clock ");
  132 + if (resetsource & MCFRESET_RSR_EXT) puts("external ");
  133 + if (resetsource & MCFRESET_RSR_POR) puts("Power-on ");
  134 + if (resetsource & MCFRESET_RSR_WDR) puts("Watchdog ");
  135 + if (resetsource & MCFRESET_RSR_SOFT) puts("Software ");
  136 + if (resetsource & MCFRESET_RSR_LVD) puts("Low-voltage ");
  137 + puts("\n");
121 138 return 0;
122 139 }
123 140  
124   -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
  141 +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  142 +{
  143 + MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
125 144 return 0;
126 145 };
127 146 #endif
cpu/mcf52x2/cpu_init.c
Diff comments   View file @ 9acb626
... ... @@ -2,6 +2,10 @@
2 2 * (C) Copyright 2003
3 3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 4 *
  5 + * MCF5282 additionals
  6 + * (C) Copyright 2005
  7 + * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  8 + *
5 9 * See file CREDITS for list of people who contributed to this
6 10 * project.
7 11 *
8 12  
... ... @@ -135,7 +139,180 @@
135 139 */
136 140 void cpu_init_f (void)
137 141 {
  142 +#ifndef CONFIG_WATCHDOG
  143 + /* disable watchdog if we aren't using it */
  144 + MCFWTM_WCR = 0;
  145 +#endif
138 146  
  147 +#ifndef CONFIG_MONITOR_IS_IN_RAM
  148 + /* Set speed /PLL */
  149 + MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
  150 +
  151 + /* Set up the GPIO ports */
  152 +#ifdef CFG_PEPAR
  153 + MCFGPIO_PEPAR = CFG_PEPAR;
  154 +#endif
  155 +#ifdef CFG_PFPAR
  156 + MCFGPIO_PFPAR = CFG_PFPAR;
  157 +#endif
  158 +#ifdef CFG_PJPAR
  159 + MCFGPIO_PJPAR = CFG_PJPAR;
  160 +#endif
  161 +#ifdef CFG_PSDPAR
  162 + MCFGPIO_PSDPAR = CFG_PSDPAR;
  163 +#endif
  164 +#ifdef CFG_PASPAR
  165 + MCFGPIO_PASPAR = CFG_PASPAR;
  166 +#endif
  167 +#ifdef CFG_PEHLPAR
  168 + MCFGPIO_PEHLPAR = CFG_PEHLPAR;
  169 +#endif
  170 +#ifdef CFG_PQSPAR
  171 + MCFGPIO_PQSPAR = CFG_PQSPAR;
  172 +#endif
  173 +#ifdef CFG_PTCPAR
  174 + MCFGPIO_PTCPAR = CFG_PTCPAR;
  175 +#endif
  176 +#ifdef CFG_PTDPAR
  177 + MCFGPIO_PTDPAR = CFG_PTDPAR;
  178 +#endif
  179 +#ifdef CFG_PUAPAR
  180 + MCFGPIO_PUAPAR = CFG_PUAPAR;
  181 +#endif
  182 +
  183 +#ifdef CFG_DDRUA
  184 + MCFGPIO_DDRUA = CFG_DDRUA;
  185 +#endif
  186 +
  187 + /* This is probably a bad place to setup chip selects, but everyone
  188 + else is doing it! */
  189 +
  190 +#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
  191 + defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
  192 + defined(CFG_CS0_WS)
  193 +
  194 + MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
  195 +
  196 + #if (CFG_CS0_WIDTH == 8)
  197 + #define CFG_CS0_PS MCFCSM_CSCR_PS_8
  198 + #elif (CFG_CS0_WIDTH == 16)
  199 + #define CFG_CS0_PS MCFCSM_CSCR_PS_16
  200 + #elif (CFG_CS0_WIDTH == 32)
  201 + #define CFG_CS0_PS MCFCSM_CSCR_PS_32
  202 + #else
  203 + #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
  204 + #endif
  205 + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
  206 + |CFG_CS0_PS
  207 + |MCFCSM_CSCR_AA;
  208 +
  209 + #if (CFG_CS0_RO != 0)
  210 + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
  211 + |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
  212 + #else
  213 + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
  214 + #endif
  215 +#else
  216 + #waring "Chip Select 0 are not initialized/used"
  217 +#endif
  218 +
  219 +#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
  220 + defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
  221 + defined(CFG_CS1_WS)
  222 +
  223 + MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
  224 +
  225 + #if (CFG_CS1_WIDTH == 8)
  226 + #define CFG_CS1_PS MCFCSM_CSCR_PS_8
  227 + #elif (CFG_CS1_WIDTH == 16)
  228 + #define CFG_CS1_PS MCFCSM_CSCR_PS_16
  229 + #elif (CFG_CS1_WIDTH == 32)
  230 + #define CFG_CS1_PS MCFCSM_CSCR_PS_32
  231 + #else
  232 + #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
  233 + #endif
  234 + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
  235 + |CFG_CS1_PS
  236 + |MCFCSM_CSCR_AA;
  237 +
  238 + #if (CFG_CS1_RO != 0)
  239 + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
  240 + |MCFCSM_CSMR_WP
  241 + |MCFCSM_CSMR_V;
  242 + #else
  243 + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
  244 + |MCFCSM_CSMR_V;
  245 + #endif
  246 +#else
  247 + #warning "Chip Select 1 are not initialized/used"
  248 +#endif
  249 +
  250 +#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
  251 + defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
  252 + defined(CFG_CS2_WS)
  253 +
  254 + MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
  255 +
  256 + #if (CFG_CS2_WIDTH == 8)
  257 + #define CFG_CS2_PS MCFCSM_CSCR_PS_8
  258 + #elif (CFG_CS2_WIDTH == 16)
  259 + #define CFG_CS2_PS MCFCSM_CSCR_PS_16
  260 + #elif (CFG_CS2_WIDTH == 32)
  261 + #define CFG_CS2_PS MCFCSM_CSCR_PS_32
  262 + #else
  263 + #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
  264 + #endif
  265 + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
  266 + |CFG_CS2_PS
  267 + |MCFCSM_CSCR_AA;
  268 +
  269 + #if (CFG_CS2_RO != 0)
  270 + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
  271 + |MCFCSM_CSMR_WP
  272 + |MCFCSM_CSMR_V;
  273 + #else
  274 + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
  275 + |MCFCSM_CSMR_V;
  276 + #endif
  277 +#else
  278 + #warning "Chip Select 2 are not initialized/used"
  279 +#endif
  280 +
  281 +#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
  282 + defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
  283 + defined(CFG_CS3_WS)
  284 +
  285 + MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
  286 +
  287 + #if (CFG_CS3_WIDTH == 8)
  288 + #define CFG_CS3_PS MCFCSM_CSCR_PS_8
  289 + #elif (CFG_CS3_WIDTH == 16)
  290 + #define CFG_CS3_PS MCFCSM_CSCR_PS_16
  291 + #elif (CFG_CS3_WIDTH == 32)
  292 + #define CFG_CS3_PS MCFCSM_CSCR_PS_32
  293 + #else
  294 + #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
  295 + #endif
  296 + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
  297 + |CFG_CS3_PS
  298 + |MCFCSM_CSCR_AA;
  299 +
  300 + #if (CFG_CS3_RO != 0)
  301 + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
  302 + |MCFCSM_CSMR_WP
  303 + |MCFCSM_CSMR_V;
  304 + #else
  305 + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
  306 + |MCFCSM_CSMR_V;
  307 + #endif
  308 +#else
  309 + #warning "Chip Select 3 are not initialized/used"
  310 +#endif
  311 +
  312 +#endif /* CONFIG_MONITOR_IS_IN_RAM */
  313 +
  314 + /* defer enabling cache until boot (see do_go) */
  315 + /* icache_enable(); */
139 316 }
140 317  
141 318 /*
... ... @@ -200,7 +200,9 @@
200 200  
201 201 int eth_init (bd_t * bd)
202 202 {
203   -
  203 +#ifndef CFG_ENET_BD_BASE
  204 + DECLARE_GLOBAL_DATA_PTR;
  205 +#endif
204 206 int i;
205 207 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
206 208  
207 209  
... ... @@ -242,9 +244,13 @@
242 244  
243 245 /* Clear multicast address hash table
244 246 */
  247 +#ifdef CONFIG_M5282
  248 + fecp->fec_ihash_table_high = 0;
  249 + fecp->fec_ihash_table_low = 0;
  250 +#else
245 251 fecp->fec_hash_table_high = 0;
246 252 fecp->fec_hash_table_low = 0;
247   -
  253 +#endif
248 254 /* Set maximum receive buffer size.
249 255 */
250 256 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
251 257  
... ... @@ -256,7 +262,16 @@
256 262 txIdx = 0;
257 263  
258 264 if (!rtx) {
  265 +#ifdef CFG_ENET_BD_BASE
259 266 rtx = (RTXBD *) CFG_ENET_BD_BASE;
  267 +#else
  268 + rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
  269 + (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
  270 + +0xFF)
  271 + & ~0xFF)
  272 + );
  273 + debug("set ENET_DB_BASE to %lX\n",(long) rtx);
  274 +#endif
260 275 }
261 276  
262 277 /*
263 278  
... ... @@ -294,11 +309,13 @@
294 309 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
295 310 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
296 311 #else /* Half duplex mode */
297   - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
  312 + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
  313 + fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
298 314 fecp->fec_x_cntrl = 0;
299 315 #endif
300 316 /* Set MII speed */
301   - fecp->fec_mii_speed = 0x0e;
  317 + fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
  318 + fecp->fec_mii_speed *= 2;
302 319  
303 320 /* Configure port B for MII.
304 321 */
... ... @@ -402,7 +419,7 @@
402 419 */
403 420 udelay (10000); /* wait 10ms */
404 421 }
405   - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  422 + for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
406 423 phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
407 424 #ifdef ET_DEBUG
408 425 printf ("PHY type 0x%x pass %d type ", phytype, pass);
cpu/mcf52x2/serial.c
Diff comments   View file @ 9acb626
... ... @@ -65,6 +65,28 @@
65 65 uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
66 66 uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
67 67 #endif
  68 +#if defined(CONFIG_M5282)
  69 + volatile unsigned char *uartp;
  70 + long clock;
  71 +
  72 + switch (port)
  73 + {
  74 + case 1:
  75 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
  76 + break;
  77 + case 2:
  78 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
  79 + break;
  80 + default:
  81 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
  82 + }
  83 +
  84 + clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */
  85 +
  86 + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
  87 + uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
  88 +
  89 +#endif
68 90 };
69 91  
70 92 void rs_serial_init(int port,int baudrate)
... ... @@ -74,10 +96,19 @@
74 96 /*
75 97 * Reset UART, get it into known state...
76 98 */
77   - if (port == 0)
78   - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
79   - else
80   - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
  99 + switch (port)
  100 + {
  101 + case 1:
  102 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
  103 + break;
  104 + #if defined(CONFIG_M5282)
  105 + case 2:
  106 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
  107 + break;
  108 + #endif
  109 + default:
  110 + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
  111 + }
81 112  
82 113 uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
83 114 uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
... ... @@ -54,8 +54,12 @@
54 54 * These vectors are to catch any un-intended traps.
55 55 */
56 56 _vectors:
57   -
58   -.long 0x00000000, _START
  57 + .long 0x00000000
  58 +#ifndef CONFIG_M5282
  59 +.long _START
  60 +#else
  61 +.long _start - TEXT_BASE
  62 +#endif
59 63 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60 64 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61 65 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62 66  
... ... @@ -96,20 +100,23 @@
96 100  
97 101 .text
98 102  
  103 +
  104 +#if defined(CFG_INT_FLASH_BASE) && \
  105 + (defined(CONFIG_M5282) || defined(CONFIG_M5281))
  106 + #if (TEXT_BASE == CFG_INT_FLASH_BASE)
  107 + .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
  108 + .long 0xFFFFFFFF /* all sectors protected */
  109 + .long 0x00000000 /* supervisor/User restriction */
  110 + .long 0x00000000 /* programm/data space restriction */
  111 + .long 0x00000000 /* Flash security */
  112 + #endif
  113 +#endif
99 114 .globl _start
100 115 _start:
101 116 nop
102 117 nop
103 118 move.w #0x2700,%sr
104 119  
105   - /* if we come from a pre-loader we have no exception table and
106   - * therefore no VBR to set
107   - */
108   -#if !defined(CONFIG_MONITOR_IS_IN_RAM)
109   - move.l #CFG_FLASH_BASE, %d0
110   - movec %d0, %VBR
111   -#endif
112   -
113 120 #if defined(CONFIG_M5272) || defined(CONFIG_M5249)
114 121 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
115 122 move.c %d0, %MBAR
116 123  
117 124  
118 125  
... ... @@ -129,14 +136,44 @@
129 136 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
130 137 move.l %d0, 0x40000000
131 138  
  139 + /* Initialize RAMBAR1: locate SRAM and validate it */
  140 + move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
  141 + movec %d0, %RAMBAR1
  142 +
  143 +#if (TEXT_BASE == CFG_INT_FLASH_BASE)
  144 + /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
  145 +
  146 + move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
  147 + move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
  148 + move.l #(CFG_INIT_RAM_ADDR), %a2
  149 +_copy_flash:
  150 + move.l (%a0)+, (%a2)+
  151 + cmp.l %a0, %a1
  152 + bgt.s _copy_flash
  153 + jmp CFG_INIT_RAM_ADDR
  154 +
  155 +_flashbar_setup:
132 156 /* Initialize FLASHBAR: locate internal Flash and validate it */
133 157 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
134 158 movec %d0, %RAMBAR0
  159 + jmp _after_flashbar_copy.L /* Force jump to absolute address */
  160 +_flashbar_setup_end:
  161 + nop
  162 +_after_flashbar_copy:
  163 +#else
  164 + /* Setup code to initialize FLASHBAR, if start from external Memory */
  165 + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
  166 + movec %d0, %RAMBAR0
  167 +#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
135 168  
136   - /* Initialize RAMBAR1: locate SRAM and validate it */
137   - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
138   - movec %d0, %RAMBAR1
139 169 #endif
  170 + /* if we come from a pre-loader we have no exception table and
  171 + * therefore no VBR to set
  172 + */
  173 +#if !defined(CONFIG_MONITOR_IS_IN_RAM)
  174 + move.l #CFG_FLASH_BASE, %d0
  175 + movec %d0, %VBR
  176 +#endif
140 177  
141 178 /* invalidate and disable cache */
142 179 move.l #0x01000000, %d0 /* Invalidate cache cmd */
... ... @@ -157,7 +194,6 @@
157 194 /* board_init_f() does not return
158 195  
159 196 /*------------------------------------------------------------------------------*/
160   -
161 197 /*
162 198 * void relocate_code (addr_sp, gd, addr_moni)
163 199 *
... ... @@ -180,7 +216,6 @@
180 216 move.l #CFG_MONITOR_BASE, %a1
181 217 move.l #__init_end, %a2
182 218 move.l %a0, %a3
183   -
184 219 /* copy the code to RAM */
185 220 1:
186 221 move.l (%a1)+, (%a3)+
187 222  
... ... @@ -191,14 +226,14 @@
191 226 * We are done. Do not return, instead branch to second part of board
192 227 * initialization, now running from RAM.
193 228 */
194   - move.l %a0, %a1
  229 + move.l %a0, %a1
195 230 add.l #(in_ram - CFG_MONITOR_BASE), %a1
196 231 jmp (%a1)
197 232  
198 233 in_ram:
199 234  
200 235 clear_bss:
201   - /*
  236 + /*
202 237 * Now clear BSS segment
203 238 */
204 239 move.l %a0, %a1
... ... @@ -228,6 +263,23 @@
228 263 cmp.l %a2, %a1
229 264 bne 7b
230 265  
  266 +#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
  267 + /* patch the 3 accesspoints to 3 ichache_state */
  268 + /* quick and dirty */
  269 +
  270 + move.l %a0,%d1
  271 + add.l #(icache_state - CFG_MONITOR_BASE),%d1
  272 + move.l %a0,%a1
  273 + add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
  274 + move.l %d1,(%a1)
  275 + move.l %a0,%a1
  276 + add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
  277 + move.l %d1,(%a1)
  278 + move.l %a0,%a1
  279 + add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
  280 + move.l %d1,(%a1)
  281 +#endif
  282 +
231 283 /* calculate relative jump to board_init_r in ram */
232 284 move.l %a0, %a1
233 285 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
... ... @@ -235,6 +287,10 @@
235 287 /* set parameters for board_init_r */
236 288 move.l %a0,-(%sp) /* dest_addr */
237 289 move.l %d0,-(%sp) /* gd */
  290 + #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
  291 + defined(CFG_HALT_BEFOR_RAM_JUMP)
  292 + halt
  293 + #endif
238 294 jsr (%a1)
239 295  
240 296 /*------------------------------------------------------------------------------*/
... ... @@ -289,6 +345,7 @@
289 345 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
290 346 movec %d0, %CACR /* Enable cache */
291 347 moveq #1, %d0
  348 +icache_state_access_1:
292 349 move.l %d0, icache_state
293 350 rts
294 351 #endif
295 352  
296 353  
... ... @@ -323,18 +380,19 @@
323 380 movec %d0, %ACR0 /* Enable cache */
324 381 movec %d0, %ACR1 /* Enable cache */
325 382 moveq #0, %d0
  383 +icache_state_access_2:
326 384 move.l %d0, icache_state
327 385 rts
328 386  
329 387 .globl icache_status
330 388 icache_status:
  389 +icache_state_access_3:
331 390 move.l icache_state, %d0
332 391 rts
333 392  
334 393 .data
335 394 icache_state:
336   - .long 1
337   -
  395 + .long 0 /* cache is diabled on inirialization */
338 396  
339 397 /*------------------------------------------------------------------------------*/
340 398  
1 1  
2 2 U-Boot for Motorola M68K
3 3  
4   -Last Update: January 12, 2004
5 4 ====================================================================
  5 +History
6 6  
  7 +August 08,2005; Jens Scharsig <esw@bus-elektronik.de>
  8 + MCF5282 implementation without preloader
  9 +January 12, 2004; <josef.baumgartner@telex.de>
  10 +====================================================================
  11 +
7 12 This file contains status information for the port of U-Boot to the
8 13 Motorola M68K series of CPUs.
9 14  
10 15  
11 16  
... ... @@ -33,18 +38,10 @@
33 38 -----------------------------
34 39 CPU specific code is located in: cpu/mcf52x2
35 40  
36   -At the moment the code isn't fully implemented and still needs a pre-loader!
37   -The preloader must initialize the processor and then start u-boot. The board
38   -must be configured for a pre-loader (see 4.1)
  41 +The MCF5282 Port no longer needs a preloader and can place in external or
  42 +internal FLASH.
39 43  
40   -For the preloader, please see
41   -http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
42 44  
43   -U-boot is configured to run at 0x20000 at default. This can be configured by
44   -change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
45   -include/configs/M5282EVB.h.
46   -
47   -
48 45 3. SUPPORTED BOARDs
49 46 -------------------
50 47  
51 48  
... ... @@ -67,7 +64,28 @@
67 64  
68 65 To configure the board, type: make M5272C3_config
69 66  
  67 +At the moment the code isn't fully implemented and still needs a pre-loader!
  68 +The preloader must initialize the processor and then start u-boot. The board
  69 +must be configured for a pre-loader (see 4.1)
70 70  
  71 +For the preloader, please see
  72 +http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
  73 +
  74 +U-boot is configured to run at 0x20000 at default. This can be configured by
  75 +change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
  76 +include/configs/M5282EVB.h.
  77 +
  78 +3.2 BuS EB+MCF-EV123
  79 +---------------------
  80 +
  81 +Board specific code is located in: board/bus/EB+MCF-EV123
  82 +
  83 +To configure the board, type:
  84 +
  85 +make EB+MCF-EV123_config for external FLASH
  86 +make EB+MCF-EV123_internal_config for internal FLASH
  87 +
  88 +
71 89 4. CONFIGURATION OPTIONS/SETTINGS
72 90 ----------------------------------
73 91  
... ... @@ -80,7 +98,6 @@
80 98 the boards config header file (CFG_MONITOR_BASE) and Makefile
81 99 (TEXT_BASE) to the load address.
82 100  
83   -
84 101 4.1 MCF5272 specific Options/Settings
85 102 -------------------------------------
86 103  
87 104  
88 105  
... ... @@ -123,15 +140,28 @@
123 140 CFG_ENET_BD_BASE
124 141 -- defines the base addres of the FEC buffer descriptors
125 142  
  143 +CFG_MFD
  144 + -- defines the PLL Multiplication Factor Devider
  145 + (see table 9-4 of MCF user manual)
  146 +CFG_RFD -- defines the PLL Reduce Frecuency Devider
  147 + (see table 9-4 of MCF user manual)
126 148  
  149 +CFG_CSx_BASE -- defines the base address of chip select x
  150 +CFG_CSx_SIZE -- defines the memory size (address range) of chip select x
  151 +CFG_CSx_WIDTH -- defines the bus with of chip select x
  152 +CFG_CSx_RO -- if set to 0 chip select x is read/wirte
  153 + else chipselct is read only
  154 +CFG_CSx_WS -- defines the number of wait states of chip select x
  155 +
  156 +CFG_PxDDR -- defines the contents of the Data Direction Registers
  157 +CFG_PxDAT -- defines the contents of the Data Registers
  158 +CFG_PXCNT -- defines the contents of the Port Configuration Registers
  159 +
  160 +CFG_PxPAR -- defines the function of ports
  161 +
  162 +
127 163 5. COMPILER
128 164 -----------
129 165 To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used.
130 166 You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
131   -
132   -
133   -Regards,
134   -
135   -Josef
136   -<josef.baumgartner@telex.de>
include/asm-m68k/immap_5282.h
Diff comments   View file @ 9acb626
... ... @@ -25,39 +25,63 @@
25 25 #ifndef __IMMAP_5282__
26 26 #define __IMMAP_5282__
27 27  
  28 +struct sys_ctrl {
  29 + uint ipsbar;
  30 + char res1[4];
  31 + uint rambar;
  32 + char res2[4];
  33 + uchar crsr;
  34 + uchar cwcr;
  35 + uchar lpicr;
  36 + uchar cwsr;
  37 + uint dmareqc;
  38 + char res3[4];
  39 + uint mpark;
28 40  
  41 + /* TODO: finish these */
  42 +};
  43 +
  44 +
  45 +
29 46 /* Fast ethernet controller registers
30 47 */
31 48 typedef struct fec {
32   - uint fec_ecntrl; /* ethernet control register */
33   - uint fec_ievent; /* interrupt event register */
34   - uint fec_imask; /* interrupt mask register */
35   - uint fec_ivec; /* interrupt level and vector status */
36   - uint fec_r_des_active; /* Rx ring updated flag */
37   - uint fec_x_des_active; /* Tx ring updated flag */
38   - uint res3[10]; /* reserved */
39   - uint fec_mii_data; /* MII data register */
40   - uint fec_mii_speed; /* MII speed control register */
41   - uint res4[17]; /* reserved */
42   - uint fec_r_bound; /* end of RAM (read-only) */
43   - uint fec_r_fstart; /* Rx FIFO start address */
44   - uint res5[6]; /* reserved */
45   - uint fec_x_fstart; /* Tx FIFO start address */
46   - uint res7[21]; /* reserved */
47   - uint fec_r_cntrl; /* Rx control register */
48   - uint fec_r_hash; /* Rx hash register */
49   - uint res8[14]; /* reserved */
50   - uint fec_x_cntrl; /* Tx control register */
51   - uint res9[0x9e]; /* reserved */
52   - uint fec_addr_low; /* lower 32 bits of station address */
53   - uint fec_addr_high; /* upper 16 bits of station address */
54   - uint fec_hash_table_high; /* upper 32-bits of hash table */
55   - uint fec_hash_table_low; /* lower 32-bits of hash table */
56   - uint fec_r_des_start; /* beginning of Rx descriptor ring */
57   - uint fec_x_des_start; /* beginning of Tx descriptor ring */
58   - uint fec_r_buff_size; /* Rx buffer size */
59   - uint res2[9]; /* reserved */
60   - uchar fec_fifo[960]; /* fifo RAM */
  49 + uint res1; /* reserved 1000*/
  50 + uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
  51 + uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
  52 + uint res2; /* reserved 100c*/
  53 + uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
  54 + uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
  55 + uint res3[3]; /* reserved 1018*/
  56 + uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
  57 + uint res4[6]; /* reserved 1028*/
  58 + uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
  59 + uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
  60 + /*1044*/
  61 + uint res5[7]; /* reserved 1048*/
  62 + uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
  63 + uint res6[7]; /* reserved 1068*/
  64 + uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
  65 + uint res7[15]; /* reserved 1088*/
  66 + uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
  67 + uint res8[7]; /* reserved 10C8*/
  68 + uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
  69 + uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
  70 + uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
  71 + uint res9[10]; /* reserved 10F0*/
  72 + uint fec_ihash_table_high; /* upper 32-bits of individual hash *//* IAUR */
  73 + uint fec_ihash_table_low; /* lower 32-bits of individual hash *//* IALR */
  74 + uint fec_ghash_table_high; /* upper 32-bits of group hash *//* GAUR */
  75 + uint fec_ghash_table_low; /* lower 32-bits of group hash *//* GALR */
  76 + uint res10[7]; /* reserved 1128*/
  77 + uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
  78 + uint res11; /* reserved 1148*/
  79 + uint fec_r_bound; /* FIFO Receive Bound Register = end of *//* FRBR */
  80 + uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = *//* FRSR */
  81 + uint res12[11]; /* reserved 1154*/
  82 + uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*//* ERDSR */
  83 + uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*//* ETDSR */
  84 + uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
61 85 } fec_t;
62 86  
63 87 #endif /* __IMMAP_5282__ */
include/asm-m68k/m5282.h
Diff comments   View file @ 9acb626
1 1 /*
2 2 * mcf5282.h -- Definitions for Motorola Coldfire 5282
3 3 *
4   - * Based on mcf5282sim.h of uCLinux distribution:
5   - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
6   - *
7 4 * See file CREDITS for list of people who contributed to this
8 5 * project.
9 6 *
10 7  
11 8  
12 9  
13 10  
... ... @@ -34,27 +31,515 @@
34 31  
35 32 #define INT_RAM_SIZE 65536
36 33  
  34 +/* General Purpose I/O Module GPIO */
37 35  
38   -/*
39   - * Define the 5282 SIM register set addresses.
40   - */
41   -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
42   -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
43   -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
44   -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
45   -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
46   -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
47   -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
48   -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
49   -#define MCFINTC_IRLR 0x18 /* */
50   -#define MCFINTC_IACKL 0x19 /* */
51   -#define MCFINTC_ICR0 0x40 /* Base ICR register */
  36 +#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000))
  37 +#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001))
  38 +#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002))
  39 +#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003))
  40 +#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004))
  41 +#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005))
  42 +#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006))
  43 +#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007))
  44 +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008))
  45 +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009))
  46 +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A))
  47 +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B))
  48 +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C))
  49 +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D))
  50 +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E))
  51 +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F))
  52 +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010))
  53 +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011))
52 54  
53   -#define MCFINT_UART0 13 /* Interrupt number for UART0 */
54   -#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
  55 +#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014))
  56 +#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015))
  57 +#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016))
  58 +#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017))
  59 +#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018))
  60 +#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019))
  61 +#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A))
  62 +#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B))
  63 +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C))
  64 +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D))
  65 +#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E))
  66 +#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F))
  67 +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020))
  68 +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021))
  69 +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022))
  70 +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023))
  71 +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024))
  72 +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025))
55 73  
56   -#define MCF5282_GPIO_PUAPAR 0x10005C
  74 +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028))
  75 +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029))
  76 +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A))
  77 +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B))
  78 +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C))
  79 +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D))
  80 +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E))
  81 +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F))
  82 +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030))
  83 +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031))
  84 +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032))
  85 +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033))
  86 +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034))
  87 +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035))
  88 +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036))
  89 +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037))
  90 +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038))
  91 +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039))
57 92  
  93 +#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028))
  94 +#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029))
  95 +#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A))
  96 +#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
  97 +#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
  98 +#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
  99 +#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
  100 +#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
  101 +#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
  102 +#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
  103 +#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
  104 +#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
  105 +#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
  106 +#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
  107 +#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
  108 +#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
  109 +#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
  110 +#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
  111 +
  112 +#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
  113 +#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
  114 +#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
  115 +#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
  116 +#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
  117 +#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
  118 +#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
  119 +#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
  120 +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
  121 +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
  122 +#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
  123 +#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
  124 +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
  125 +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
  126 +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
  127 +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
  128 +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
  129 +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
  130 +
  131 +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
  132 +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
  133 +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
  134 +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
  135 +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
  136 +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
  137 +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
  138 +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
  139 +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
  140 +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
  141 +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
  142 +
  143 +/* Bit level definitions and macros */
  144 +#define MCFGPIO_PORT7 (0x80)
  145 +#define MCFGPIO_PORT6 (0x40)
  146 +#define MCFGPIO_PORT5 (0x20)
  147 +#define MCFGPIO_PORT4 (0x10)
  148 +#define MCFGPIO_PORT3 (0x08)
  149 +#define MCFGPIO_PORT2 (0x04)
  150 +#define MCFGPIO_PORT1 (0x02)
  151 +#define MCFGPIO_PORT0 (0x01)
  152 +#define MCFGPIO_PORT(x) (0x01<<x)
  153 +
  154 +#define MCFGPIO_DDR7 (0x80)
  155 +#define MCFGPIO_DDR6 (0x40)
  156 +#define MCFGPIO_DDR5 (0x20)
  157 +#define MCFGPIO_DDR4 (0x10)
  158 +#define MCFGPIO_DDR3 (0x08)
  159 +#define MCFGPIO_DDR2 (0x04)
  160 +#define MCFGPIO_DDR1 (0x02)
  161 +#define MCFGPIO_DDR0 (0x01)
  162 +#define MCFGPIO_DDR(x) (0x01<<x)
  163 +
  164 +#define MCFGPIO_Px7 (0x80)
  165 +#define MCFGPIO_Px6 (0x40)
  166 +#define MCFGPIO_Px5 (0x20)
  167 +#define MCFGPIO_Px4 (0x10)
  168 +#define MCFGPIO_Px3 (0x08)
  169 +#define MCFGPIO_Px2 (0x04)
  170 +#define MCFGPIO_Px1 (0x02)
  171 +#define MCFGPIO_Px0 (0x01)
  172 +#define MCFGPIO_Px(x) (0x01<<x)
  173 +
  174 +
  175 +#define MCFGPIO_PBCDPAR_PBPA (0x80)
  176 +#define MCFGPIO_PBCDPAR_PCDPA (0x40)
  177 +
  178 +#define MCFGPIO_PEPAR_PEPA7 (0x4000)
  179 +#define MCFGPIO_PEPAR_PEPA6 (0x1000)
  180 +#define MCFGPIO_PEPAR_PEPA5 (0x0400)
  181 +#define MCFGPIO_PEPAR_PEPA4 (0x0100)
  182 +#define MCFGPIO_PEPAR_PEPA3 (0x0040)
  183 +#define MCFGPIO_PEPAR_PEPA2 (0x0010)
  184 +#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
  185 +#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3))
  186 +
  187 +#define MCFGPIO_PFPAR_PFPA7 (0x80)
  188 +#define MCFGPIO_PFPAR_PFPA6 (0x40)
  189 +#define MCFGPIO_PFPAR_PFPA5 (0x20)
  190 +
  191 +#define MCFGPIO_PJPAR_PJPA7 (0x80)
  192 +#define MCFGPIO_PJPAR_PJPA6 (0x40)
  193 +#define MCFGPIO_PJPAR_PJPA5 (0x20)
  194 +#define MCFGPIO_PJPAR_PJPA4 (0x10)
  195 +#define MCFGPIO_PJPAR_PJPA3 (0x08)
  196 +#define MCFGPIO_PJPAR_PJPA2 (0x04)
  197 +#define MCFGPIO_PJPAR_PJPA1 (0x02)
  198 +#define MCFGPIO_PJPAR_PJPA0 (0x01)
  199 +#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x)
  200 +
  201 +#define MCFGPIO_PSDPAR_PSDPA (0x80)
  202 +
  203 +#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10)
  204 +#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8)
  205 +#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6)
  206 +#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4)
  207 +#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2)
  208 +#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3))
  209 +
  210 +#define MCFGPIO_PEHLPAR_PEHPA (0x80)
  211 +#define MCFGPIO_PEHLPAR_PELPA (0x40)
  212 +
  213 +#define MCFGPIO_PQSPAR_PQSPA6 (0x40)
  214 +#define MCFGPIO_PQSPAR_PQSPA5 (0x20)
  215 +#define MCFGPIO_PQSPAR_PQSPA4 (0x10)
  216 +#define MCFGPIO_PQSPAR_PQSPA3 (0x08)
  217 +#define MCFGPIO_PQSPAR_PQSPA2 (0x04)
  218 +#define MCFGPIO_PQSPAR_PQSPA1 (0x02)
  219 +#define MCFGPIO_PQSPAR_PQSPA0 (0x01)
  220 +#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x)
  221 +
  222 +#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6)
  223 +#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4)
  224 +#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2)
  225 +#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3))
  226 +
  227 +#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6)
  228 +#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4)
  229 +#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2)
  230 +#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3))
  231 +
  232 +#define MCFGPIO_PUAPAR_PUAPA3 (0x08)
  233 +#define MCFGPIO_PUAPAR_PUAPA2 (0x04)
  234 +#define MCFGPIO_PUAPAR_PUAPA1 (0x02)
  235 +#define MCFGPIO_PUAPAR_PUAPA0 (0x01)
  236 +
  237 +/* System Conrol Module SCM */
  238 +
  239 +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
  240 +#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
  241 +#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
  242 +#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
  243 +#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013))
  244 +
  245 +#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C))
  246 +#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020))
  247 +#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024))
  248 +#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025))
  249 +#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026))
  250 +#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027))
  251 +#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028))
  252 +#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A))
  253 +#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B))
  254 +#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C))
  255 +#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E))
  256 +#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
  257 +#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
  258 +
  259 +
  260 +#define MCFSCM_CRSR_EXT (0x80)
  261 +#define MCFSCM_CRSR_CWDR (0x20)
  262 +#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
  263 +#define MCFSCM_RAMBAR_BDE (0x00000200)
  264 +
  265 +/* Reset Controller Module RCM */
  266 +
  267 +#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
  268 +#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
  269 +
  270 +#define MCFRESET_RCR_SOFTRST (0x80)
  271 +#define MCFRESET_RCR_FRCRSTOUT (0x40)
  272 +#define MCFRESET_RCR_LVDF (0x10)
  273 +#define MCFRESET_RCR_LVDIE (0x08)
  274 +#define MCFRESET_RCR_LVDRE (0x04)
  275 +#define MCFRESET_RCR_LVDE (0x01)
  276 +
  277 +#define MCFRESET_RSR_LVD (0x40)
  278 +#define MCFRESET_RSR_SOFT (0x20)
  279 +#define MCFRESET_RSR_WDR (0x10)
  280 +#define MCFRESET_RSR_POR (0x08)
  281 +#define MCFRESET_RSR_EXT (0x04)
  282 +#define MCFRESET_RSR_LOC (0x02)
  283 +#define MCFRESET_RSR_LOL (0x01)
  284 +#define MCFRESET_RSR_ALL (0x7F)
  285 +#define MCFRESET_RCR_SOFTRST (0x80)
  286 +#define MCFRESET_RCR_FRCRSTOUT (0x40)
  287 +
  288 +/* Chip Configuration Module CCM */
  289 +
  290 +#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004))
  291 +#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
  292 +#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
  293 +
  294 +
  295 +/* Bit level definitions and macros */
  296 +#define MCFCCM_CCR_LOAD (0x8000)
  297 +#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
  298 +#define MCFCCM_CCR_SZEN (0x0040)
  299 +#define MCFCCM_CCR_PSTEN (0x0020)
  300 +#define MCFCCM_CCR_BME (0x0008)
  301 +#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
  302 +
  303 +#define MCFCCM_CIR_PIN_MASK (0xFF00)
  304 +#define MCFCCM_CIR_PRN_MASK (0x00FF)
  305 +
  306 +/* Clock Module */
  307 +
  308 +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
  309 +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
  310 +
  311 +#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
  312 +#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
  313 +#define MCFCLOCK_SYNSR_LOCK 0x08
  314 +
  315 +#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
  316 +#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
  317 +#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c))
  318 +#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050))
  319 +#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054))
  320 +
  321 +#define MCFSDRAMC_DCR_NAM (0x2000)
  322 +#define MCFSDRAMC_DCR_COC (0x1000)
  323 +#define MCFSDRAMC_DCR_IS (0x0800)
  324 +#define MCFSDRAMC_DCR_RTIM_3 (0x0000)
  325 +#define MCFSDRAMC_DCR_RTIM_6 (0x0200)
  326 +#define MCFSDRAMC_DCR_RTIM_9 (0x0400)
  327 +#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF)
  328 +
  329 +#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000)
  330 +#define MCFSDRAMC_DACR_RE (0x00008000)
  331 +#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12)
  332 +#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8)
  333 +#define MCFSDRAMC_DACR_PS_32 (0x00000000)
  334 +#define MCFSDRAMC_DACR_PS_16 (0x00000020)
  335 +#define MCFSDRAMC_DACR_PS_8 (0x00000010)
  336 +#define MCFSDRAMC_DACR_IP (0x00000008)
  337 +#define MCFSDRAMC_DACR_IMRS (0x00000040)
  338 +
  339 +#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
  340 +#define MCFSDRAMC_DMR_WP (0x00000100)
  341 +#define MCFSDRAMC_DMR_CI (0x00000040)
  342 +#define MCFSDRAMC_DMR_AM (0x00000020)
  343 +#define MCFSDRAMC_DMR_SC (0x00000010)
  344 +#define MCFSDRAMC_DMR_SD (0x00000008)
  345 +#define MCFSDRAMC_DMR_UC (0x00000004)
  346 +#define MCFSDRAMC_DMR_UD (0x00000002)
  347 +#define MCFSDRAMC_DMR_V (0x00000001)
  348 +
  349 +#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
  350 +#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
  351 +#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
  352 +#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
  353 +
  354 +/* Chip SELECT Module CSM */
  355 +#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
  356 +#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084))
  357 +#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a))
  358 +#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C))
  359 +#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090))
  360 +#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096))
  361 +#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098))
  362 +#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C))
  363 +#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2))
  364 +#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4))
  365 +#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8))
  366 +#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE))
  367 +
  368 +#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
  369 +#define MCFCSM_CSMR_WP (1<<8)
  370 +#define MCFCSM_CSMR_V (0x01)
  371 +#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
  372 +#define MCFCSM_CSCR_AA (0x0100)
  373 +#define MCFCSM_CSCR_PS_32 (0x0000)
  374 +#define MCFCSM_CSCR_PS_8 (0x0040)
  375 +#define MCFCSM_CSCR_PS_16 (0x0080)
  376 +
  377 +/*********************************************************************
  378 +*
  379 +* General Purpose Timer (GPT) Module
  380 +*
  381 +*********************************************************************/
  382 +
  383 +#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
  384 +#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001))
  385 +#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002))
  386 +#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003))
  387 +#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004))
  388 +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006))
  389 +#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008))
  390 +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009))
  391 +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B))
  392 +#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C))
  393 +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D))
  394 +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E))
  395 +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F))
  396 +#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010))
  397 +#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012))
  398 +#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014))
  399 +#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016))
  400 +#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018))
  401 +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019))
  402 +#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A))
  403 +#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
  404 +#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
  405 +
  406 +
  407 +#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
  408 +#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
  409 +#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
  410 +#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003))
  411 +#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004))
  412 +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006))
  413 +#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008))
  414 +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009))
  415 +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B))
  416 +#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C))
  417 +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D))
  418 +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E))
  419 +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F))
  420 +#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010))
  421 +#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012))
  422 +#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014))
  423 +#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016))
  424 +#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018))
  425 +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019))
  426 +#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A))
  427 +#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D))
  428 +#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E))
  429 +
  430 +/* Bit level definitions and macros */
  431 +#define MCFGPT_GPTIOS_IOS3 (0x08)
  432 +#define MCFGPT_GPTIOS_IOS2 (0x04)
  433 +#define MCFGPT_GPTIOS_IOS1 (0x02)
  434 +#define MCFGPT_GPTIOS_IOS0 (0x01)
  435 +
  436 +#define MCFGPT_GPTCFORC_FOC3 (0x08)
  437 +#define MCFGPT_GPTCFORC_FOC2 (0x04)
  438 +#define MCFGPT_GPTCFORC_FOC1 (0x02)
  439 +#define MCFGPT_GPTCFORC_FOC0 (0x01)
  440 +
  441 +#define MCFGPT_GPTOC3M_OC3M3 (0x08)
  442 +#define MCFGPT_GPTOC3M_OC3M2 (0x04)
  443 +#define MCFGPT_GPTOC3M_OC3M1 (0x02)
  444 +#define MCFGPT_GPTOC3M_OC3M0 (0x01)
  445 +
  446 +#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04))
  447 +
  448 +#define MCFGPT_GPTSCR1_GPTEN (0x80)
  449 +#define MCFGPT_GPTSCR1_TFFCA (0x10)
  450 +
  451 +#define MCFGPT_GPTTOV3 (0x08)
  452 +#define MCFGPT_GPTTOV2 (0x04)
  453 +#define MCFGPT_GPTTOV1 (0x02)
  454 +#define MCFGPT_GPTTOV0 (0x01)
  455 +
  456 +#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6)
  457 +#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4)
  458 +#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2)
  459 +#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03))
  460 +
  461 +#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6)
  462 +#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4)
  463 +#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2)
  464 +#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03))
  465 +
  466 +#define MCFGPT_GPTIE_C3I (0x08)
  467 +#define MCFGPT_GPTIE_C2I (0x04)
  468 +#define MCFGPT_GPTIE_C1I (0x02)
  469 +#define MCFGPT_GPTIE_C0I (0x01)
  470 +
  471 +#define MCFGPT_GPTSCR2_TOI (0x80)
  472 +#define MCFGPT_GPTSCR2_PUPT (0x20)
  473 +#define MCFGPT_GPTSCR2_RDPT (0x10)
  474 +#define MCFGPT_GPTSCR2_TCRE (0x08)
  475 +#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07))
  476 +
  477 +#define MCFGPT_GPTFLG1_C3F (0x08)
  478 +#define MCFGPT_GPTFLG1_C2F (0x04)
  479 +#define MCFGPT_GPTFLG1_C1F (0x02)
  480 +#define MCFGPT_GPTFLG1_C0F (0x01)
  481 +
  482 +#define MCFGPT_GPTFLG2_TOF (0x80)
  483 +#define MCFGPT_GPTFLG2_C3F (0x08)
  484 +#define MCFGPT_GPTFLG2_C2F (0x04)
  485 +#define MCFGPT_GPTFLG2_C1F (0x02)
  486 +#define MCFGPT_GPTFLG2_C0F (0x01)
  487 +
  488 +#define MCFGPT_GPTPACTL_PAE (0x40)
  489 +#define MCFGPT_GPTPACTL_PAMOD (0x20)
  490 +#define MCFGPT_GPTPACTL_PEDGE (0x10)
  491 +#define MCFGPT_GPTPACTL_CLK_PACLK (0x04)
  492 +#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08)
  493 +#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C)
  494 +#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2)
  495 +#define MCFGPT_GPTPACTL_PAOVI (0x02)
  496 +#define MCFGPT_GPTPACTL_PAI (0x01)
  497 +
  498 +#define MCFGPT_GPTPAFLG_PAOVF (0x02)
  499 +#define MCFGPT_GPTPAFLG_PAIF (0x01)
  500 +
  501 +#define MCFGPT_GPTPORT_PORTT3 (0x08)
  502 +#define MCFGPT_GPTPORT_PORTT2 (0x04)
  503 +#define MCFGPT_GPTPORT_PORTT1 (0x02)
  504 +#define MCFGPT_GPTPORT_PORTT0 (0x01)
  505 +
  506 +#define MCFGPT_GPTDDR_DDRT3 (0x08)
  507 +#define MCFGPT_GPTDDR_DDRT2 (0x04)
  508 +#define MCFGPT_GPTDDR_DDRT1 (0x02)
  509 +#define MCFGPT_GPTDDR_DDRT0 (0x01)
  510 +
  511 +/* Coldfire Flash Module CFM */
  512 +
  513 +#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000))
  514 +#define MCFCFM_MCR_LOCK (0x0400)
  515 +#define MCFCFM_MCR_PVIE (0x0200)
  516 +#define MCFCFM_MCR_AEIE (0x0100)
  517 +#define MCFCFM_MCR_CBEIE (0x0080)
  518 +#define MCFCFM_MCR_CCIE (0x0040)
  519 +#define MCFCFM_MCR_KEYACC (0x0020)
  520 +
  521 +#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002))
  522 +
  523 +#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008))
  524 +#define MCFCFM_SEC_KEYEN (0x80000000)
  525 +#define MCFCFM_SEC_SECSTAT (0x40000000)
  526 +
  527 +#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010))
  528 +#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014))
  529 +#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018))
  530 +#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020))
  531 +#define MCFCFM_USTAT_CBEIF 0x80
  532 +#define MCFCFM_USTAT_CCIF 0x40
  533 +#define MCFCFM_USTAT_PVIOL 0x20
  534 +#define MCFCFM_USTAT_ACCERR 0x10
  535 +#define MCFCFM_USTAT_BLANK 0x04
  536 +
  537 +#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024))
  538 +#define MCFCFM_CMD_ERSVER 0x05
  539 +#define MCFCFM_CMD_PGERSVER 0x06
  540 +#define MCFCFM_CMD_PGM 0x20
  541 +#define MCFCFM_CMD_PGERS 0x40
  542 +#define MCFCFM_CMD_MASERS 0x41
58 543  
59 544 /****************************************************************************/
60 545 #endif /* m5282_h */
include/configs/EB+MCF-EV123.h
Diff comments   View file @ 9acb626
  1 +/*
  2 + * Configuation settings for the BuS EB+MCF-EV123 boards.
  3 + *
  4 + * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#ifndef _CONFIG_EB_MCF_EV123_H_
  26 +#define _CONFIG_EB_MCF_EV123_H_
  27 +
  28 +#define CONFIG_EB_MCF_EV123
  29 +
  30 +#undef DEBUG
  31 +#undef CFG_HALT_BEFOR_RAM_JUMP
  32 +#undef ET_DEBUG
  33 +
  34 +/*
  35 + * High Level Configuration Options (easy to change)
  36 + */
  37 +
  38 +#define CONFIG_MCF52x2 /* define processor family */
  39 +#define CONFIG_M5282 /* define processor type */
  40 +
  41 +#define CONFIG_MISC_INIT_R
  42 +
  43 +#define FEC_ENET
  44 +#define CONFIG_ETHADDR 00:CF:52:82:EB:01
  45 +
  46 +#define CONFIG_BAUDRATE 9600
  47 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  48 +
  49 +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  50 +
  51 +#define CONFIG_BOOTCOMMAND "printenv"
  52 +
  53 +/* Configuration for environment
  54 + * Environment is embedded in u-boot in the second sector of the flash
  55 + */
  56 +#ifndef CONFIG_MONITOR_IS_IN_RAM
  57 +#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
  58 +#define CFG_ENV_SECT_SIZE 0x4000
  59 +#define CFG_ENV_IS_IN_FLASH 1
  60 +/*
  61 +#define CFG_ENV_IS_EMBEDDED 1
  62 +#define CFG_ENV_ADDR_REDUND 0xF0018000
  63 +#define CFG_ENV_SECT_SIZE_REDUND 0x4000
  64 +*/
  65 +#else
  66 +#define CFG_ENV_ADDR 0xFFE04000
  67 +#define CFG_ENV_SECT_SIZE 0x2000
  68 +#define CFG_ENV_IS_IN_FLASH 1
  69 +#endif
  70 +
  71 +//#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
  72 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
  73 +
  74 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  75 +#include <cmd_confdefs.h>
  76 +
  77 +#define CONFIG_BOOTDELAY 5
  78 +#define CFG_PROMPT "\nEV123 U-Boot> "
  79 +#define CFG_LONGHELP /* undef to save memory */
  80 +
  81 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  82 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  83 +#else
  84 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  85 +#endif
  86 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  87 +#define CFG_MAXARGS 16 /* max number of command args */
  88 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  89 +
  90 +#define CFG_LOAD_ADDR 0x20000
  91 +
  92 +#define CFG_MEMTEST_START 0x100000
  93 +#define CFG_MEMTEST_END 0x400000
  94 +/*#define CFG_DRAM_TEST 1 */
  95 +#undef CFG_DRAM_TEST
  96 +
  97 +/* Clock and PLL Configuration */
  98 +#define CFG_HZ 10000000
  99 +#define CFG_CLK 58982400 /* 9,8304MHz * 6 */
  100 +
  101 +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
  102 +
  103 +#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
  104 +#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
  105 +
  106 +/*
  107 + * Low Level Configuration Settings
  108 + * (address mappings, register initial values, etc.)
  109 + * You should know what you are doing if you make changes here.
  110 + */
  111 +#define CFG_MBAR 0x40000000
  112 +
  113 +#define CFG_DISCOVER_PHY
  114 +/* #define CFG_ENET_BD_BASE 0x380000 */
  115 +
  116 +/*-----------------------------------------------------------------------
  117 + * Definitions for initial stack pointer and data area (in DPRAM)
  118 + */
  119 +#define CFG_INIT_RAM_ADDR 0x20000000
  120 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
  121 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  122 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  123 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  124 +
  125 +/*-----------------------------------------------------------------------
  126 + * Start addresses for the final memory configuration
  127 + * (Set up by the startup code)
  128 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  129 + */
  130 +#define CFG_SDRAM_BASE1 0x00000000
  131 +#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
  132 +
  133 +/*
  134 +#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
  135 +#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
  136 +
  137 +#define CFG_SDRAM_BASE CFG_SDRAM_BASE1
  138 +#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
  139 +
  140 +#define CFG_FLASH_BASE 0xFFE00000
  141 +#define CFG_INT_FLASH_BASE 0xF0000000
  142 +
  143 +/* If M5282 port is fully implemented the monitor base will be behind
  144 + * the vector table. */
  145 +#if (TEXT_BASE != CFG_INT_FLASH_BASE)
  146 +#define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
  147 +#else
  148 +#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
  149 +#endif
  150 +
  151 +#define CFG_MONITOR_LEN 0x20000
  152 +#define CFG_MALLOC_LEN (256 << 10)
  153 +#define CFG_BOOTPARAMS_LEN 64*1024
  154 +
  155 +/*
  156 + * For booting Linux, the board info and command line data
  157 + * have to be in the first 8 MB of memory, since this is
  158 + * the maximum mapped by the Linux kernel during initialization ??
  159 + */
  160 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  161 +
  162 +/*-----------------------------------------------------------------------
  163 + * FLASH organization
  164 + */
  165 +#define CFG_MAX_FLASH_SECT 35
  166 +#define CFG_MAX_FLASH_BANKS 2
  167 +#define CFG_FLASH_ERASE_TOUT 10000000
  168 +#define CFG_FLASH_PROTECTION
  169 +
  170 +/*-----------------------------------------------------------------------
  171 + * Cache Configuration
  172 + */
  173 +#define CFG_CACHELINE_SIZE 16
  174 +
  175 +/*-----------------------------------------------------------------------
  176 + * Memory bank definitions
  177 + */
  178 +
  179 +#define CFG_CS0_BASE CFG_FLASH_BASE
  180 +#define CFG_CS0_SIZE 2*1024*1024
  181 +#define CFG_CS0_WIDTH 16
  182 +#define CFG_CS0_RO 0
  183 +#define CFG_CS0_WS 6
  184 +
  185 +#define CFG_CS3_BASE 0xE0000000
  186 +#define CFG_CS3_SIZE 1*1024*1024
  187 +#define CFG_CS3_WIDTH 16
  188 +#define CFG_CS3_RO 0
  189 +#define CFG_CS3_WS 6
  190 +
  191 +/*-----------------------------------------------------------------------
  192 + * Port configuration
  193 + */
  194 +#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
  195 +#define CFG_PADDR 0x0000000
  196 +#define CFG_PADAT 0x0000000
  197 +
  198 +#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
  199 +#define CFG_PBDDR 0x0000000
  200 +#define CFG_PBDAT 0x0000000
  201 +
  202 +#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
  203 +#define CFG_PCDDR 0x0000000
  204 +#define CFG_PCDAT 0x0000000
  205 +
  206 +#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
  207 +#define CFG_PCDDR 0x0000000
  208 +#define CFG_PCDAT 0x0000000
  209 +
  210 +#define CFG_PEHLPAR 0xC0
  211 +#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
  212 +#define CFG_DDRUA 0x05
  213 +#define CFG_PJPAR 0xFF;
  214 +
  215 +/*-----------------------------------------------------------------------
  216 + * CCM configuration
  217 + */
  218 +
  219 +#define CFG_CCM_SIZ 0
  220 +
  221 +/*---------------------------------------------------------------------*/
  222 +#endif /* _CONFIG_M5282EVB_H */
  223 +/*---------------------------------------------------------------------*/