Add support for Congatec Conga-QEVAl board

Add minimal support (only boot from mmc device) for the Congatec Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad processor) module. Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>

Add support for Congatec Conga-QEVAl board
Add minimal support (only boot from mmc device) for the Congatec Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad processor) module. Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
SARTRE Leo · Stefano Babic
1 parent a7efb02636
Showing 6 changed files with 437 additions and 0 deletions Side-by-side Diff
MAINTAINERS
board/congatec/cgtqmx6eval/Makefile
board/congatec/cgtqmx6eval/README
board/congatec/cgtqmx6eval/cgtqmx6eval.c
boards.cfg
include/configs/cgtqmx6eval.h
@@ -893,6 +893,10 @@
  
 	omap3_overo	ARM ARMV7 (OMAP3xx SoC)
  
+Leo Sartre <lsartre@adeneo-embedded.com>
+
+	cgtqmx6qeval		i.MX6Q
+
 Jens Scharsig <esw@bus-elektronik.de>
  
 	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := cgtqmx6eval.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
+qmx6 quad module.
+
+This file contains information for the port of U-Boot to the Congatec
+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+This version of u-boot works only on the SD card. By default, the
+Congatec board can boot only from the SPI-NOR.
+But, with the u-boot version provided with the board you can write boot
+registers to force the board to reboot and boot from the SD slot. If
+"bmode" command is not available from your pre-installed u-boot, these
+instruction will produce the same effect:
+
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
+conga-QMX6 U-Boot > reset
+resetting ...
+
+The the board will reboot and, if you have written your SD correctly
+the board will use u-boot that live into the SD
+
+To copy the resulting u-boot.imx to the SD card:
+
+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
+
+Note: Replace xxx with the device representing the SD card in your system.
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on mx6qsabrelite.c file
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(1, 4));
+		ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+		break;
+	case USDHC4_BASE_ADDR:
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+		break;
+	default:
+		printf("Bad USDHC interface\n");
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+	status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+		     fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Conga-QEVAL QMX6 Quad\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
@@ -256,6 +256,7 @@
 mx53smd                      arm         armv7       mx53smd             freescale      mx5		mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
 ima3-mx53                    arm         armv7       ima3-mx53           esg            mx5		ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+cgtqmx6qeval				 arm		 armv7		 cgtqmx6eval		 congatec		mx6		cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+/*
+ *
+ * Congatec Conga-QEVAl board configuration file.
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on Freescale i.MX6Q Sabre Lite board configuration file.
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_CGTQMX6EVAL_H
+#define __CONFIG_CGTQMX6EVAL_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	4122
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	       1
+#define CONFIG_BAUDRATE			       115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	       3
+
+#define CONFIG_LOADADDR			       0x12000000
+#define CONFIG_SYS_TEXT_BASE	       0x17800000
+
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"boot_dir=/boot\0" \
+	"console=ttymxc1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr=0x11000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${boot_dir}/${uimage}\0" \
+	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+		"${boot_dir}/${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else "\
+				   "echo ERR: Fail to boot from mmc; " \
+			   "fi; " \
+		   "fi; " \
+	   "else echo ERR: Fail to boot from mmc; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "CGT-QMX6-Quad U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	       256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
+#define CONFIG_SYS_HZ		       1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	       1
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_CGTQMX6EVAL_H */
...	...	@@ -893,6 +893,10 @@
893	893
894	894	omap3_overo ARM ARMV7 (OMAP3xx SoC)
895	895
	896	+Leo Sartre <lsartre@adeneo-embedded.com>
	897	+
	898	+ cgtqmx6qeval i.MX6Q
	899	+
896	900	Jens Scharsig <esw@bus-elektronik.de>
897	901
898	902	eb_cpux9k2 ARM920T (AT91RM9200 SoC)
	1	+#
	2	+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	+#
	4	+# (C) Copyright 2011 Freescale Semiconductor, Inc.
	5	+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
	6	+#
	7	+# This program is free software; you can redistribute it and/or
	8	+# modify it under the terms of the GNU General Public License as
	9	+# published by the Free Software Foundation; either version 2 of
	10	+# the License, or (at your option) any later version.
	11	+#
	12	+# This program is distributed in the hope that it will be useful,
	13	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+# GNU General Public License for more details.
	16	+#
	17	+# You should have received a copy of the GNU General Public License
	18	+# along with this program; if not, write to the Free Software
	19	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+# MA 02111-1307 USA
	21	+#
	22	+
	23	+include $(TOPDIR)/config.mk
	24	+
	25	+LIB = $(obj)lib$(BOARD).o
	26	+
	27	+COBJS := cgtqmx6eval.o
	28	+
	29	+SRCS := $(COBJS:.o=.c)
	30	+OBJS := $(addprefix $(obj),$(COBJS))
	31	+
	32	+$(LIB): $(obj).depend $(OBJS)
	33	+ $(call cmd_link_o_target, $(OBJS))
	34	+
	35	+#########################################################################
	36	+
	37	+# defines $(obj).depend target
	38	+include $(SRCTREE)/rules.mk
	39	+
	40	+sinclude $(obj).depend
	41	+
	42	+#########################################################################
	1	+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
	2	+qmx6 quad module.
	3	+
	4	+This file contains information for the port of U-Boot to the Congatec
	5	+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
	6	+
	7	+1. Boot source, boot from SD card
	8	+---------------------------------
	9	+
	10	+This version of u-boot works only on the SD card. By default, the
	11	+Congatec board can boot only from the SPI-NOR.
	12	+But, with the u-boot version provided with the board you can write boot
	13	+registers to force the board to reboot and boot from the SD slot. If
	14	+"bmode" command is not available from your pre-installed u-boot, these
	15	+instruction will produce the same effect:
	16	+
	17	+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
	18	+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
	19	+conga-QMX6 U-Boot > reset
	20	+resetting ...
	21	+
	22	+The the board will reboot and, if you have written your SD correctly
	23	+the board will use u-boot that live into the SD
	24	+
	25	+To copy the resulting u-boot.imx to the SD card:
	26	+
	27	+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
	28	+
	29	+Note: Replace xxx with the device representing the SD card in your system.
	1	+/*
	2	+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	3	+ * Based on mx6qsabrelite.c file
	4	+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
	5	+ * Leo Sartre, <lsartre@adeneo-embedded.com>
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ */
	22	+
	23	+#include <common.h>
	24	+#include <asm/io.h>
	25	+#include <asm/arch/clock.h>
	26	+#include <asm/arch/imx-regs.h>
	27	+#include <asm/arch/iomux.h>
	28	+#include <asm/arch/mx6-pins.h>
	29	+#include <asm/gpio.h>
	30	+#include <asm/imx-common/iomux-v3.h>
	31	+#include <asm/imx-common/boot_mode.h>
	32	+#include <mmc.h>
	33	+#include <fsl_esdhc.h>
	34	+
	35	+DECLARE_GLOBAL_DATA_PTR;
	36	+
	37	+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \|\
	38	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	39	+
	40	+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \|\
	41	+ PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	42	+
	43	+int dram_init(void)
	44	+{
	45	+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	46	+
	47	+ return 0;
	48	+}
	49	+
	50	+iomux_v3_cfg_t const uart2_pads[] = {
	51	+ MX6_PAD_EIM_D26__UART2_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	52	+ MX6_PAD_EIM_D27__UART2_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	53	+};
	54	+
	55	+iomux_v3_cfg_t const usdhc2_pads[] = {
	56	+ MX6_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	57	+ MX6_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	58	+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	59	+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	60	+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	61	+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	62	+ MX6_PAD_GPIO_4__GPIO_1_4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	63	+};
	64	+
	65	+iomux_v3_cfg_t const usdhc4_pads[] = {
	66	+ MX6_PAD_SD4_CLK__USDHC4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	67	+ MX6_PAD_SD4_CMD__USDHC4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	68	+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	69	+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	70	+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	71	+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	72	+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	73	+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	74	+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	75	+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	76	+ MX6_PAD_NANDF_D6__GPIO_2_6 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
	77	+};
	78	+
	79	+static void setup_iomux_uart(void)
	80	+{
	81	+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
	82	+}
	83	+
	84	+#ifdef CONFIG_FSL_ESDHC
	85	+struct fsl_esdhc_cfg usdhc_cfg[] = {
	86	+ {USDHC2_BASE_ADDR},
	87	+ {USDHC4_BASE_ADDR},
	88	+};
	89	+
	90	+int board_mmc_getcd(struct mmc *mmc)
	91	+{
	92	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	93	+ int ret = 0;
	94	+
	95	+ switch (cfg->esdhc_base) {
	96	+ case USDHC2_BASE_ADDR:
	97	+ gpio_direction_input(IMX_GPIO_NR(1, 4));
	98	+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
	99	+ break;
	100	+ case USDHC4_BASE_ADDR:
	101	+ gpio_direction_input(IMX_GPIO_NR(2, 6));
	102	+ ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
	103	+ break;
	104	+ default:
	105	+ printf("Bad USDHC interface\n");
	106	+ }
	107	+
	108	+ return ret;
	109	+}
	110	+
	111	+int board_mmc_init(bd_t *bis)
	112	+{
	113	+ s32 status = 0;
	114	+
	115	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	116	+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	117	+
	118	+ imx_iomux_v3_setup_multiple_pads(
	119	+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
	120	+ imx_iomux_v3_setup_multiple_pads(
	121	+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
	122	+
	123	+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) \|
	124	+ fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
	125	+
	126	+ return status;
	127	+}
	128	+#endif
	129	+
	130	+int board_early_init_f(void)
	131	+{
	132	+ setup_iomux_uart();
	133	+
	134	+ return 0;
	135	+}
	136	+
	137	+int board_init(void)
	138	+{
	139	+ /* address of boot parameters */
	140	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	141	+
	142	+ return 0;
	143	+}
	144	+
	145	+int checkboard(void)
	146	+{
	147	+ puts("Board: Conga-QEVAL QMX6 Quad\n");
	148	+
	149	+ return 0;
	150	+}
	151	+
	152	+#ifdef CONFIG_CMD_BMODE
	153	+static const struct boot_mode board_boot_modes[] = {
	154	+ /* 4 bit bus width */
	155	+ {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
	156	+ {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
	157	+ {NULL, 0},
	158	+};
	159	+#endif
	160	+
	161	+int misc_init_r(void)
	162	+{
	163	+#ifdef CONFIG_CMD_BMODE
	164	+ add_board_boot_modes(board_boot_modes);
	165	+#endif
	166	+ return 0;
	167	+}
...	...	@@ -256,6 +256,7 @@
256	256	mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
257	257	ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
258	258	vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
	259	+cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
259	260	mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
260	261	mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
261	262	mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
	1	+/*
	2	+ *
	3	+ * Congatec Conga-QEVAl board configuration file.
	4	+ *
	5	+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	6	+ * Based on Freescale i.MX6Q Sabre Lite board configuration file.
	7	+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
	8	+ * Leo Sartre, <lsartre@adeneo-embedded.com>
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#ifndef __CONFIG_CGTQMX6EVAL_H
	27	+#define __CONFIG_CGTQMX6EVAL_H
	28	+
	29	+#define CONFIG_MX6
	30	+
	31	+#include "mx6_common.h"
	32	+
	33	+#define CONFIG_DISPLAY_CPUINFO
	34	+#define CONFIG_DISPLAY_BOARDINFO
	35	+
	36	+#define CONFIG_MACH_TYPE 4122
	37	+
	38	+#include <asm/arch/imx-regs.h>
	39	+#include <asm/imx-common/gpio.h>
	40	+
	41	+#define CONFIG_CMDLINE_TAG
	42	+#define CONFIG_SETUP_MEMORY_TAGS
	43	+#define CONFIG_INITRD_TAG
	44	+#define CONFIG_REVISION_TAG
	45	+
	46	+/* Size of malloc() pool */
	47	+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	48	+
	49	+#define CONFIG_BOARD_EARLY_INIT_F
	50	+#define CONFIG_MISC_INIT_R
	51	+#define CONFIG_MXC_GPIO
	52	+
	53	+#define CONFIG_MXC_UART
	54	+#define CONFIG_MXC_UART_BASE UART2_BASE
	55	+
	56	+/* MMC Configs */
	57	+#define CONFIG_FSL_ESDHC
	58	+#define CONFIG_FSL_USDHC
	59	+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	60	+
	61	+#define CONFIG_MMC
	62	+#define CONFIG_CMD_MMC
	63	+#define CONFIG_GENERIC_MMC
	64	+#define CONFIG_BOUNCE_BUFFER
	65	+#define CONFIG_CMD_EXT2
	66	+#define CONFIG_CMD_FAT
	67	+#define CONFIG_DOS_PARTITION
	68	+
	69	+/* Miscellaneous commands */
	70	+#define CONFIG_CMD_BMODE
	71	+
	72	+/* allow to overwrite serial and ethaddr */
	73	+#define CONFIG_ENV_OVERWRITE
	74	+#define CONFIG_CONS_INDEX 1
	75	+#define CONFIG_BAUDRATE 115200
	76	+
	77	+/* Command definition */
	78	+#include <config_cmd_default.h>
	79	+
	80	+#undef CONFIG_CMD_IMLS
	81	+
	82	+#define CONFIG_BOOTDELAY 3
	83	+
	84	+#define CONFIG_LOADADDR 0x12000000
	85	+#define CONFIG_SYS_TEXT_BASE 0x17800000
	86	+
	87	+#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
	88	+
	89	+#define CONFIG_EXTRA_ENV_SETTINGS \
	90	+ "script=boot.scr\0" \
	91	+ "uimage=uImage\0" \
	92	+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
	93	+ "boot_dir=/boot\0" \
	94	+ "console=ttymxc1\0" \
	95	+ "fdt_high=0xffffffff\0" \
	96	+ "initrd_high=0xffffffff\0" \
	97	+ "fdt_addr=0x11000000\0" \
	98	+ "boot_fdt=try\0" \
	99	+ "mmcdev=1\0" \
	100	+ "mmcpart=1\0" \
	101	+ "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
	102	+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
	103	+ "root=${mmcroot}\0" \
	104	+ "loadbootscript=" \
	105	+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	106	+ "bootscript=echo Running bootscript from mmc ...; " \
	107	+ "source\0" \
	108	+ "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
	109	+ "${boot_dir}/${uimage}\0" \
	110	+ "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
	111	+ "${boot_dir}/${fdt_file}\0" \
	112	+ "mmcboot=echo Booting from mmc ...; " \
	113	+ "run mmcargs; " \
	114	+ "if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	115	+ "if run loadfdt; then " \
	116	+ "bootm ${loadaddr} - ${fdt_addr}; " \
	117	+ "else " \
	118	+ "if test ${boot_fdt} = try; then " \
	119	+ "bootm; " \
	120	+ "else " \
	121	+ "echo WARN: Cannot load the DT; " \
	122	+ "fi; " \
	123	+ "fi; " \
	124	+ "else " \
	125	+ "bootm; " \
	126	+ "fi;\0"
	127	+
	128	+#define CONFIG_BOOTCOMMAND \
	129	+ "mmc dev ${mmcdev};" \
	130	+ "mmc dev ${mmcdev}; if mmc rescan; then " \
	131	+ "if run loadbootscript; then " \
	132	+ "run bootscript; " \
	133	+ "else " \
	134	+ "if run loaduimage; then " \
	135	+ "run mmcboot; " \
	136	+ "else "\
	137	+ "echo ERR: Fail to boot from mmc; " \
	138	+ "fi; " \
	139	+ "fi; " \
	140	+ "else echo ERR: Fail to boot from mmc; fi"
	141	+
	142	+/* Miscellaneous configurable options */
	143	+#define CONFIG_SYS_LONGHELP
	144	+#define CONFIG_SYS_HUSH_PARSER
	145	+#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > "
	146	+#define CONFIG_AUTO_COMPLETE
	147	+#define CONFIG_SYS_CBSIZE 256
	148	+
	149	+/* Print Buffer Size */
	150	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	151	+#define CONFIG_SYS_MAXARGS 16
	152	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	153	+
	154	+#define CONFIG_SYS_MEMTEST_START 0x10000000
	155	+#define CONFIG_SYS_MEMTEST_END 0x10010000
	156	+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
	157	+
	158	+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	159	+#define CONFIG_SYS_HZ 1000
	160	+
	161	+#define CONFIG_CMDLINE_EDITING
	162	+
	163	+/* Physical Memory Map */
	164	+#define CONFIG_NR_DRAM_BANKS 1
	165	+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	166	+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	167	+
	168	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	169	+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	170	+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	171	+
	172	+#define CONFIG_SYS_INIT_SP_OFFSET \
	173	+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	174	+#define CONFIG_SYS_INIT_SP_ADDR \
	175	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	176	+
	177	+/* FLASH and environment organization */
	178	+#define CONFIG_SYS_NO_FLASH
	179	+
	180	+#define CONFIG_ENV_SIZE (8 * 1024)
	181	+
	182	+#define CONFIG_ENV_IS_IN_MMC
	183	+
	184	+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
	185	+#define CONFIG_SYS_MMC_ENV_DEV 0
	186	+
	187	+#define CONFIG_OF_LIBFDT
	188	+#define CONFIG_CMD_BOOTZ
	189	+
	190	+#ifndef CONFIG_SYS_DCACHE_OFF
	191	+#define CONFIG_CMD_CACHE
	192	+#endif
	193	+
	194	+#endif /* __CONFIG_CGTQMX6EVAL_H */