Eric Lee / smarc-uboot

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Commit 9b880bd4d86dc568221107516e6d4728c5f93a4e

Authored by Wolfgang Denk
1 parent 1820d4c73b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Update ARM Integrator boards: 

Correct addessing errors in platform files.
Split off common core module data from Integrator header files to
include/armcoremodule.h.
Patch by Peter Pearse, 04 Oct 2005

Showing 9 changed files with 224 additions and 135 deletions Side-by-side Diff

... ... @@ -2,16 +2,24 @@
2 2 Changes for U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Cleanup
  6 +
  7 +* Update ARM Integrator boards:
  8 + Correct addessing errors in platform files.
  9 + Split off common core module data from Integrator header files to
  10 + include/armcoremodule.h.
  11 + Patch by Peter Pearse, 04 Oct 2005
  12 +
5 13 * Make sure only supported compiler options are used
6 14 Import "cc-option" shell function from kernel and
7 15 use it to get the correct ARM GCC options for individual CPUs
8 16 Patch by Peter Pearse, 30 Jun 2005
9 17  
10 18 * Fix 440GR to print correct cpu revision
11   - Patch by Stefan Roese, 4 Oct 2005
  19 + Patch by Stefan Roese, 04 Oct 2005
12 20  
13 21 * Change board message on AMCC Yosemite & Yellowstone to common style
14   - Patch by Stefan Roese, 3 Oct 2005
  22 + Patch by Stefan Roese, 03 Oct 2005
15 23  
16 24 * Fix compiler warning
17 25  
board/integratorap/integratorap.c
Diff comments   View file @ 9b880bd
... ... @@ -649,4 +649,9 @@
649 649 {
650 650 return CFG_HZ_CLOCK/div_clock;
651 651 }
  652 +
  653 +/* The Integrator/AP timer1 is clocked at 24MHz
  654 + * can be divided by 16 or 256
  655 + * and is a 16-bit counter
  656 + */
board/integratorap/platform.S
Diff comments   View file @ 9b880bd
... ... @@ -32,7 +32,7 @@
32 32 mov r0, #CM_BASE
33 33 ldr r1,[r0,#OS_CTRL]
34 34 orr r1,r1,#CMMASK_RESET
35   - str r1,[r0]
  35 + str r1,[r0,#OS_CTRL]
36 36  
37 37 reset_failed:
38 38 b reset_failed
... ... @@ -98,8 +98,8 @@
98 98 beq init_reg_OK
99 99  
100 100 /* lock for change */
101   - mov r3, #CMVAL_LOCK
102   - and r3,r3,#CMMASK_LOCK
  101 + mov r3, #CMVAL_LOCK1
  102 + add r3,r3,#CMVAL_LOCK2
103 103 str r3, [r0, #OS_LOCK]
104 104 /* set desired value */
105 105 orr r1,r1,r2
board/integratorcp/platform.S
Diff comments   View file @ 9b880bd
... ... @@ -32,7 +32,7 @@
32 32 mov r0, #CM_BASE
33 33 ldr r1,[r0,#OS_CTRL]
34 34 orr r1,r1,#CMMASK_RESET
35   - str r1,[r0]
  35 + str r1,[r0,#OS_CTRL]
36 36  
37 37 reset_failed:
38 38 b reset_failed
... ... @@ -65,6 +65,7 @@
65 65  
66 66 #if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
67 67 !defined (CONFIG_CM940T)
  68 + /* CMxx6 code */
68 69  
69 70 #ifdef CONFIG_CM_MULTIPLE_SSRAM
70 71 /* set simple mapping */
... ... @@ -98,8 +99,8 @@
98 99 beq init_reg_OK
99 100  
100 101 /* lock for change */
101   - mov r3, #CMVAL_LOCK
102   - and r3,r3,#CMMASK_LOCK
  102 + mov r3, #CMVAL_LOCK1
  103 + and r3, r3, #CMVAL_LOCK2
103 104 str r3, [r0, #OS_LOCK]
104 105 /* set desired value */
105 106 orr r1,r1,r2
... ... @@ -91,7 +91,7 @@
91 91 # only supported compiler options are used
92 92 #
93 93 cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
94   - > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
  94 + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
95 95  
96 96 #
97 97 # Include the make variables (CC, etc...)
doc/README-integrator
Diff comments   View file @ 9b880bd
... ... @@ -18,6 +18,7 @@
18 18 SDRAM
19 19 RAM controllers
20 20 clock generators etc.
  21 +CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
21 22  
22 23 Boot Methods :
23 24 ------------
include/armcoremodule.h
Diff comments   View file @ 9b880bd
  1 +/*
  2 + * (C) Copyright 2005
  3 + * ARM Ltd.
  4 + * Peter Pearse, <Peter.Pearse@arm.com>
  5 + * Configuration for ARM Core Modules.
  6 + * No standalonw port yet available
  7 + * - this file is included by both integratorap.h & integratorcp.h
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + */
  27 +
  28 +#ifndef __ARMCOREMODULE_H
  29 +#define __ARMCOREMODULE_H
  30 +
  31 +#define CM_BASE 0x10000000
  32 +
  33 +/* CM registers common to all CMs */
  34 +/* Note that observed values after reboot into the ARM Boot Monitor
  35 + have been used as defaults, rather than the POR values */
  36 +#define OS_CTRL 0x0000000C
  37 +#define CMMASK_REMAP 0x00000005 /* set remap & led */
  38 +#define CMMASK_RESET 0x00000008
  39 +#define OS_LOCK 0x00000014
  40 +#define CMVAL_LOCK1 0x0000A000 /* locking value */
  41 +#define CMVAL_LOCK2 0x0000005F /* locking value */
  42 +#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
  43 +#define OS_SDRAM 0x00000020
  44 +#define OS_INIT 0x00000024
  45 +#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
  46 +#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
  47 +#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
  48 +#define CMMASK_LE 0xFFFFFFF7 /* little endian */
  49 +#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
  50 + /* - observed reset value of */
  51 + /* CM926EJ-S */
  52 + /* CM1136-EJ-S */
  53 +
  54 +#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
  55 +#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
  56 + /* - PLL test clock bypassed */
  57 + /* - bus clock ratio 2 */
  58 + /* - little endian */
  59 + /* - vectors at zero */
  60 +#endif /* CM1022xx */
  61 +
  62 +/* Determine CM characteristics */
  63 +
  64 +#undef CONFIG_CM_MULTIPLE_SSRAM
  65 +#undef CONFIG_CM_SPD_DETECT
  66 +#undef CONFIG_CM_REMAP
  67 +#undef CONFIG_CM_INIT
  68 +#undef CONFIG_CM_TCRAM
  69 +
  70 +#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
  71 +#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
  72 +#endif
  73 +
  74 +/* Excalibur core module has reduced functionality */
  75 +#ifndef CONFIG_CM922T_XA10
  76 +#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
  77 +#define OS_SPD 0x00000100 /* Address of SPD data */
  78 +#define CONFIG_CM_REMAP /* CM supports remapping */
  79 +#define CONFIG_CM_INIT /* CM has initialization reg */
  80 +#endif /* NOT EXCALIBUR */
  81 +
  82 +#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
  83 + defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
  84 + defined(CONFIG_CM1136JF_S)
  85 +#define CONFIG_CM_TCRAM /* CM has TCRAM */
  86 +#endif
  87 +
  88 +#ifdef CONFIG_CM_SPD_DETECT
  89 +#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
  90 +#endif
  91 +
  92 +#endif /* __ARMCOREMODULE_H */
include/configs/integratorap.h
Diff comments   View file @ 9b880bd
... ... @@ -275,43 +275,7 @@
275 275 * to define the necessary CONFIG_ s for the CM involved
276 276 * see e.g. integratorcp_CM926EJ-S_config
277 277 */
  278 +#include "armcoremodule.h"
278 279  
279   -#define CM_BASE 0x10000000
280   -
281   -/* CM registers common to all integrator/CP CMs */
282   -#define OS_CTRL 0x0000000C
283   -#define CMMASK_REMAP 0x00000005 /* Set remap & led */
284   -#define CMMASK_RESET 0x00000008
285   -#define OS_LOCK 0x00000014
286   -#define CMVAL_LOCK 0x0000A000 /* Locking value */
287   -#define CMMASK_LOCK 0x0000005F /* Locking value */
288   -#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
289   -#define OS_SDRAM 0x00000020
290   -#define OS_INIT 0x00000024
291   -#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
292   -#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
293   -#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
294   -
295   -#ifdef CONFIG_CM_SPD_DETECT
296   -#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
297   -#endif
298   -
299   -#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
300   -#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
301   - * - PLL test clock bypassed
302   - * - bus clock ratio 2
303   - * - little endian
304   - * - vectors at zero
305   - */
306   -#endif /* CM1022xx */
307   -
308   -#define CMMASK_LE 0x00000008 /* little endian */
309   -#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
310   - * - divisor/ratio b00000001
311   - * bx
312   - * - HCLKDIV b000
313   - * bxx
314   - * - PLL BYPASS b00
315   - */
316 280 #endif /* __CONFIG_H */
include/configs/integratorcp.h
Diff comments   View file @ 9b880bd
... ... @@ -66,7 +66,7 @@
66 66 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
67 67 #define CONFIG_CONS_INDEX 0
68 68 #define CONFIG_BAUDRATE 38400
69   -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  69 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
70 70 #define CFG_SERIAL0 0x16000000
71 71 #define CFG_SERIAL1 0x17000000
72 72  
73 73  
74 74  
75 75  
76 76  
77 77  
... ... @@ -84,30 +84,31 @@
84 84  
85 85 #if 0
86 86 #define CONFIG_BOOTDELAY 2
87   -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
  87 +#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
88 88 #define CONFIG_BOOTCOMMAND "bootp ; bootm"
89 89 #endif
  90 +/* The kernel command line & boot command below are for a platform flashed with afu.axf
90 91  
91   -/* Flash loaded
92   - - U-Boot
93   - - u-linux
94   - - system.cramfs
  92 +Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot
  93 +Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
  94 +Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
  95 +SIB at Block62 End Block62 address 0x24f80000
  96 +
95 97 */
96 98 #define CONFIG_BOOTDELAY 2
97   -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0, \
98   -0xfc800000,0xfc800010,eth0 video=clcdfb:0"
99   -#define CONFIG_BOOTCOMMAND "cp 0x24040000 0x7fc0 0x80000; bootm"
  99 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
  100 +#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
100 101  
101 102 /*
102 103 * Miscellaneous configurable options
103 104 */
104   -#define CFG_LONGHELP /* undef to save memory */
105   -#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
106   -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  105 +#define CFG_LONGHELP /* undef to save memory */
  106 +#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
  107 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/
107 108 /* Print Buffer Size */
108 109 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
109   -#define CFG_MAXARGS 16 /* max number of command args */
110   -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  110 +#define CFG_MAXARGS 16 /* max number of command args */
  111 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/
111 112  
112 113 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
113 114 #define CFG_LOAD_ADDR 0x7fc0 /* default load address */
114 115  
115 116  
116 117  
117 118  
118 119  
119 120  
120 121  
121 122  
122 123  
123 124  
124 125  
125 126  
126 127  
127 128  
128 129  
129 130  
... ... @@ -126,91 +127,118 @@
126 127 /*-----------------------------------------------------------------------
127 128 * Physical Memory Map
128 129 */
129   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
130   -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
131   -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  130 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  131 +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
  132 +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
132 133  
133 134 /*-----------------------------------------------------------------------
134 135 * FLASH and environment organization
  136 +
  137 + * Top varies according to amount fitted
  138 + * Reserve top 4 blocks of flash
  139 + * - ARM Boot Monitor
  140 + * - Unused
  141 + * - SIB block
  142 + * - U-Boot environment
  143 + *
  144 + * Base is always 0x24000000
  145 +
135 146 */
136   -#define CFG_FLASH_BASE 0x24000000
  147 +#define CFG_FLASH_BASE 0x24000000
137 148 #define CFG_MAX_FLASH_SECT 64
138 149 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
139   -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
  150 +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
140 151 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
141 152 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
142 153  
143   -#define CFG_MONITOR_BASE 0x24F40000
144   -#define CFG_ENV_IS_IN_FLASH
  154 +#define CFG_MONITOR_LEN 0x00100000
  155 +#define CFG_ENV_IS_IN_FLASH (1)
  156 +
  157 +/*
  158 + * Move up the U-Boot & monitor area if more flash is fitted.
  159 + * If this U-Boot is to be run on Integrators with varying flash sizes,
  160 + * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
  161 + * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
  162 + * - CFG_MONITOR_BASE is set to indicate that the environment is not
  163 + * embedded in the boot monitor(s) area
  164 + */
  165 +#if ( PHYS_FLASH_SIZE == 0x04000000 )
  166 +
  167 +#define CFG_ENV_ADDR 0x27F00000
  168 +#define CFG_MONITOR_BASE 0x27F40000
  169 +
  170 +#elif (PHYS_FLASH_SIZE == 0x02000000 )
  171 +
  172 +#define CFG_ENV_ADDR 0x25F00000
  173 +#define CFG_MONITOR_BASE 0x25F40000
  174 +
  175 +#else
  176 +
145 177 #define CFG_ENV_ADDR 0x24F00000
  178 +#define CFG_MONITOR_BASE 0x27F40000
  179 +
  180 +#endif
  181 +
146 182 #define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
147 183 #define CFG_ENV_SIZE 8192 /* 8KB */
148   -
149 184 /*-----------------------------------------------------------------------
150   - * There are various dependencies on the core module (CM) fitted
151   - * Users should refer to their CM user guide
152   - * - when porting adjust u-boot/Makefile accordingly
153   - * to define the necessary CONFIG_ s for the CM involved
154   - * see e.g. integratorcp_CM926EJ-S_config
  185 + * CP control registers
155 186 */
  187 +#define CPCR_BASE 0xCB000000 /* CP Registers*/
  188 +#define OS_FLASHPROG 0x00000004 /* Flash register*/
  189 +#define CPMASK_EXTRABANK 0x8
  190 +#define CPMASK_FLASHSIZE 0x4
  191 +#define CPMASK_FLWREN 0x2
  192 +#define CPMASK_FLVPPEN 0x1
156 193  
157   -#define CM_BASE 0x10000000
  194 +/*
  195 + * The ARM boot monitor initializes the board.
  196 + * However, the default U-Boot code also performs the initialization.
  197 + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
  198 + * - see documentation supplied with board for details of how to choose the
  199 + * image to run at reset/power up
  200 + * e.g. whether the ARM Boot Monitor runs before U-Boot
158 201  
159   -/* CM registers common to all integrator/CP CMs */
160   -#define OS_CTRL 0x0000000C
161   -#define CMMASK_REMAP 0x00000005 /* set remap & led */
162   -#define CMMASK_RESET 0x00000008
163   -#define OS_LOCK 0x00000014
164   -#define CMVAL_LOCK 0x0000A000 /* locking value */
165   -#define CMMASK_LOCK 0x0000005F /* locking value */
166   -#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
167   -#define OS_SDRAM 0x00000020
168   -#define OS_INIT 0x00000024
169   -#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
170   -#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
171   -#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
172   -#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
173   -#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
174   - * - PLL test clock bypassed
175   - * - bus clock ratio 2
176   - * - little endian
177   - * - vectors at zero
178   - */
179   -#endif /* CM1022xx */
  202 +#define CONFIG_SKIP_LOWLEVEL_INIT
180 203  
181   -#define CMMASK_LE 0x00000008 /* little endian */
182   -#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
183   - * - divisor/ratio b00000001
184   - * bx
185   - * - HCLKDIV b000
186   - * bxx
187   - * - PLL BYPASS b00
188   - */
  204 + */
189 205  
190   -/* Determine CM characteristics */
  206 +/*
  207 + * The ARM boot monitor does not relocate U-Boot.
  208 + * However, the default U-Boot code performs the relocation check,
  209 + * and may relocate the code if the memory map is changed.
  210 + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
191 211  
192   -#undef CONFIG_CM_MULTIPLE_SSRAM
193   -#undef CONFIG_CM_SPD_DETECT
194   -#undef CONFIG_CM_REMAP
195   -#undef CONFIG_CM_INIT
196   -#undef CONFIG_CM_TCRAM
  212 +#define SKIP_CONFIG_RELOCATE_UBOOT
197 213  
198   -#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
199   -#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
200   -#endif
  214 + */
  215 +/*-----------------------------------------------------------------------
  216 + * There are various dependencies on the core module (CM) fitted
  217 + * Users should refer to their CM user guide
  218 + * - when porting adjust u-boot/Makefile accordingly
  219 + * to define the necessary CONFIG_ s for the CM involved
  220 + * see e.g. cp_926ejs_config
  221 + */
201 222  
202   -#ifndef CONFIG_CM922t_XA10
203   -#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
204   -#define OS_SPD 0x00000100 /* Address of SPD data */
205   -#define CONFIG_CM_REMAP /* CM supports remapping */
206   -#define CONFIG_CM_INIT /* CM has initialization reg */
207   -#endif
  223 +#include "armcoremodule.h"
208 224  
209   -#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
210   - defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
211   - defined(CONFIG_CM1136JF_S)
212   -#define CONFIG_CM_TCRAM /* CM has TCRAM */
213   -#endif
  225 +/*
  226 + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
  227 + * the core module has a CM_INIT register
  228 + * then the U-Boot initialisation code will
  229 + * e.g. ARM Boot Monitor or pre-loader is repeated once
  230 + * (to re-initialise any existing CM_INIT settings to safe values).
  231 + *
  232 + * This is usually not the desired behaviour since the platform
  233 + * will either reboot into the ARM monitor (or pre-loader)
  234 + * or continuously cycle thru it without U-Boot running,
  235 + * depending upon the setting of Integrator/CP switch S2-4.
  236 + *
  237 + * However it may be needed if Integrator/CP switch S2-1
  238 + * is set OFF to boot direct into U-Boot.
  239 + * In that case comment out the line below.
  240 +#undef CONFIG_CM_INIT
  241 + */
214 242  
215 243 #endif /* __CONFIG_H */