FSL DDR: Convert SBC8641D to new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

FSL DDR: Convert SBC8641D to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala · Wolfgang Denk
1 parent 39aa1a7348
Showing 4 changed files with 99 additions and 8 deletions Side-by-side Diff
board/sbc8641d/Makefile
board/sbc8641d/ddr.c
board/sbc8641d/sbc8641d.c
include/configs/sbc8641d.h
@@ -25,10 +25,12 @@
  
 LIB	= $(obj)lib$(BOARD).a
  
-COBJS	:= $(BOARD).o law.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
  
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
  
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_bus_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		}
+		if (ctrl_num == 0 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		}
+		if (ctrl_num == 1 && i == 0) {
+			i2c_address = SPD_EEPROM_ADDRESS3;
+		}
+		if (ctrl_num == 1 && i == 1) {
+			i2c_address = SPD_EEPROM_ADDRESS4;
+		}
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
@@ -34,7 +34,7 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd_sdram.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
  
@@ -42,7 +42,6 @@
 extern void ddr_enable_ecc (unsigned int dram_size);
 #endif
  
-void sdram_init (void);
 long int fixed_sdram (void);
  
 int board_early_init_f (void)
@@ -62,7 +61,7 @@
 	long dram_size = 0;
  
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram ();
 #endif
@@ -61,8 +61,6 @@
 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
  
 #undef CONFIG_SPD_EEPROM		/* Do not use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
@@ -113,6 +111,10 @@
 #define CONFIG_VERY_BIG_RAM
  
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  
 #if defined(CONFIG_SPD_EEPROM)
     /*
...	...	@@ -25,10 +25,12 @@
25	25
26	26	LIB = $(obj)lib$(BOARD).a
27	27
28		-COBJS := $(BOARD).o law.o
	28	+COBJS-y += $(BOARD).o
	29	+COBJS-y += law.o
	30	+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
29	31
30		-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
31		-OBJS := $(addprefix $(obj),$(COBJS))
	32	+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
	33	+OBJS := $(addprefix $(obj),$(COBJS-y))
32	34	SOBJS := $(addprefix $(obj),$(SOBJS))
33	35
34	36	$(LIB): $(obj).depend $(OBJS) $(SOBJS)
	1	+/*
	2	+ * Copyright 2008 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * Version 2 as published by the Free Software Foundation.
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <i2c.h>
	11	+
	12	+#include <asm/fsl_ddr_sdram.h>
	13	+
	14	+static void
	15	+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
	16	+{
	17	+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
	18	+}
	19	+
	20	+unsigned int fsl_ddr_get_mem_data_rate(void)
	21	+{
	22	+ return get_bus_freq(0);
	23	+}
	24	+
	25	+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
	26	+ unsigned int ctrl_num)
	27	+{
	28	+ unsigned int i;
	29	+ unsigned int i2c_address = 0;
	30	+
	31	+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
	32	+ if (ctrl_num == 0 && i == 0) {
	33	+ i2c_address = SPD_EEPROM_ADDRESS1;
	34	+ }
	35	+ if (ctrl_num == 0 && i == 1) {
	36	+ i2c_address = SPD_EEPROM_ADDRESS2;
	37	+ }
	38	+ if (ctrl_num == 1 && i == 0) {
	39	+ i2c_address = SPD_EEPROM_ADDRESS3;
	40	+ }
	41	+ if (ctrl_num == 1 && i == 1) {
	42	+ i2c_address = SPD_EEPROM_ADDRESS4;
	43	+ }
	44	+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
	45	+ }
	46	+}
	47	+
	48	+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
	49	+{
	50	+ /*
	51	+ * Factors to consider for clock adjust:
	52	+ * - number of chips on bus
	53	+ * - position of slot
	54	+ * - DDR1 vs. DDR2?
	55	+ * - ???
	56	+ *
	57	+ * This needs to be determined on a board-by-board basis.
	58	+ * 0110 3/4 cycle late
	59	+ * 0111 7/8 cycle late
	60	+ */
	61	+ popts->clk_adjust = 7;
	62	+
	63	+ /*
	64	+ * Factors to consider for CPO:
	65	+ * - frequency
	66	+ * - ddr1 vs. ddr2
	67	+ */
	68	+ popts->cpo_override = 10;
	69	+
	70	+ /*
	71	+ * Factors to consider for write data delay:
	72	+ * - number of DIMMs
	73	+ *
	74	+ * 1 = 1/4 clock delay
	75	+ * 2 = 1/2 clock delay
	76	+ * 3 = 3/4 clock delay
	77	+ * 4 = 1 clock delay
	78	+ * 5 = 5/4 clock delay
	79	+ * 6 = 3/2 clock delay
	80	+ */
	81	+ popts->write_data_delay = 3;
	82	+
	83	+ /*
	84	+ * Factors to consider for half-strength driver enable:
	85	+ * - number of DIMMs installed
	86	+ */
	87	+ popts->half_strength_driver_enable = 0;
	88	+}
...	...	@@ -34,7 +34,7 @@
34	34	#include <asm/processor.h>
35	35	#include <asm/immap_86xx.h>
36	36	#include <asm/immap_fsl_pci.h>
37		-#include <spd_sdram.h>
	37	+#include <asm/fsl_ddr_sdram.h>
38	38	#include <libfdt.h>
39	39	#include <fdt_support.h>
40	40
...	...	@@ -42,7 +42,6 @@
42	42	extern void ddr_enable_ecc (unsigned int dram_size);
43	43	#endif
44	44
45		-void sdram_init (void);
46	45	long int fixed_sdram (void);
47	46
48	47	int board_early_init_f (void)
...	...	@@ -62,7 +61,7 @@
62	61	long dram_size = 0;
63	62
64	63	#if defined(CONFIG_SPD_EEPROM)
65		- dram_size = spd_sdram ();
	64	+ dram_size = fsl_ddr_sdram();
66	65	#else
67	66	dram_size = fixed_sdram ();
68	67	#endif
...	...	@@ -61,8 +61,6 @@
61	61	#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
62	62
63	63	#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
64		-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
65		-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
66	64	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
67	65	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
68	66	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
...	...	@@ -113,6 +111,10 @@
113	111	#define CONFIG_VERY_BIG_RAM
114	112
115	113	#define MPC86xx_DDR_SDRAM_CLK_CNTL
	114	+
	115	+#define CONFIG_NUM_DDR_CONTROLLERS 2
	116	+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	117	+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
116	118
117	119	#if defined(CONFIG_SPD_EEPROM)
118	120	/*