Eric Lee / smarc-uboot

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Commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3

Authored by Wolfgang Denk
Committed by Wolfgang Denk
1 parent de8404441b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Minor code cleanup.

Showing 2 changed files with 322 additions and 328 deletions Inline Diff

board/tqm8272/tqm8272.c
Diff comments   View file @ 9c0f42e
1 /* 1 /*
2 * (C) Copyright 2006 2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #include <common.h> 24 #include <common.h>
25 #include <ioports.h> 25 #include <ioports.h>
26 #include <mpc8260.h> 26 #include <mpc8260.h>
27 27
28 #include <command.h> 28 #include <command.h>
29 #ifdef CONFIG_PCI 29 #ifdef CONFIG_PCI
30 #include <pci.h> 30 #include <pci.h>
31 #include <asm/m8260_pci.h> 31 #include <asm/m8260_pci.h>
32 #endif 32 #endif
33 #if CONFIG_OF_FLAT_TREE 33 #if CONFIG_OF_FLAT_TREE
34 #include <ft_build.h> 34 #include <ft_build.h>
35 #include <image.h> 35 #include <image.h>
36 #endif 36 #endif
37 37
38 #if 0 38 #if 0
39 #define deb_printf(fmt,arg...) \ 39 #define deb_printf(fmt,arg...) \
40 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) 40 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
41 #else 41 #else
42 #define deb_printf(fmt,arg...) \ 42 #define deb_printf(fmt,arg...) \
43 do { } while (0) 43 do { } while (0)
44 #endif 44 #endif
45 45
46 #if defined(CONFIG_BOARD_GET_CPU_CLK_F) 46 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
47 unsigned long board_get_cpu_clk_f (void); 47 unsigned long board_get_cpu_clk_f (void);
48 #endif 48 #endif
49 49
50 /* 50 /*
51 * I/O Port configuration table 51 * I/O Port configuration table
52 * 52 *
53 * if conf is 1, then that port pin will be configured at boot time 53 * if conf is 1, then that port pin will be configured at boot time
54 * according to the five values podr/pdir/ppar/psor/pdat for that entry 54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 */ 55 */
56 56
57 const iop_conf_t iop_conf_tab[4][32] = { 57 const iop_conf_t iop_conf_tab[4][32] = {
58 58
59 /* Port A configuration */ 59 /* Port A configuration */
60 { /* conf ppar psor pdir podr pdat */ 60 { /* conf ppar psor pdir podr pdat */
61 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ 61 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
62 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ 62 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
63 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ 63 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
64 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ 64 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
65 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ 65 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
66 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ 66 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
67 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ 67 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
68 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ 68 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
69 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ 69 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
70 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ 70 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
71 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ 71 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
72 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ 72 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
73 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ 73 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
74 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ 74 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
75 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ 75 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
76 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ 76 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
77 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ 77 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
78 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ 78 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
79 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ 79 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
80 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ 80 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
81 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ 81 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
82 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ 82 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
83 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ 83 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
84 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ 84 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
85 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ 85 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
86 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ 86 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
87 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ 87 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
88 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ 88 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
89 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ 89 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
90 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ 90 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
91 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ 91 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
92 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ 92 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
93 }, 93 },
94 94
95 /* Port B configuration */ 95 /* Port B configuration */
96 { /* conf ppar psor pdir podr pdat */ 96 { /* conf ppar psor pdir podr pdat */
97 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 97 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
98 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 98 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
99 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 99 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
100 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 100 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
101 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 101 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
102 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 102 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
103 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 103 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
104 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 104 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
105 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 105 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
106 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 106 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
107 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 107 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
108 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 108 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
109 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 109 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
110 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 110 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
111 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ 111 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
112 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ 112 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
113 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ 113 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
114 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ 114 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
115 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ 115 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
116 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ 116 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
117 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ 117 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
118 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ 118 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
119 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ 119 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
120 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ 120 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
121 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ 121 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
122 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ 122 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
123 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ 123 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
124 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ 124 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
125 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 125 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 126 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 127 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 128 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
129 }, 129 },
130 130
131 /* Port C */ 131 /* Port C */
132 { /* conf ppar psor pdir podr pdat */ 132 { /* conf ppar psor pdir podr pdat */
133 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ 133 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
134 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ 134 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
135 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 135 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
136 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ 136 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
137 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ 137 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
138 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ 138 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
139 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ 139 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
140 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ 140 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
141 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 141 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
142 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 142 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
143 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 143 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
144 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 144 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
145 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ 145 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
146 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ 146 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
147 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ 147 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
148 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ 148 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
149 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ 149 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
150 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 150 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
151 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ 151 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
152 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ 152 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
153 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ 153 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
154 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ 154 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
155 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ 155 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
156 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ 156 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
157 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ 157 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
158 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ 158 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
159 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ 159 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
160 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ 160 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
161 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ 161 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
162 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ 162 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
163 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 163 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
164 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ 164 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
165 }, 165 },
166 166
167 /* Port D */ 167 /* Port D */
168 { /* conf ppar psor pdir podr pdat */ 168 { /* conf ppar psor pdir podr pdat */
169 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 169 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
170 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ 170 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
171 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ 171 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
172 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ 172 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
173 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ 173 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
174 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ 174 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
175 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ 175 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
176 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ 176 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
177 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ 177 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
178 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ 178 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
179 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ 179 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
180 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ 180 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
181 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 181 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
182 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 182 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 183 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
184 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ 184 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
185 #if defined(CONFIG_SOFT_I2C) 185 #if defined(CONFIG_SOFT_I2C)
186 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ 186 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
187 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ 187 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
188 #else 188 #else
189 #if defined(CONFIG_HARD_I2C) 189 #if defined(CONFIG_HARD_I2C)
190 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ 190 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
191 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ 191 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
192 #else /* normal I/O port pins */ 192 #else /* normal I/O port pins */
193 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ 193 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
194 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ 194 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
195 #endif 195 #endif
196 #endif 196 #endif
197 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ 197 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
198 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ 198 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
199 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ 199 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
200 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ 200 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
201 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 201 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
202 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 202 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
203 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ 203 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
204 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ 204 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
205 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ 205 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
206 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ 206 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
207 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 207 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
208 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 208 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
209 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 209 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
210 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 210 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
211 } 211 }
212 }; 212 };
213 213
214 #define _NOT_USED_ 0xFFFFFFFF 214 #define _NOT_USED_ 0xFFFFFFFF
215 215
216 /* UPM pattern for bus clock = 66.7 MHz */ 216 /* UPM pattern for bus clock = 66.7 MHz */
217 static const uint upmTable67[] = 217 static const uint upmTable67[] =
218 { 218 {
219 /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ 219 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
220 /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, 220 /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
221 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, 221 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
222 222
223 /* UPM Read Burst RAM array entry -> unused */ 223 /* UPM Read Burst RAM array entry -> unused */
224 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 224 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
225 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 225 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
226 226
227 /* UPM Read Burst RAM array entry -> unused */ 227 /* UPM Read Burst RAM array entry -> unused */
228 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 228 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
229 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 229 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
230 230
231 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ 231 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
232 /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 232 /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
233 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, 233 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
234 234
235 /* UPM Write Burst RAM array entry -> unused */ 235 /* UPM Write Burst RAM array entry -> unused */
236 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 236 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
237 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 237 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
238 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 238 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
239 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 239 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
240 240
241 /* UPM Refresh Timer RAM array entry -> unused */ 241 /* UPM Refresh Timer RAM array entry -> unused */
242 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 242 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
243 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 243 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
244 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 244 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
245 245
246 /* UPM Exception RAM array entry -> unsused */ 246 /* UPM Exception RAM array entry -> unsused */
247 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 247 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
248 }; 248 };
249 249
250 /* UPM pattern for bus clock = 100 MHz */ 250 /* UPM pattern for bus clock = 100 MHz */
251 static const uint upmTable100[] = 251 static const uint upmTable100[] =
252 { 252 {
253 /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ 253 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
254 /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, 254 /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
255 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, 255 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
256 256
257 /* UPM Read Burst RAM array entry -> unused */ 257 /* UPM Read Burst RAM array entry -> unused */
258 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 258 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
259 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 259 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
260 260
261 /* UPM Read Burst RAM array entry -> unused */ 261 /* UPM Read Burst RAM array entry -> unused */
262 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 262 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
263 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 263 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
264 264
265 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ 265 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
266 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, 266 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
267 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, 267 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
268 268
269 /* UPM Write Burst RAM array entry -> unused */ 269 /* UPM Write Burst RAM array entry -> unused */
270 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 270 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
271 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 271 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
272 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 272 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
273 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 273 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
274 274
275 /* UPM Refresh Timer RAM array entry -> unused */ 275 /* UPM Refresh Timer RAM array entry -> unused */
276 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 276 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
277 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 277 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
278 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 278 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
279 279
280 /* UPM Exception RAM array entry -> unsused */ 280 /* UPM Exception RAM array entry -> unsused */
281 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 281 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
282 }; 282 };
283 283
284 /* UPM pattern for bus clock = 133.3 MHz */ 284 /* UPM pattern for bus clock = 133.3 MHz */
285 static const uint upmTable133[] = 285 static const uint upmTable133[] =
286 { 286 {
287 /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ 287 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
288 /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, 288 /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
289 /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, 289 /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
290 290
291 /* UPM Read Burst RAM array entry -> unused */ 291 /* UPM Read Burst RAM array entry -> unused */
292 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 292 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
293 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 293 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
294 294
295 /* UPM Read Burst RAM array entry -> unused */ 295 /* UPM Read Burst RAM array entry -> unused */
296 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 296 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
297 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 297 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
298 298
299 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ 299 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
300 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, 300 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
301 /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, 301 /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
302 302
303 /* UPM Write Burst RAM array entry -> unused */ 303 /* UPM Write Burst RAM array entry -> unused */
304 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 304 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
305 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 305 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
306 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 306 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
307 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 307 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
308 308
309 /* UPM Refresh Timer RAM array entry -> unused */ 309 /* UPM Refresh Timer RAM array entry -> unused */
310 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 310 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
311 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 311 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
312 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 312 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
313 313
314 /* UPM Exception RAM array entry -> unsused */ 314 /* UPM Exception RAM array entry -> unsused */
315 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 315 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
316 }; 316 };
317 317
318 static int chipsel = 0; 318 static int chipsel = 0;
319 319
320 /* UPM pattern for slow init */ 320 /* UPM pattern for slow init */
321 static const uint upmTableSlow[] = 321 static const uint upmTableSlow[] =
322 { 322 {
323 /* Offset */ /* UPM Read Single RAM array entry */ 323 /* Offset UPM Read Single RAM array entry */
324 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, 324 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
325 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, 325 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
326 326
327 /* UPM Read Burst RAM array entry -> unused */ 327 /* UPM Read Burst RAM array entry -> unused */
328 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 328 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
329 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 329 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
330 330
331 /* UPM Read Burst RAM array entry -> unused */ 331 /* UPM Read Burst RAM array entry -> unused */
332 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 332 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
333 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 333 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
334 334
335 /* UPM Write Single RAM array entry */ 335 /* UPM Write Single RAM array entry */
336 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, 336 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
337 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, 337 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
338 338
339 /* UPM Write Burst RAM array entry -> unused */ 339 /* UPM Write Burst RAM array entry -> unused */
340 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 340 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
341 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 341 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
342 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 342 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
343 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 343 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
344 344
345 /* UPM Refresh Timer RAM array entry -> unused */ 345 /* UPM Refresh Timer RAM array entry -> unused */
346 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 346 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
347 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 347 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
348 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 348 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
349 349
350 /* UPM Exception RAM array entry -> unused */ 350 /* UPM Exception RAM array entry -> unused */
351 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 351 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
352 }; 352 };
353 353
354 /* UPM pattern for fast init */ 354 /* UPM pattern for fast init */
355 static const uint upmTableFast[] = 355 static const uint upmTableFast[] =
356 { 356 {
357 /* Offset */ /* UPM Read Single RAM array entry */ 357 /* Offset UPM Read Single RAM array entry */
358 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, 358 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
359 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, 359 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
360 360
361 /* UPM Read Burst RAM array entry -> unused */ 361 /* UPM Read Burst RAM array entry -> unused */
362 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 362 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
363 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 363 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
364 364
365 /* UPM Read Burst RAM array entry -> unused */ 365 /* UPM Read Burst RAM array entry -> unused */
366 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 366 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
367 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 367 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
368 368
369 /* UPM Write Single RAM array entry */ 369 /* UPM Write Single RAM array entry */
370 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, 370 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
371 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, 371 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
372 372
373 /* UPM Write Burst RAM array entry -> unused */ 373 /* UPM Write Burst RAM array entry -> unused */
374 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 374 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
375 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 375 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
376 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 376 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
377 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 377 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
378 378
379 /* UPM Refresh Timer RAM array entry -> unused */ 379 /* UPM Refresh Timer RAM array entry -> unused */
380 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 380 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
381 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 381 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
382 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 382 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
383 383
384 /* UPM Exception RAM array entry -> unused */ 384 /* UPM Exception RAM array entry -> unused */
385 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 385 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
386 }; 386 };
387 387
388 388
389 /* ------------------------------------------------------------------------- */ 389 /* ------------------------------------------------------------------------- */
390 390
391 /* Check Board Identity: 391 /* Check Board Identity:
392 */ 392 */
393 int checkboard (void) 393 int checkboard (void)
394 { 394 {
395 char *p = (char *) HWIB_INFO_START_ADDR; 395 char *p = (char *) HWIB_INFO_START_ADDR;
396 396
397 puts ("Board: "); 397 puts ("Board: ");
398 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { 398 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
399 puts (p); 399 puts (p);
400 } else { 400 } else {
401 puts ("No HWIB assuming TQM8272"); 401 puts ("No HWIB assuming TQM8272");
402 } 402 }
403 putc ('\n'); 403 putc ('\n');
404 404
405 return 0; 405 return 0;
406 } 406 }
407 407
408 /* ------------------------------------------------------------------------- */ 408 /* ------------------------------------------------------------------------- */
409 #if defined(CONFIG_BOARD_GET_CPU_CLK_F) 409 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
410 static int get_cas_latency (void) 410 static int get_cas_latency (void)
411 { 411 {
412 /* get it from the option -ts in CIB */ 412 /* get it from the option -ts in CIB */
413 /* default is 3 */ 413 /* default is 3 */
414 int ret = 3; 414 int ret = 3;
415 int pos = 0; 415 int pos = 0;
416 char *p = (char *) CIB_INFO_START_ADDR; 416 char *p = (char *) CIB_INFO_START_ADDR;
417 417
418 while ((*p != '\0') && (pos < CIB_INFO_LEN)) { 418 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
419 if (*p < ' ' || *p > '~') { /* ASCII strings! */ 419 if (*p < ' ' || *p > '~') { /* ASCII strings! */
420 return ret; 420 return ret;
421 } 421 }
422 if (*p == '-') { 422 if (*p == '-') {
423 if ((p[1] == 't') && (p[2] == 's')) { 423 if ((p[1] == 't') && (p[2] == 's')) {
424 return (p[4] - '0'); 424 return (p[4] - '0');
425 } 425 }
426 } 426 }
427 p++; 427 p++;
428 pos++; 428 pos++;
429 } 429 }
430 return ret; 430 return ret;
431 } 431 }
432 #endif 432 #endif
433 433
434 static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) 434 static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
435 { 435 {
436 #if defined(CONFIG_BOARD_GET_CPU_CLK_F) 436 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
437 int clk = board_get_cpu_clk_f (); 437 int clk = board_get_cpu_clk_f ();
438 volatile immap_t *immr = (immap_t *)CFG_IMMR; 438 volatile immap_t *immr = (immap_t *)CFG_IMMR;
439 int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); 439 int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
440 int cas; 440 int cas;
441 441
442 sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ 442 sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
443 PSDMR_BUFCMD); 443 PSDMR_BUFCMD);
444 if (busmode) { 444 if (busmode) {
445 switch (clk) { 445 switch (clk) {
446 case 66666666: 446 case 66666666:
447 sdmr |= (PSDMR_RFRC_66MHZ_60X | \ 447 sdmr |= (PSDMR_RFRC_66MHZ_60X | \
448 PSDMR_PRETOACT_66MHZ_60X | \ 448 PSDMR_PRETOACT_66MHZ_60X | \
449 PSDMR_WRC_66MHZ_60X | \ 449 PSDMR_WRC_66MHZ_60X | \
450 PSDMR_BUFCMD_66MHZ_60X); 450 PSDMR_BUFCMD_66MHZ_60X);
451 break; 451 break;
452 case 100000000: 452 case 100000000:
453 sdmr |= (PSDMR_RFRC_100MHZ_60X | \ 453 sdmr |= (PSDMR_RFRC_100MHZ_60X | \
454 PSDMR_PRETOACT_100MHZ_60X | \ 454 PSDMR_PRETOACT_100MHZ_60X | \
455 PSDMR_WRC_100MHZ_60X | \ 455 PSDMR_WRC_100MHZ_60X | \
456 PSDMR_BUFCMD_100MHZ_60X); 456 PSDMR_BUFCMD_100MHZ_60X);
457 break; 457 break;
458 458
459 } 459 }
460 } else { 460 } else {
461 switch (clk) { 461 switch (clk) {
462 case 66666666: 462 case 66666666:
463 sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ 463 sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
464 PSDMR_PRETOACT_66MHZ_SINGLE | \ 464 PSDMR_PRETOACT_66MHZ_SINGLE | \
465 PSDMR_WRC_66MHZ_SINGLE | \ 465 PSDMR_WRC_66MHZ_SINGLE | \
466 PSDMR_BUFCMD_66MHZ_SINGLE); 466 PSDMR_BUFCMD_66MHZ_SINGLE);
467 break; 467 break;
468 case 100000000: 468 case 100000000:
469 sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ 469 sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
470 PSDMR_PRETOACT_100MHZ_SINGLE | \ 470 PSDMR_PRETOACT_100MHZ_SINGLE | \
471 PSDMR_WRC_100MHZ_SINGLE | \ 471 PSDMR_WRC_100MHZ_SINGLE | \
472 PSDMR_BUFCMD_100MHZ_SINGLE); 472 PSDMR_BUFCMD_100MHZ_SINGLE);
473 break; 473 break;
474 case 133333333: 474 case 133333333:
475 sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ 475 sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
476 PSDMR_PRETOACT_133MHZ_SINGLE | \ 476 PSDMR_PRETOACT_133MHZ_SINGLE | \
477 PSDMR_WRC_133MHZ_SINGLE | \ 477 PSDMR_WRC_133MHZ_SINGLE | \
478 PSDMR_BUFCMD_133MHZ_SINGLE); 478 PSDMR_BUFCMD_133MHZ_SINGLE);
479 break; 479 break;
480 } 480 }
481 } 481 }
482 cas = get_cas_latency(); 482 cas = get_cas_latency();
483 sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); 483 sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
484 sdmr |= cas; 484 sdmr |= cas;
485 sdmr |= ((cas - 1) << 6); 485 sdmr |= ((cas - 1) << 6);
486 return sdmr; 486 return sdmr;
487 #else 487 #else
488 return sdmr; 488 return sdmr;
489 #endif 489 #endif
490 } 490 }
491 491
492 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx 492 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
493 * 493 *
494 * This routine performs standard 8260 initialization sequence 494 * This routine performs standard 8260 initialization sequence
495 * and calculates the available memory size. It may be called 495 * and calculates the available memory size. It may be called
496 * several times to try different SDRAM configurations on both 496 * several times to try different SDRAM configurations on both
497 * 60x and local buses. 497 * 60x and local buses.
498 */ 498 */
499 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, 499 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
500 ulong orx, volatile uchar * base, int col) 500 ulong orx, volatile uchar * base, int col)
501 { 501 {
502 volatile uchar c = 0xff; 502 volatile uchar c = 0xff;
503 volatile uint *sdmr_ptr; 503 volatile uint *sdmr_ptr;
504 volatile uint *orx_ptr; 504 volatile uint *orx_ptr;
505 ulong maxsize, size; 505 ulong maxsize, size;
506 int i; 506 int i;
507 507
508 /* We must be able to test a location outsize the maximum legal size 508 /* We must be able to test a location outsize the maximum legal size
509 * to find out THAT we are outside; but this address still has to be 509 * to find out THAT we are outside; but this address still has to be
510 * mapped by the controller. That means, that the initial mapping has 510 * mapped by the controller. That means, that the initial mapping has
511 * to be (at least) twice as large as the maximum expected size. 511 * to be (at least) twice as large as the maximum expected size.
512 */ 512 */
513 maxsize = (1 + (~orx | 0x7fff)) / 2; 513 maxsize = (1 + (~orx | 0x7fff)) / 2;
514 514
515 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that 515 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
516 * we are configuring CS1 if base != 0 516 * we are configuring CS1 if base != 0
517 */ 517 */
518 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; 518 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
519 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; 519 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
520 520
521 *orx_ptr = orx; 521 *orx_ptr = orx;
522 sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); 522 sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
523 /* 523 /*
524 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): 524 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
525 * 525 *
526 * "At system reset, initialization software must set up the 526 * "At system reset, initialization software must set up the
527 * programmable parameters in the memory controller banks registers 527 * programmable parameters in the memory controller banks registers
528 * (ORx, BRx, P/LSDMR). After all memory parameters are configured, 528 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
529 * system software should execute the following initialization sequence 529 * system software should execute the following initialization sequence
530 * for each SDRAM device. 530 * for each SDRAM device.
531 * 531 *
532 * 1. Issue a PRECHARGE-ALL-BANKS command 532 * 1. Issue a PRECHARGE-ALL-BANKS command
533 * 2. Issue eight CBR REFRESH commands 533 * 2. Issue eight CBR REFRESH commands
534 * 3. Issue a MODE-SET command to initialize the mode register 534 * 3. Issue a MODE-SET command to initialize the mode register
535 * 535 *
536 * The initial commands are executed by setting P/LSDMR[OP] and 536 * The initial commands are executed by setting P/LSDMR[OP] and
537 * accessing the SDRAM with a single-byte transaction." 537 * accessing the SDRAM with a single-byte transaction."
538 * 538 *
539 * The appropriate BRx/ORx registers have already been set when we 539 * The appropriate BRx/ORx registers have already been set when we
540 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. 540 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
541 */ 541 */
542 542
543 *sdmr_ptr = sdmr | PSDMR_OP_PREA; 543 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
544 *base = c; 544 *base = c;
545 545
546 *sdmr_ptr = sdmr | PSDMR_OP_CBRR; 546 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
547 for (i = 0; i < 8; i++) 547 for (i = 0; i < 8; i++)
548 *base = c; 548 *base = c;
549 549
550 *sdmr_ptr = sdmr | PSDMR_OP_MRW; 550 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
551 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ 551 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
552 552
553 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; 553 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
554 *base = c; 554 *base = c;
555 555
556 size = get_ram_size((long *)base, maxsize); 556 size = get_ram_size((long *)base, maxsize);
557 *orx_ptr = orx | ~(size - 1); 557 *orx_ptr = orx | ~(size - 1);
558 558
559 return (size); 559 return (size);
560 } 560 }
561 561
562 long int initdram (int board_type) 562 long int initdram (int board_type)
563 { 563 {
564 volatile immap_t *immap = (immap_t *) CFG_IMMR; 564 volatile immap_t *immap = (immap_t *) CFG_IMMR;
565 volatile memctl8260_t *memctl = &immap->im_memctl; 565 volatile memctl8260_t *memctl = &immap->im_memctl;
566 566
567 #ifndef CFG_RAMBOOT 567 #ifndef CFG_RAMBOOT
568 long size8, size9; 568 long size8, size9;
569 #endif 569 #endif
570 long psize, lsize; 570 long psize, lsize;
571 571
572 psize = 16 * 1024 * 1024; 572 psize = 16 * 1024 * 1024;
573 lsize = 0; 573 lsize = 0;
574 574
575 memctl->memc_psrt = CFG_PSRT; 575 memctl->memc_psrt = CFG_PSRT;
576 memctl->memc_mptpr = CFG_MPTPR; 576 memctl->memc_mptpr = CFG_MPTPR;
577 577
578 #ifndef CFG_RAMBOOT 578 #ifndef CFG_RAMBOOT
579 /* 60x SDRAM setup: 579 /* 60x SDRAM setup:
580 */ 580 */
581 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, 581 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
582 (uchar *) CFG_SDRAM_BASE, 8); 582 (uchar *) CFG_SDRAM_BASE, 8);
583 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, 583 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
584 (uchar *) CFG_SDRAM_BASE, 9); 584 (uchar *) CFG_SDRAM_BASE, 9);
585 585
586 if (size8 < size9) { 586 if (size8 < size9) {
587 psize = size9; 587 psize = size9;
588 printf ("(60x:9COL - %ld MB, ", psize >> 20); 588 printf ("(60x:9COL - %ld MB, ", psize >> 20);
589 } else { 589 } else {
590 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, 590 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
591 (uchar *) CFG_SDRAM_BASE, 8); 591 (uchar *) CFG_SDRAM_BASE, 8);
592 printf ("(60x:8COL - %ld MB, ", psize >> 20); 592 printf ("(60x:8COL - %ld MB, ", psize >> 20);
593 } 593 }
594 594
595 #endif /* CFG_RAMBOOT */ 595 #endif /* CFG_RAMBOOT */
596 596
597 icache_enable (); 597 icache_enable ();
598 598
599 return (psize); 599 return (psize);
600 } 600 }
601 601
602 602
603 static inline int scanChar (char *p, int len, unsigned long *number) 603 static inline int scanChar (char *p, int len, unsigned long *number)
604 { 604 {
605 int akt = 0; 605 int akt = 0;
606 606
607 *number = 0; 607 *number = 0;
608 while (akt < len) 608 while (akt < len) {
609 {
610 if ((*p >= '0') && (*p <= '9')) { 609 if ((*p >= '0') && (*p <= '9')) {
611 *number *= 10; 610 *number *= 10;
612 *number += *p - '0'; 611 *number += *p - '0';
613 p += 1; 612 p += 1;
614 } else { 613 } else {
615 if (*p == '-') return akt; 614 if (*p == '-') return akt;
616 return -1; 615 return -1;
617 } 616 }
618 akt ++; 617 akt ++;
619 } 618 }
620 return akt; 619 return akt;
621 } 620 }
622 621
623 typedef struct{ 622 typedef struct{
624 int Bus; 623 int Bus;
625 int flash; 624 int flash;
626 int flash_nr; 625 int flash_nr;
627 int ram; 626 int ram;
628 int ram_cs; 627 int ram_cs;
629 int nand; 628 int nand;
630 int nand_cs; 629 int nand_cs;
631 int eeprom; 630 int eeprom;
632 int can; 631 int can;
633 unsigned long cpunr; 632 unsigned long cpunr;
634 unsigned long option; 633 unsigned long option;
635 int SecEng; 634 int SecEng;
636 int cpucl; 635 int cpucl;
637 int cpmcl; 636 int cpmcl;
638 int buscl; 637 int buscl;
639 int busclk_real_ok; 638 int busclk_real_ok;
640 int busclk_real; 639 int busclk_real;
641 unsigned char OK; 640 unsigned char OK;
642 unsigned char ethaddr[20]; 641 unsigned char ethaddr[20];
643 } HWIB_INFO; 642 } HWIB_INFO;
644 643
645 HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, 644 HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
646 0, 0, 0, 0, 0, 0}; 645 0, 0, 0, 0, 0, 0};
647 646
648 static int dump_hwib(void) 647 static int dump_hwib(void)
649 { 648 {
650 HWIB_INFO *hw = &hwinf; 649 HWIB_INFO *hw = &hwinf;
651 volatile immap_t *immr = (immap_t *)CFG_IMMR; 650 volatile immap_t *immr = (immap_t *)CFG_IMMR;
652 char *s = getenv("serial#"); 651 char *s = getenv("serial#");
653 652
654 if (hw->OK) { 653 if (hw->OK) {
655 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); 654 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
656 printf ("serial : %s\n", s); 655 printf ("serial : %s\n", s);
657 printf ("ethaddr: %s\n", hw->ethaddr); 656 printf ("ethaddr: %s\n", hw->ethaddr);
658 printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); 657 printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
659 printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); 658 printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
660 printf ("CPU : %d\n", hw->cpunr); 659 printf ("CPU : %d\n", hw->cpunr);
661 printf ("CAN : %d\n", hw->can); 660 printf ("CAN : %d\n", hw->can);
662 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); 661 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
663 else printf ("No EEprom\n"); 662 else printf ("No EEprom\n");
664 if (hw->nand) { 663 if (hw->nand) {
665 printf ("NAND : %x\n", hw->nand); 664 printf ("NAND : %x\n", hw->nand);
666 printf ("NAND CS: %d\n", hw->nand_cs); 665 printf ("NAND CS: %d\n", hw->nand_cs);
667 } else { printf ("No NAND\n");} 666 } else { printf ("No NAND\n");}
668 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); 667 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
669 printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ 668 printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
670 "60x" : "Single PQII")); 669 "60x" : "Single PQII"));
671 printf ("Option : %x\n", hw->option); 670 printf ("Option : %x\n", hw->option);
672 printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); 671 printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
673 printf ("CPM Clk: %d\n", hw->cpmcl); 672 printf ("CPM Clk: %d\n", hw->cpmcl);
674 printf ("CPU Clk: %d\n", hw->cpucl); 673 printf ("CPU Clk: %d\n", hw->cpucl);
675 printf ("Bus Clk: %d\n", hw->buscl); 674 printf ("Bus Clk: %d\n", hw->buscl);
676 if (hw->busclk_real_ok) { 675 if (hw->busclk_real_ok) {
677 printf (" real Clk: %d\n", hw->busclk_real); 676 printf (" real Clk: %d\n", hw->busclk_real);
678 } 677 }
679 printf ("CAS : %d\n", get_cas_latency()); 678 printf ("CAS : %d\n", get_cas_latency());
680 } else { 679 } else {
681 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); 680 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
682 } 681 }
683 return 0; 682 return 0;
684 } 683 }
685 684
686 static inline int search_real_busclk (int *clk) 685 static inline int search_real_busclk (int *clk)
687 { 686 {
688 int part = 0, pos = 0; 687 int part = 0, pos = 0;
689 char *p = (char *) CIB_INFO_START_ADDR; 688 char *p = (char *) CIB_INFO_START_ADDR;
690 int ok = 0; 689 int ok = 0;
691 690
692 while ((*p != '\0') && (pos < CIB_INFO_LEN)) { 691 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
693 if (*p < ' ' || *p > '~') { /* ASCII strings! */ 692 if (*p < ' ' || *p > '~') { /* ASCII strings! */
694 return 0; 693 return 0;
695 } 694 }
696 switch (part) { 695 switch (part) {
697 default: 696 default:
698 if (*p == '-') { 697 if (*p == '-') {
699 ++part; 698 ++part;
700 } 699 }
701 break; 700 break;
702 case 3: 701 case 3:
703 if (*p == '-') { 702 if (*p == '-') {
704 ++part; 703 ++part;
705 break; 704 break;
706 } 705 }
707 if (*p == 'b') { 706 if (*p == 'b') {
708 ok = 1; 707 ok = 1;
709 p++; 708 p++;
710 break; 709 break;
711 } 710 }
712 if (ok) { 711 if (ok) {
713 switch (*p) { 712 switch (*p) {
714 case '6': 713 case '6':
715 *clk = 66666666; 714 *clk = 66666666;
716 return 1; 715 return 1;
717 break; 716 break;
718 case '1': 717 case '1':
719 if (p[1] == '3') { 718 if (p[1] == '3') {
720 *clk = 133333333; 719 *clk = 133333333;
721 } else { 720 } else {
722 *clk = 100000000; 721 *clk = 100000000;
723 } 722 }
724 return 1; 723 return 1;
725 break; 724 break;
726 } 725 }
727 } 726 }
728 break; 727 break;
729 } 728 }
730 p++; 729 p++;
731 } 730 }
732 return 0; 731 return 0;
733 } 732 }
734 733
735 int analyse_hwib (void) 734 int analyse_hwib (void)
736 { 735 {
737 char *p = (char *) HWIB_INFO_START_ADDR; 736 char *p = (char *) HWIB_INFO_START_ADDR;
738 int anz; 737 int anz;
739 int part = 1, i = 0, pos = 0; 738 int part = 1, i = 0, pos = 0;
740 HWIB_INFO *hw = &hwinf; 739 HWIB_INFO *hw = &hwinf;
741 740
742 deb_printf(" %s pointer: %p\n", __FUNCTION__, p); 741 deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
743 /* Head = TQM */ 742 /* Head = TQM */
744 if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) { 743 if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
745 deb_printf("No HWIB\n"); 744 deb_printf("No HWIB\n");
746 return -1; 745 return -1;
747 } 746 }
748 p += 3; 747 p += 3;
749 if (scanChar (p, 4, &hw->cpunr) < 0) { 748 if (scanChar (p, 4, &hw->cpunr) < 0) {
750 deb_printf("No CPU\n"); 749 deb_printf("No CPU\n");
751 return -2; 750 return -2;
752 } 751 }
753 p +=4; 752 p +=4;
754 753
755 hw->flash = 0x200000 << (*p - 'A'); 754 hw->flash = 0x200000 << (*p - 'A');
756 p++; 755 p++;
757 hw->flash_nr = *p - '0'; 756 hw->flash_nr = *p - '0';
758 p++; 757 p++;
759 758
760 hw->ram = 0x2000000 << (*p - 'A'); 759 hw->ram = 0x2000000 << (*p - 'A');
761 p++; 760 p++;
762 if (*p == '2') { 761 if (*p == '2') {
763 hw->ram_cs = 2; 762 hw->ram_cs = 2;
764 p++; 763 p++;
765 } 764 }
766 765
767 if (*p == 'A') hw->can = 1; 766 if (*p == 'A') hw->can = 1;
768 if (*p == 'B') hw->can = 2; 767 if (*p == 'B') hw->can = 2;
769 p +=1; 768 p +=1;
770 p +=1; /* connector */ 769 p +=1; /* connector */
771 if (*p != '0') { 770 if (*p != '0') {
772 hw->eeprom = 0x100 << (*p - 'A'); 771 hw->eeprom = 0x100 << (*p - 'A');
773 } 772 }
774 p++; 773 p++;
775 774
776 if ((*p < '0') || (*p > '9')) { 775 if ((*p < '0') || (*p > '9')) {
777 /* NAND before z-option */ 776 /* NAND before z-option */
778 hw->nand = 0x8000000 << (*p - 'A'); 777 hw->nand = 0x8000000 << (*p - 'A');
779 p++; 778 p++;
780 hw->nand_cs = *p - '0'; 779 hw->nand_cs = *p - '0';
781 p += 2; 780 p += 2;
782 } 781 }
783 /* z-option */ 782 /* z-option */
784 anz = scanChar (p, 4, &hw->option); 783 anz = scanChar (p, 4, &hw->option);
785 if (anz < 0) { 784 if (anz < 0) {
786 deb_printf("No option\n"); 785 deb_printf("No option\n");
787 return -3; 786 return -3;
788 } 787 }
789 if (hw->option & 0x8) hw->Bus = 1; 788 if (hw->option & 0x8) hw->Bus = 1;
790 p += anz; 789 p += anz;
791 if (*p != '-') { 790 if (*p != '-') {
792 deb_printf("No -\n"); 791 deb_printf("No -\n");
793 return -4; 792 return -4;
794 } 793 }
795 p++; 794 p++;
796 /* C option */ 795 /* C option */
797 if (*p == 'E') { 796 if (*p == 'E') {
798 hw->SecEng = 1; 797 hw->SecEng = 1;
799 p++; 798 p++;
800 } 799 }
801 switch (*p) { 800 switch (*p) {
802 case 'M': hw->cpucl = 266666666; 801 case 'M': hw->cpucl = 266666666;
803 break; 802 break;
804 case 'P': hw->cpucl = 300000000; 803 case 'P': hw->cpucl = 300000000;
805 break; 804 break;
806 case 'T': hw->cpucl = 400000000; 805 case 'T': hw->cpucl = 400000000;
807 break; 806 break;
808 default: 807 default:
809 deb_printf("No CPU Clk: %c\n", *p); 808 deb_printf("No CPU Clk: %c\n", *p);
810 return -5; 809 return -5;
811 break; 810 break;
812 } 811 }
813 p++; 812 p++;
814 switch (*p) { 813 switch (*p) {
815 case 'I': hw->cpmcl = 200000000; 814 case 'I': hw->cpmcl = 200000000;
816 break; 815 break;
817 case 'M': hw->cpmcl = 300000000; 816 case 'M': hw->cpmcl = 300000000;
818 break; 817 break;
819 default: 818 default:
820 deb_printf("No CPM Clk\n"); 819 deb_printf("No CPM Clk\n");
821 return -6; 820 return -6;
822 break; 821 break;
823 } 822 }
824 p++; 823 p++;
825 switch (*p) { 824 switch (*p) {
826 case 'B': hw->buscl = 66666666; 825 case 'B': hw->buscl = 66666666;
827 break; 826 break;
828 case 'E': hw->buscl = 100000000; 827 case 'E': hw->buscl = 100000000;
829 break; 828 break;
830 case 'F': hw->buscl = 133333333; 829 case 'F': hw->buscl = 133333333;
831 break; 830 break;
832 default: 831 default:
833 deb_printf("No BUS Clk\n"); 832 deb_printf("No BUS Clk\n");
834 return -7; 833 return -7;
835 break; 834 break;
836 } 835 }
837 p++; 836 p++;
838 837
839 hw->OK = 1; 838 hw->OK = 1;
840 /* search MAC Address */ 839 /* search MAC Address */
841 while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) { 840 while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
842 if (*p < ' ' || *p > '~') { /* ASCII strings! */ 841 if (*p < ' ' || *p > '~') { /* ASCII strings! */
843 return 0; 842 return 0;
844 } 843 }
845 switch (part) { 844 switch (part) {
846 default: 845 default:
847 if (*p == ' ') { 846 if (*p == ' ') {
848 ++part; 847 ++part;
849 i = 0; 848 i = 0;
850 } 849 }
851 break; 850 break;
852 case 3: /* Copy MAC address */ 851 case 3: /* Copy MAC address */
853 if (*p == ' ') { 852 if (*p == ' ') {
854 ++part; 853 ++part;
855 i = 0; 854 i = 0;
856 break; 855 break;
857 } 856 }
858 hw->ethaddr[i++] = *p; 857 hw->ethaddr[i++] = *p;
859 if ((i % 3) == 2) 858 if ((i % 3) == 2)
860 hw->ethaddr[i++] = ':'; 859 hw->ethaddr[i++] = ':';
861 break; 860 break;
862 861
863 } 862 }
864 p++; 863 p++;
865 } 864 }
866 865
867 hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); 866 hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
868 return 0; 867 return 0;
869 } 868 }
870 869
871 #if defined(CONFIG_GET_CPU_STR_F) 870 #if defined(CONFIG_GET_CPU_STR_F)
872 /* !! This routine runs from Flash */ 871 /* !! This routine runs from Flash */
873 char get_cpu_str_f (char *buf) 872 char get_cpu_str_f (char *buf)
874 { 873 {
875 char *p = (char *) HWIB_INFO_START_ADDR; 874 char *p = (char *) HWIB_INFO_START_ADDR;
876 int i = 0; 875 int i = 0;
877 876
878 buf[i++] = 'M'; 877 buf[i++] = 'M';
879 buf[i++] = 'P'; 878 buf[i++] = 'P';
880 buf[i++] = 'C'; 879 buf[i++] = 'C';
881 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { 880 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
882 buf[i++] = *&p[3]; 881 buf[i++] = *&p[3];
883 buf[i++] = *&p[4]; 882 buf[i++] = *&p[4];
884 buf[i++] = *&p[5]; 883 buf[i++] = *&p[5];
885 buf[i++] = *&p[6]; 884 buf[i++] = *&p[6];
886 } else { 885 } else {
887 buf[i++] = '8'; 886 buf[i++] = '8';
888 buf[i++] = '2'; 887 buf[i++] = '2';
889 buf[i++] = '7'; 888 buf[i++] = '7';
890 buf[i++] = 'x'; 889 buf[i++] = 'x';
891 } 890 }
892 buf[i++] = 0; 891 buf[i++] = 0;
893 return 0; 892 return 0;
894 } 893 }
895 #endif 894 #endif
896 895
897 #if defined(CONFIG_BOARD_GET_CPU_CLK_F) 896 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
898 /* !! This routine runs from Flash */ 897 /* !! This routine runs from Flash */
899 unsigned long board_get_cpu_clk_f (void) 898 unsigned long board_get_cpu_clk_f (void)
900 { 899 {
901 char *p = (char *) HWIB_INFO_START_ADDR; 900 char *p = (char *) HWIB_INFO_START_ADDR;
902 int i = 0; 901 int i = 0;
903 902
904 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { 903 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
905 if (search_real_busclk (&i)) 904 if (search_real_busclk (&i))
906 return i; 905 return i;
907 } 906 }
908 return CONFIG_8260_CLKIN; 907 return CONFIG_8260_CLKIN;
909 } 908 }
910 #endif 909 #endif
911 910
912 #if CONFIG_BOARD_EARLY_INIT_R 911 #if CONFIG_BOARD_EARLY_INIT_R
913 912
914 static int can_test (unsigned long off) 913 static int can_test (unsigned long off)
915 { 914 {
916 volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off); 915 volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off);
917 916
918 *(base + 0x17) = 'T'; 917 *(base + 0x17) = 'T';
919 *(base + 0x18) = 'Q'; 918 *(base + 0x18) = 'Q';
920 *(base + 0x19) = 'M'; 919 *(base + 0x19) = 'M';
921 if ((*(base + 0x17) != 'T') || 920 if ((*(base + 0x17) != 'T') ||
922 (*(base + 0x18) != 'Q') || 921 (*(base + 0x18) != 'Q') ||
923 (*(base + 0x19) != 'M')) { 922 (*(base + 0x19) != 'M')) {
924 return 0; 923 return 0;
925 } 924 }
926 return 1; 925 return 1;
927 } 926 }
928 927
929 static int can_config_one (unsigned long off) 928 static int can_config_one (unsigned long off)
930 { 929 {
931 volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off); 930 volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off);
932 volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02); 931 volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
933 volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f); 932 volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
934 unsigned char temp; 933 unsigned char temp;
935 934
936 *cpu_if = 0x45; 935 *cpu_if = 0x45;
937 temp = *ctrl; 936 temp = *ctrl;
938 temp |= 0x40; 937 temp |= 0x40;
939 *ctrl = temp; 938 *ctrl = temp;
940 *clkout = 0x20; 939 *clkout = 0x20;
941 temp = *ctrl; 940 temp = *ctrl;
942 temp &= ~0x40; 941 temp &= ~0x40;
943 *ctrl = temp; 942 *ctrl = temp;
944 return 0; 943 return 0;
945 } 944 }
946 945
947 static int can_config (void) 946 static int can_config (void)
948 { 947 {
949 int ret = 0; 948 int ret = 0;
950 can_config_one (0); 949 can_config_one (0);
951 if (hwinf.can == 2) { 950 if (hwinf.can == 2) {
952 can_config_one (0x100); 951 can_config_one (0x100);
953 } 952 }
954 /* make Test if they really there */ 953 /* make Test if they really there */
955 ret += can_test (0); 954 ret += can_test (0);
956 ret += can_test (0x100); 955 ret += can_test (0x100);
957 return ret; 956 return ret;
958 } 957 }
959 958
960 static int init_can (void) 959 static int init_can (void)
961 { 960 {
962 volatile immap_t * immr = (immap_t *)CFG_IMMR; 961 volatile immap_t * immr = (immap_t *)CFG_IMMR;
963 volatile memctl8260_t *memctl = &immr->im_memctl; 962 volatile memctl8260_t *memctl = &immr->im_memctl;
964 int count = 0; 963 int count = 0;
965 964
966 if ((hwinf.OK) && (hwinf.can)) { 965 if ((hwinf.OK) && (hwinf.can)) {
967 memctl->memc_or4 = CFG_CAN_OR; 966 memctl->memc_or4 = CFG_CAN_OR;
968 memctl->memc_br4 = CFG_CAN_BR; 967 memctl->memc_br4 = CFG_CAN_BR;
969 /* upm Init */ 968 /* upm Init */
970 upmconfig (UPMC, (uint *) upmTableFast, 969 upmconfig (UPMC, (uint *) upmTableFast,
971 sizeof (upmTableFast) / sizeof (uint)); 970 sizeof (upmTableFast) / sizeof (uint));
972 memctl->memc_mcmr = (MxMR_DSx_3_CYCL | 971 memctl->memc_mcmr = (MxMR_DSx_3_CYCL |
973 MxMR_GPL_x4DIS | 972 MxMR_GPL_x4DIS |
974 MxMR_RLFx_2X | 973 MxMR_RLFx_2X |
975 MxMR_WLFx_2X | 974 MxMR_WLFx_2X |
976 MxMR_OP_NORM); 975 MxMR_OP_NORM);
977 /* can configure */ 976 /* can configure */
978 count = can_config (); 977 count = can_config ();
979 printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE); 978 printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE);
980 if (hwinf.can != count) printf("!!! difference to HWIB\n"); 979 if (hwinf.can != count) printf("!!! difference to HWIB\n");
981 } else { 980 } else {
982 printf ("CAN: No\n"); 981 printf ("CAN: No\n");
983 } 982 }
984 return 0; 983 return 0;
985 } 984 }
986 985
987 int board_early_init_r(void) 986 int board_early_init_r(void)
988 { 987 {
989 analyse_hwib (); 988 analyse_hwib ();
990 init_can (); 989 init_can ();
991 return 0; 990 return 0;
992 } 991 }
993 #endif 992 #endif
994 993
995 int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) 994 int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
996 { 995 {
997 dump_hwib (); 996 dump_hwib ();
998 return 0; 997 return 0;
999 } 998 }
1000 999
1001 U_BOOT_CMD( 1000 U_BOOT_CMD(
1002 hwib, 1, 1, do_hwib_dump, 1001 hwib, 1, 1, do_hwib_dump,
1003 "hwib - dump HWIB'\n", 1002 "hwib - dump HWIB'\n",
1004 "\n" 1003 "\n"
1005 ); 1004 );
1006 1005
1007 #ifdef CFG_UPDATE_FLASH_SIZE 1006 #ifdef CFG_UPDATE_FLASH_SIZE
1008 static int get_flash_timing (void) 1007 static int get_flash_timing (void)
1009 { 1008 {
1010 /* get it from the option -tf in CIB */ 1009 /* get it from the option -tf in CIB */
1011 /* default is 0x00000c84 */ 1010 /* default is 0x00000c84 */
1012 int ret = 0x00000c84; 1011 int ret = 0x00000c84;
1013 int pos = 0; 1012 int pos = 0;
1014 int nr = 0; 1013 int nr = 0;
1015 char *p = (char *) CIB_INFO_START_ADDR; 1014 char *p = (char *) CIB_INFO_START_ADDR;
1016 1015
1017 while ((*p != '\0') && (pos < CIB_INFO_LEN)) { 1016 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
1018 if (*p < ' ' || *p > '~') { /* ASCII strings! */ 1017 if (*p < ' ' || *p > '~') { /* ASCII strings! */
1019 return ret; 1018 return ret;
1020 } 1019 }
1021 if (*p == '-') { 1020 if (*p == '-') {
1022 if ((p[1] == 't') && (p[2] == 'f')) { 1021 if ((p[1] == 't') && (p[2] == 'f')) {
1023 p += 6; 1022 p += 6;
1024 ret = 0; 1023 ret = 0;
1025 while (nr < 8) { 1024 while (nr < 8) {
1026 if ((*p >= '0') && (*p <= '9')) { 1025 if ((*p >= '0') && (*p <= '9')) {
1027 ret *= 0x10; 1026 ret *= 0x10;
1028 ret += *p - '0'; 1027 ret += *p - '0';
1029 p += 1; 1028 p += 1;
1030 nr ++; 1029 nr ++;
1031 } else if ((*p >= 'A') && (*p <= 'F')) { 1030 } else if ((*p >= 'A') && (*p <= 'F')) {
1032 ret *= 10; 1031 ret *= 10;
1033 ret += *p - '7'; 1032 ret += *p - '7';
1034 p += 1; 1033 p += 1;
1035 nr ++; 1034 nr ++;
1036 } else { 1035 } else {
1037 if (nr < 8) return 0x00000c84; 1036 if (nr < 8) return 0x00000c84;
1038 return ret; 1037 return ret;
1039 } 1038 }
1040 } 1039 }
1041 } 1040 }
1042 } 1041 }
1043 p++; 1042 p++;
1044 pos++; 1043 pos++;
1045 } 1044 }
1046 return ret; 1045 return ret;
1047 } 1046 }
1048 1047
1049 /* Update the Flash_Size and the Flash Timing */ 1048 /* Update the Flash_Size and the Flash Timing */
1050 int update_flash_size (int flash_size) 1049 int update_flash_size (int flash_size)
1051 { 1050 {
1052 volatile immap_t * immr = (immap_t *)CFG_IMMR; 1051 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1053 volatile memctl8260_t *memctl = &immr->im_memctl; 1052 volatile memctl8260_t *memctl = &immr->im_memctl;
1054 unsigned long reg; 1053 unsigned long reg;
1055 unsigned long tim; 1054 unsigned long tim;
1056 1055
1057 /* I must use reg, otherwise the board hang */ 1056 /* I must use reg, otherwise the board hang */
1058 reg = memctl->memc_or0; 1057 reg = memctl->memc_or0;
1059 reg &= ~ORxU_AM_MSK; 1058 reg &= ~ORxU_AM_MSK;
1060 reg |= MEG_TO_AM(flash_size >> 20); 1059 reg |= MEG_TO_AM(flash_size >> 20);
1061 tim = get_flash_timing (); 1060 tim = get_flash_timing ();
1062 reg &= ~0xfff; 1061 reg &= ~0xfff;
1063 reg |= (tim & 0xfff); 1062 reg |= (tim & 0xfff);
1064 memctl->memc_or0 = reg; 1063 memctl->memc_or0 = reg;
1065 return 0; 1064 return 0;
1066 } 1065 }
1067 #endif 1066 #endif
1068 1067
1069 #if (CONFIG_COMMANDS & CFG_CMD_NAND) 1068 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
1070 1069
1071 #include <nand.h> 1070 #include <nand.h>
1072 #include <linux/mtd/mtd.h> 1071 #include <linux/mtd/mtd.h>
1073 1072
1074 static u8 hwctl = 0; 1073 static u8 hwctl = 0;
1075 1074
1076 static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd) 1075 static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
1077 { 1076 {
1078 switch (cmd) { 1077 switch (cmd) {
1079 case NAND_CTL_SETCLE: 1078 case NAND_CTL_SETCLE:
1080 hwctl |= 0x1; 1079 hwctl |= 0x1;
1081 break; 1080 break;
1082 case NAND_CTL_CLRCLE: 1081 case NAND_CTL_CLRCLE:
1083 hwctl &= ~0x1; 1082 hwctl &= ~0x1;
1084 break; 1083 break;
1085 1084
1086 case NAND_CTL_SETALE: 1085 case NAND_CTL_SETALE:
1087 hwctl |= 0x2; 1086 hwctl |= 0x2;
1088 break; 1087 break;
1089 1088
1090 case NAND_CTL_CLRALE: 1089 case NAND_CTL_CLRALE:
1091 hwctl &= ~0x2; 1090 hwctl &= ~0x2;
1092 break; 1091 break;
1093 } 1092 }
1094 } 1093 }
1095 1094
1096 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) 1095 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
1097 { 1096 {
1098 struct nand_chip *this = mtdinfo->priv; 1097 struct nand_chip *this = mtdinfo->priv;
1099 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); 1098 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1100 1099
1101 if (hwctl & 0x1) { 1100 if (hwctl & 0x1) {
1102 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); 1101 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
1103 } else if (hwctl & 0x2) { 1102 } else if (hwctl & 0x2) {
1104 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); 1103 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
1105 } else { 1104 } else {
1106 WRITE_NAND(byte, base); 1105 WRITE_NAND(byte, base);
1107 } 1106 }
1108 } 1107 }
1109 1108
1110 static u_char upmnand_read_byte(struct mtd_info *mtdinfo) 1109 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
1111 { 1110 {
1112 struct nand_chip *this = mtdinfo->priv; 1111 struct nand_chip *this = mtdinfo->priv;
1113 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); 1112 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1114 1113
1115 return READ_NAND(base); 1114 return READ_NAND(base);
1116 } 1115 }
1117 1116
1118 static int tqm8272_dev_ready(struct mtd_info *mtdinfo) 1117 static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
1119 { 1118 {
1120 /* constant delay (see also tR in the datasheet) */ 1119 /* constant delay (see also tR in the datasheet) */
1121 udelay(12); \ 1120 udelay(12); \
1122 return 1; 1121 return 1;
1123 } 1122 }
1124 1123
1125 #ifndef CONFIG_NAND_SPL 1124 #ifndef CONFIG_NAND_SPL
1126 static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) 1125 static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
1127 { 1126 {
1128 struct nand_chip *this = mtdinfo->priv; 1127 struct nand_chip *this = mtdinfo->priv;
1129 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); 1128 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1130 int i; 1129 int i;
1131 1130
1132 for (i = 0; i< len; i++) 1131 for (i = 0; i< len; i++)
1133 buf[i] = *base; 1132 buf[i] = *base;
1134 } 1133 }
1135 1134
1136 static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) 1135 static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1137 { 1136 {
1138 struct nand_chip *this = mtdinfo->priv; 1137 struct nand_chip *this = mtdinfo->priv;
1139 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); 1138 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1140 int i; 1139 int i;
1141 1140
1142 for (i = 0; i< len; i++) 1141 for (i = 0; i< len; i++)
1143 *base = buf[i]; 1142 *base = buf[i];
1144 } 1143 }
1145 1144
1146 static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) 1145 static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1147 { 1146 {
1148 struct nand_chip *this = mtdinfo->priv; 1147 struct nand_chip *this = mtdinfo->priv;
1149 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); 1148 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1150 int i; 1149 int i;
1151 1150
1152 for (i = 0; i < len; i++) 1151 for (i = 0; i < len; i++)
1153 if (buf[i] != *base) 1152 if (buf[i] != *base)
1154 return -1; 1153 return -1;
1155 return 0; 1154 return 0;
1156 } 1155 }
1157 #endif /* #ifndef CONFIG_NAND_SPL */ 1156 #endif /* #ifndef CONFIG_NAND_SPL */
1158 1157
1159 void board_nand_select_device(struct nand_chip *nand, int chip) 1158 void board_nand_select_device(struct nand_chip *nand, int chip)
1160 { 1159 {
1161 chipsel = chip; 1160 chipsel = chip;
1162 } 1161 }
1163 1162
1164 int board_nand_init(struct nand_chip *nand) 1163 int board_nand_init(struct nand_chip *nand)
1165 { 1164 {
1166 static int UpmInit = 0; 1165 static int UpmInit = 0;
1167 volatile immap_t * immr = (immap_t *)CFG_IMMR; 1166 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1168 volatile memctl8260_t *memctl = &immr->im_memctl; 1167 volatile memctl8260_t *memctl = &immr->im_memctl;
1169 1168
1170 if (hwinf.nand == 0) return -1; 1169 if (hwinf.nand == 0) return -1;
1171 1170
1172 /* Setup the UPM */ 1171 /* Setup the UPM */
1173 if (UpmInit == 0) { 1172 if (UpmInit == 0) {
1174 switch (hwinf.busclk_real) { 1173 switch (hwinf.busclk_real) {
1175 case 100000000: 1174 case 100000000:
1176 upmconfig (UPMB, (uint *) upmTable100, 1175 upmconfig (UPMB, (uint *) upmTable100,
1177 sizeof (upmTable100) / sizeof (uint)); 1176 sizeof (upmTable100) / sizeof (uint));
1178 break; 1177 break;
1179 case 133333333: 1178 case 133333333:
1180 upmconfig (UPMB, (uint *) upmTable133, 1179 upmconfig (UPMB, (uint *) upmTable133,
1181 sizeof (upmTable133) / sizeof (uint)); 1180 sizeof (upmTable133) / sizeof (uint));
1182 break; 1181 break;
1183 default: 1182 default:
1184 upmconfig (UPMB, (uint *) upmTable67, 1183 upmconfig (UPMB, (uint *) upmTable67,
1185 sizeof (upmTable67) / sizeof (uint)); 1184 sizeof (upmTable67) / sizeof (uint));
1186 break; 1185 break;
1187 } 1186 }
1188 UpmInit = 1; 1187 UpmInit = 1;
1189 } 1188 }
1190 1189
1191 /* Setup the memctrl */ 1190 /* Setup the memctrl */
1192 memctl->memc_or3 = CFG_NAND_OR; 1191 memctl->memc_or3 = CFG_NAND_OR;
1193 memctl->memc_br3 = CFG_NAND_BR; 1192 memctl->memc_br3 = CFG_NAND_BR;
1194 memctl->memc_mbmr = (MxMR_OP_NORM); 1193 memctl->memc_mbmr = (MxMR_OP_NORM);
1195 1194
1196 nand->eccmode = NAND_ECC_SOFT; 1195 nand->eccmode = NAND_ECC_SOFT;
1197 1196
1198 nand->hwcontrol = upmnand_hwcontrol; 1197 nand->hwcontrol = upmnand_hwcontrol;
1199 nand->read_byte = upmnand_read_byte; 1198 nand->read_byte = upmnand_read_byte;
1200 nand->write_byte = upmnand_write_byte; 1199 nand->write_byte = upmnand_write_byte;
1201 nand->dev_ready = tqm8272_dev_ready; 1200 nand->dev_ready = tqm8272_dev_ready;
1202 1201
1203 #ifndef CONFIG_NAND_SPL 1202 #ifndef CONFIG_NAND_SPL
1204 nand->write_buf = tqm8272_write_buf; 1203 nand->write_buf = tqm8272_write_buf;
1205 nand->read_buf = tqm8272_read_buf; 1204 nand->read_buf = tqm8272_read_buf;
1206 nand->verify_buf = tqm8272_verify_buf; 1205 nand->verify_buf = tqm8272_verify_buf;
1207 #endif 1206 #endif
1208 1207
1209 /* 1208 /*
1210 * Select required NAND chip 1209 * Select required NAND chip
1211 */ 1210 */
1212 board_nand_select_device(nand, 0); 1211 board_nand_select_device(nand, 0);
1213 return 0; 1212 return 0;
1214 } 1213 }
1215 1214
1216 #endif /* CFG_CMD_NAND */ 1215 #endif /* CFG_CMD_NAND */
1217 1216
1218 #ifdef CONFIG_PCI 1217 #ifdef CONFIG_PCI
1219 struct pci_controller hose; 1218 struct pci_controller hose;
1220 1219
1221 int board_early_init_f (void) 1220 int board_early_init_f (void)
1222 { 1221 {
1223 volatile immap_t *immap = (immap_t *) CFG_IMMR; 1222 volatile immap_t *immap = (immap_t *) CFG_IMMR;
1224 1223
1225 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; 1224 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
1226 return 0; 1225 return 0;
1227 } 1226 }
1228 1227
1229 extern void pci_mpc8250_init(struct pci_controller *); 1228 extern void pci_mpc8250_init(struct pci_controller *);
1230 1229
1231 void pci_init_board(void) 1230 void pci_init_board(void)
1232 { 1231 {
1233 pci_mpc8250_init(&hose); 1232 pci_mpc8250_init(&hose);
1234 } 1233 }
1235 #endif 1234 #endif
1236 1235
1237
include/configs/TQM8272.h
Diff comments   View file @ 9c0f42e
1 /* 1 /*
2 * (C) Copyright 2006 2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 /* 24 /*
25 * board/config.h - configuration options, board specific 25 * board/config.h - configuration options, board specific
26 */ 26 */
27 27
28 #ifndef __CONFIG_H 28 #ifndef __CONFIG_H
29 #define __CONFIG_H 29 #define __CONFIG_H
30 30
31 /* 31 /*
32 * High Level Configuration Options 32 * High Level Configuration Options
33 * (easy to change) 33 * (easy to change)
34 */ 34 */
35 35
36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37 #define CONFIG_MPC8272_FAMILY 1 37 #define CONFIG_MPC8272_FAMILY 1
38 #define CONFIG_TQM8272 1 38 #define CONFIG_TQM8272 1
39 39
40 #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ 40 #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
41 #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ 41 #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
42 42
43 #define STK82xx_150 1 /* on a STK82xx.150 */ 43 #define STK82xx_150 1 /* on a STK82xx.150 */
44 44
45 #define CONFIG_CPM2 1 /* Has a CPM2 */ 45 #define CONFIG_CPM2 1 /* Has a CPM2 */
46 46
47 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ 47 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
48 48
49 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 49 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50 50
51 #define CONFIG_BOARD_EARLY_INIT_R 1 51 #define CONFIG_BOARD_EARLY_INIT_R 1
52 52
53 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 53 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
54 #define CONFIG_BAUDRATE 230400 54 #define CONFIG_BAUDRATE 230400
55 #else 55 #else
56 #define CONFIG_BAUDRATE 115200 56 #define CONFIG_BAUDRATE 115200
57 #endif 57 #endif
58 58
59 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" 59 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
60 60
61 #undef CONFIG_BOOTARGS 61 #undef CONFIG_BOOTARGS
62 62
63 #define CONFIG_EXTRA_ENV_SETTINGS \ 63 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "netdev=eth0\0" \ 64 "netdev=eth0\0" \
65 "consdev=ttyCPM0\0" \ 65 "consdev=ttyCPM0\0" \
66 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 66 "nfsargs=setenv bootargs root=/dev/nfs rw " \
67 "nfsroot=${serverip}:${rootpath}\0" \ 67 "nfsroot=${serverip}:${rootpath}\0" \
68 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 68 "ramargs=setenv bootargs root=/dev/ram rw\0" \
69 "hostname=tqm8272\0" \ 69 "hostname=tqm8272\0" \
70 "addip=setenv bootargs ${bootargs} " \ 70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \ 72 ":${hostname}:${netdev}:off panic=1\0" \
73 "addcons=setenv bootargs ${bootargs} " \ 73 "addcons=setenv bootargs ${bootargs} " \
74 "console=$(consdev),$(baudrate)\0" \ 74 "console=$(consdev),$(baudrate)\0" \
75 "flash_nfs=run nfsargs addip addcons;" \ 75 "flash_nfs=run nfsargs addip addcons;" \
76 "bootm ${kernel_addr}\0" \ 76 "bootm ${kernel_addr}\0" \
77 "flash_self=run ramargs addip addcons;" \ 77 "flash_self=run ramargs addip addcons;" \
78 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 78 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 "net_nfs=tftp 300000 ${bootfile};" \ 79 "net_nfs=tftp 300000 ${bootfile};" \
80 "run nfsargs addip addcons;bootm\0" \ 80 "run nfsargs addip addcons;bootm\0" \
81 "rootpath=/opt/eldk/ppc_82xx\0" \ 81 "rootpath=/opt/eldk/ppc_82xx\0" \
82 "bootfile=/tftpboot/tqm8272/uImage\0" \ 82 "bootfile=/tftpboot/tqm8272/uImage\0" \
83 "kernel_addr=40080000\0" \ 83 "kernel_addr=40080000\0" \
84 "ramdisk_addr=40100000\0" \ 84 "ramdisk_addr=40100000\0" \
85 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ 85 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
86 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ 86 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
87 "cp.b 300000 40000000 40000;" \ 87 "cp.b 300000 40000000 40000;" \
88 "setenv filesize;saveenv\0" \ 88 "setenv filesize;saveenv\0" \
89 "cphwib=cp.b 4003fc00 33fc00 400\0" \ 89 "cphwib=cp.b 4003fc00 33fc00 400\0" \
90 "upd=run load;run cphwib;run update\0" \ 90 "upd=run load;run cphwib;run update\0" \
91 "" 91 ""
92 #define CONFIG_BOOTCOMMAND "run flash_self" 92 #define CONFIG_BOOTCOMMAND "run flash_self"
93 93
94 #define CONFIG_I2C 1 94 #define CONFIG_I2C 1
95 95
96 #if CONFIG_I2C 96 #if CONFIG_I2C
97 /* enable I2C and select the hardware/software driver */ 97 /* enable I2C and select the hardware/software driver */
98 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 98 #undef CONFIG_HARD_I2C /* I2C with hardware support */
99 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 99 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
100 #define ADD_CMD_I2C CFG_CMD_I2C | \ 100 #define ADD_CMD_I2C CFG_CMD_I2C | \
101 CFG_CMD_DATE |\ 101 CFG_CMD_DATE |\
102 CFG_CMD_DTT |\ 102 CFG_CMD_DTT |\
103 CFG_CMD_EEPROM 103 CFG_CMD_EEPROM
104 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 104 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
105 #define CFG_I2C_SLAVE 0x7F 105 #define CFG_I2C_SLAVE 0x7F
106 106
107 /* 107 /*
108 * Software (bit-bang) I2C driver configuration 108 * Software (bit-bang) I2C driver configuration
109 */ 109 */
110 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 110 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
111 #define I2C_ACTIVE (iop->pdir |= 0x00010000) 111 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
112 #define I2C_TRISTATE (iop->pdir &= ~0x00010000) 112 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
113 #define I2C_READ ((iop->pdat & 0x00010000) != 0) 113 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
114 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 114 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
115 else iop->pdat &= ~0x00010000 115 else iop->pdat &= ~0x00010000
116 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 116 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
117 else iop->pdat &= ~0x00020000 117 else iop->pdat &= ~0x00020000
118 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 118 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
119 119
120 #define CONFIG_I2C_X 120 #define CONFIG_I2C_X
121 121
122 /* EEPROM */ 122 /* EEPROM */
123 #define CFG_I2C_EEPROM_ADDR_LEN 2 123 #define CFG_I2C_EEPROM_ADDR_LEN 2
124 #define CFG_EEPROM_PAGE_WRITE_BITS 4 124 #define CFG_EEPROM_PAGE_WRITE_BITS 4
125 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 125 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
126 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ 126 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
127 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 127 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
128 128
129 /* I2C RTC */ 129 /* I2C RTC */
130 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ 130 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
131 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 131 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
132 132
133 /* I2C SYSMON (LM75) */ 133 /* I2C SYSMON (LM75) */
134 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 134 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
135 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 135 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
136 #define CFG_DTT_MAX_TEMP 70 136 #define CFG_DTT_MAX_TEMP 70
137 #define CFG_DTT_LOW_TEMP -30 137 #define CFG_DTT_LOW_TEMP -30
138 #define CFG_DTT_HYSTERESIS 3 138 #define CFG_DTT_HYSTERESIS 3
139 139
140 #else 140 #else
141 #undef CONFIG_HARD_I2C 141 #undef CONFIG_HARD_I2C
142 #undef CONFIG_SOFT_I2C 142 #undef CONFIG_SOFT_I2C
143 #define ADD_CMD_I2C 0 143 #define ADD_CMD_I2C 0
144 #endif 144 #endif
145 145
146 /* 146 /*
147 * select serial console configuration 147 * select serial console configuration
148 * 148 *
149 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 149 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
150 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 150 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
151 * for SCC). 151 * for SCC).
152 * 152 *
153 * if CONFIG_CONS_NONE is defined, then the serial console routines must 153 * if CONFIG_CONS_NONE is defined, then the serial console routines must
154 * defined elsewhere (for example, on the cogent platform, there are serial 154 * defined elsewhere (for example, on the cogent platform, there are serial
155 * ports on the motherboard which are used for the serial console - see 155 * ports on the motherboard which are used for the serial console - see
156 * cogent/cma101/serial.[ch]). 156 * cogent/cma101/serial.[ch]).
157 */ 157 */
158 #define CONFIG_CONS_ON_SMC /* define if console on SMC */ 158 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
159 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 159 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
160 #undef CONFIG_CONS_NONE /* define if console on something else*/ 160 #undef CONFIG_CONS_NONE /* define if console on something else*/
161 #ifdef CONFIG_82xx_CONS_SMC1 161 #ifdef CONFIG_82xx_CONS_SMC1
162 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 162 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
163 #endif 163 #endif
164 #ifdef CONFIG_82xx_CONS_SMC2 164 #ifdef CONFIG_82xx_CONS_SMC2
165 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 165 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
166 #endif 166 #endif
167 167
168 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 168 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
169 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 169 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
170 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ 170 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
171 171
172 /* 172 /*
173 * select ethernet configuration 173 * select ethernet configuration
174 * 174 *
175 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 175 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
176 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 176 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
177 * for FCC) 177 * for FCC)
178 * 178 *
179 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 179 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
180 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed 180 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
181 * from CONFIG_COMMANDS to remove support for networking. 181 * from CONFIG_COMMANDS to remove support for networking.
182 * 182 *
183 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the 183 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
184 * X.29 connector, and FCC2 is hardwired to the X.1 connector) 184 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
185 */ 185 */
186 #define CFG_FCC_ETHERNET 186 #define CFG_FCC_ETHERNET
187 187
188 #if defined(CFG_FCC_ETHERNET) 188 #if defined(CFG_FCC_ETHERNET)
189 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 189 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
190 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 190 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
191 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 191 #undef CONFIG_ETHER_NONE /* define if ether on something else */
192 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ 192 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
193 #else 193 #else
194 #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 194 #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
195 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 195 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
196 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 196 #undef CONFIG_ETHER_NONE /* define if ether on something else */
197 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ 197 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
198 #endif 198 #endif
199 199
200 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) 200 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
201 201
202 /* 202 /*
203 * - RX clk is CLK11 203 * - RX clk is CLK11
204 * - TX clk is CLK12 204 * - TX clk is CLK12
205 */ 205 */
206 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) 206 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
207 207
208 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) 208 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
209 209
210 /* 210 /*
211 * - Rx-CLK is CLK13 211 * - Rx-CLK is CLK13
212 * - Tx-CLK is CLK14 212 * - Tx-CLK is CLK14
213 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 213 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
214 * - Enable Full Duplex in FSMR 214 * - Enable Full Duplex in FSMR
215 */ 215 */
216 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 216 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
217 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 217 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
218 # define CFG_CPMFCR_RAMTYPE 0 218 # define CFG_CPMFCR_RAMTYPE 0
219 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 219 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
220 220
221 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ 221 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
222 222
223 #define CONFIG_MII /* MII PHY management */ 223 #define CONFIG_MII /* MII PHY management */
224 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 224 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
225 /* 225 /*
226 * GPIO pins used for bit-banged MII communications 226 * GPIO pins used for bit-banged MII communications
227 */ 227 */
228 #define MDIO_PORT 2 /* Port C */ 228 #define MDIO_PORT 2 /* Port C */
229 229
230 #if STK82xx_150 230 #if STK82xx_150
231 #define CFG_MDIO_PIN 0x00008000 /* PC16 */ 231 #define CFG_MDIO_PIN 0x00008000 /* PC16 */
232 #define CFG_MDC_PIN 0x00004000 /* PC17 */ 232 #define CFG_MDC_PIN 0x00004000 /* PC17 */
233 #endif 233 #endif
234 234
235 #if STK82xx_100 235 #if STK82xx_100
236 #define CFG_MDIO_PIN 0x00000002 /* PC30 */ 236 #define CFG_MDIO_PIN 0x00000002 /* PC30 */
237 #define CFG_MDC_PIN 0x00000001 /* PC31 */ 237 #define CFG_MDC_PIN 0x00000001 /* PC31 */
238 #endif 238 #endif
239 239
240 #if 1 240 #if 1
241 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) 241 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
242 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) 242 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
243 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) 243 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
244 244
245 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ 245 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
246 else iop->pdat &= ~CFG_MDIO_PIN 246 else iop->pdat &= ~CFG_MDIO_PIN
247 247
248 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ 248 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
249 else iop->pdat &= ~CFG_MDC_PIN 249 else iop->pdat &= ~CFG_MDC_PIN
250 #else 250 #else
251 #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;}) 251 #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;})
252 #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;}) 252 #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
253 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) 253 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
254 254
255 #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\ 255 #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\
256 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;} 256 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
257 257
258 #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\ 258 #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\
259 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;} 259 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
260 #endif 260 #endif
261 261
262 #define MIIDELAY udelay(1) 262 #define MIIDELAY udelay(1)
263 263
264 264
265
266 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 265 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
267 #define CONFIG_8260_CLKIN 66666666 /* in Hz */ 266 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
268 267
269 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 268 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
270 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 269 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
271 270
272 #undef CONFIG_WATCHDOG /* watchdog disabled */ 271 #undef CONFIG_WATCHDOG /* watchdog disabled */
273 272
274 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 273 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
275 274
276 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) 275 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
277 276
278 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ 277 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
279 CFG_CMD_NAND | \ 278 CFG_CMD_NAND | \
280 CFG_CMD_DHCP | \ 279 CFG_CMD_DHCP | \
281 CFG_CMD_PING | \ 280 CFG_CMD_PING | \
282 ADD_CMD_I2C | \ 281 ADD_CMD_I2C | \
283 CFG_CMD_NFS | \ 282 CFG_CMD_NFS | \
284 CFG_CMD_MII | \ 283 CFG_CMD_MII | \
285 CFG_CMD_PCI | \ 284 CFG_CMD_PCI | \
286 CFG_CMD_SNTP ) 285 CFG_CMD_SNTP )
287 286
288 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 287 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
289 #include <cmd_confdefs.h> 288 #include <cmd_confdefs.h>
290 289
291 /* 290 /*
292 * Miscellaneous configurable options 291 * Miscellaneous configurable options
293 */ 292 */
294 #define CFG_LONGHELP /* undef to save memory */ 293 #define CFG_LONGHELP /* undef to save memory */
295 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 294 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
296 295
297 #if 0 296 #if 0
298 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 297 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
299 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 298 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
300 #ifdef CFG_HUSH_PARSER 299 #ifdef CFG_HUSH_PARSER
301 #define CFG_PROMPT_HUSH_PS2 "> " 300 #define CFG_PROMPT_HUSH_PS2 "> "
302 #endif 301 #endif
303 #endif 302 #endif
304 303
305 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 304 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
306 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 305 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
307 #else 306 #else
308 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 307 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
309 #endif 308 #endif
310 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 309 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
311 #define CFG_MAXARGS 16 /* max number of command args */ 310 #define CFG_MAXARGS 16 /* max number of command args */
312 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 311 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
313 312
314 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ 313 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
315 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 314 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
316 315
317 #define CFG_LOAD_ADDR 0x300000 /* default load address */ 316 #define CFG_LOAD_ADDR 0x300000 /* default load address */
318 317
319 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ 318 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
320 319
321 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 320 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
322 321
323 #define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */ 322 #define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */
324 323
325 /* 324 /*
326 * For booting Linux, the board info and command line data 325 * For booting Linux, the board info and command line data
327 * have to be in the first 8 MB of memory, since this is 326 * have to be in the first 8 MB of memory, since this is
328 * the maximum mapped by the Linux kernel during initialization. 327 * the maximum mapped by the Linux kernel during initialization.
329 */ 328 */
330 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 329 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
331 330
332 /*----------------------------------------------------------------------- 331 /*-----------------------------------------------------------------------
333 * CAN stuff 332 * CAN stuff
334 *----------------------------------------------------------------------- 333 *-----------------------------------------------------------------------
335 */ 334 */
336 #define CFG_CAN_BASE 0x51000000 335 #define CFG_CAN_BASE 0x51000000
337 #define CFG_CAN_SIZE 1 336 #define CFG_CAN_SIZE 1
338 #define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\ 337 #define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\
339 BRx_PS_8 |\ 338 BRx_PS_8 |\
340 BRx_MS_UPMC |\ 339 BRx_MS_UPMC |\
341 BRx_V) 340 BRx_V)
342 341
343 #define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\ 342 #define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\
344 ORxU_BI) 343 ORxU_BI)
345 344
346 345
347 /* What should the base address of the main FLASH be and how big is 346 /* What should the base address of the main FLASH be and how big is
348 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk 347 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
349 * The main FLASH is whichever is connected to *CS0. 348 * The main FLASH is whichever is connected to *CS0.
350 */ 349 */
351 #define CFG_FLASH0_BASE 0x40000000 350 #define CFG_FLASH0_BASE 0x40000000
352 #define CFG_FLASH0_SIZE 32 /* 32 MB */ 351 #define CFG_FLASH0_SIZE 32 /* 32 MB */
353 352
354 /* Flash bank size (for preliminary settings) 353 /* Flash bank size (for preliminary settings)
355 */ 354 */
356 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE 355 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
357 356
358 /*----------------------------------------------------------------------- 357 /*-----------------------------------------------------------------------
359 * FLASH organization 358 * FLASH organization
360 */ 359 */
361 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ 360 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
362 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 361 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
363 362
364 #define CFG_FLASH_CFI /* flash is CFI compat. */ 363 #define CFG_FLASH_CFI /* flash is CFI compat. */
365 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 364 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
366 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ 365 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
367 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ 366 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
368 367
369 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 368 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
370 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 369 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
371 370
372 #define CFG_UPDATE_FLASH_SIZE 371 #define CFG_UPDATE_FLASH_SIZE
373 372
374 #define CFG_ENV_IS_IN_FLASH 1 373 #define CFG_ENV_IS_IN_FLASH 1
375 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) 374 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
376 #define CFG_ENV_SIZE 0x20000 375 #define CFG_ENV_SIZE 0x20000
377 #define CFG_ENV_SECT_SIZE 0x20000 376 #define CFG_ENV_SECT_SIZE 0x20000
378 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) 377 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE)
379 #define CFG_ENV_SIZE_REDUND 0x20000 378 #define CFG_ENV_SIZE_REDUND 0x20000
380 379
381 /* Where is the Hardwareinformation Block (from Monitor Sources) */ 380 /* Where is the Hardwareinformation Block (from Monitor Sources) */
382 #define MON_RES_LENGTH (0x0003FC00) 381 #define MON_RES_LENGTH (0x0003FC00)
383 #define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH) 382 #define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH)
384 #define HWIB_INFO_LEN 512 383 #define HWIB_INFO_LEN 512
385 #define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) 384 #define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
386 #define CIB_INFO_LEN 512 385 #define CIB_INFO_LEN 512
387 386
388 #define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ 387 #define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
389 #define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */ 388 #define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */
390 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 389 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
391 390
392 /*----------------------------------------------------------------------- 391 /*-----------------------------------------------------------------------
393 * NAND-FLASH stuff 392 * NAND-FLASH stuff
394 *----------------------------------------------------------------------- 393 *-----------------------------------------------------------------------
395 */ 394 */
396 #if (CONFIG_COMMANDS & CFG_CMD_NAND) 395 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
397 396
398 #define CFG_NAND_CS_DIST 0x80 397 #define CFG_NAND_CS_DIST 0x80
399 #define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 398 #define CFG_NAND_UPM_WRITE_CMD_OFS 0x20
400 #define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40 399 #define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40
401 400
402 #define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\ 401 #define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\
403 BRx_PS_8 |\ 402 BRx_PS_8 |\
404 BRx_MS_UPMB |\ 403 BRx_MS_UPMB |\
405 BRx_V) 404 BRx_V)
406 405
407 #define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\ 406 #define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\
408 ORxU_BI |\ 407 ORxU_BI |\
409 ORxU_EHTR_8IDLE) 408 ORxU_EHTR_8IDLE)
410 409
411 #define CFG_NAND_SIZE 1 410 #define CFG_NAND_SIZE 1
412 #define CFG_NAND0_BASE 0x50000000 411 #define CFG_NAND0_BASE 0x50000000
413 #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) 412 #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
414 #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) 413 #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
415 #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) 414 #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
416 415
417 #define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ 416 #define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
418 #define NAND_MAX_CHIPS 1 417 #define NAND_MAX_CHIPS 1
419 418
420 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ 419 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
421 CFG_NAND1_BASE, \ 420 CFG_NAND1_BASE, \
422 CFG_NAND2_BASE, \ 421 CFG_NAND2_BASE, \
423 CFG_NAND3_BASE, \ 422 CFG_NAND3_BASE, \
424 } 423 }
425 424
426 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) 425 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
427 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) 426 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
428 #define WRITE_NAND_UPM(d, adr, off) do \ 427 #define WRITE_NAND_UPM(d, adr, off) do \
429 { \ 428 { \
430 volatile unsigned char *addr = (unsigned char *) (adr + off); \ 429 volatile unsigned char *addr = (unsigned char *) (adr + off); \
431 WRITE_NAND(d, addr); \ 430 WRITE_NAND(d, addr); \
432 } while(0) 431 } while(0)
433 432
434 #endif /* CFG_CMD_NAND */ 433 #endif /* CFG_CMD_NAND */
435 434
436 #define CONFIG_PCI 435 #define CONFIG_PCI
437 #ifdef CONFIG_PCI 436 #ifdef CONFIG_PCI
438 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 437 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
439 #define CONFIG_PCI_PNP 438 #define CONFIG_PCI_PNP
440 #define CONFIG_EEPRO100 439 #define CONFIG_EEPRO100
441 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 440 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
442 #define CONFIG_PCI_SCAN_SHOW 441 #define CONFIG_PCI_SCAN_SHOW
443 #endif 442 #endif
444 443
445 /*----------------------------------------------------------------------- 444 /*-----------------------------------------------------------------------
446 * Hard Reset Configuration Words 445 * Hard Reset Configuration Words
447 * 446 *
448 * if you change bits in the HRCW, you must also change the CFG_* 447 * if you change bits in the HRCW, you must also change the CFG_*
449 * defines for the various registers affected by the HRCW e.g. changing 448 * defines for the various registers affected by the HRCW e.g. changing
450 * HRCW_DPPCxx requires you to also change CFG_SIUMCR. 449 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
451 */ 450 */
452 #if 0 451 #if 0
453 #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) 452 #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
454 453
455 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) 454 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
456 #else 455 #else
457 #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) 456 #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
458 #endif 457 #endif
459 458
460 /* no slaves so just fill with zeros */ 459 /* no slaves so just fill with zeros */
461 #define CFG_HRCW_SLAVE1 0 460 #define CFG_HRCW_SLAVE1 0
462 #define CFG_HRCW_SLAVE2 0 461 #define CFG_HRCW_SLAVE2 0
463 #define CFG_HRCW_SLAVE3 0 462 #define CFG_HRCW_SLAVE3 0
464 #define CFG_HRCW_SLAVE4 0 463 #define CFG_HRCW_SLAVE4 0
465 #define CFG_HRCW_SLAVE5 0 464 #define CFG_HRCW_SLAVE5 0
466 #define CFG_HRCW_SLAVE6 0 465 #define CFG_HRCW_SLAVE6 0
467 #define CFG_HRCW_SLAVE7 0 466 #define CFG_HRCW_SLAVE7 0
468 467
469 /*----------------------------------------------------------------------- 468 /*-----------------------------------------------------------------------
470 * Internal Memory Mapped Register 469 * Internal Memory Mapped Register
471 */ 470 */
472 #define CFG_IMMR 0xFFF00000 471 #define CFG_IMMR 0xFFF00000
473 472
474 /*----------------------------------------------------------------------- 473 /*-----------------------------------------------------------------------
475 * Definitions for initial stack pointer and data area (in DPRAM) 474 * Definitions for initial stack pointer and data area (in DPRAM)
476 */ 475 */
477 #define CFG_INIT_RAM_ADDR CFG_IMMR 476 #define CFG_INIT_RAM_ADDR CFG_IMMR
478 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 477 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
479 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 478 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
480 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 479 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
481 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 480 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
482 481
483 /*----------------------------------------------------------------------- 482 /*-----------------------------------------------------------------------
484 * Start addresses for the final memory configuration 483 * Start addresses for the final memory configuration
485 * (Set up by the startup code) 484 * (Set up by the startup code)
486 * Please note that CFG_SDRAM_BASE _must_ start at 0 485 * Please note that CFG_SDRAM_BASE _must_ start at 0
487 */ 486 */
488 #define CFG_SDRAM_BASE 0x00000000 487 #define CFG_SDRAM_BASE 0x00000000
489 #define CFG_FLASH_BASE CFG_FLASH0_BASE 488 #define CFG_FLASH_BASE CFG_FLASH0_BASE
490 #define CFG_MONITOR_BASE TEXT_BASE 489 #define CFG_MONITOR_BASE TEXT_BASE
491 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 490 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
492 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 491 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
493 492
494 /* 493 /*
495 * Internal Definitions 494 * Internal Definitions
496 * 495 *
497 * Boot Flags 496 * Boot Flags
498 */ 497 */
499 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 498 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
500 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 499 #define BOOTFLAG_WARM 0x02 /* Software reboot */
501 500
502
503 /*----------------------------------------------------------------------- 501 /*-----------------------------------------------------------------------
504 * Cache Configuration 502 * Cache Configuration
505 */ 503 */
506 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 504 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
507 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 505 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
508 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 506 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
509 #endif 507 #endif
510 508
511 /*----------------------------------------------------------------------- 509 /*-----------------------------------------------------------------------
512 * HIDx - Hardware Implementation-dependent Registers 2-11 510 * HIDx - Hardware Implementation-dependent Registers 2-11
513 *----------------------------------------------------------------------- 511 *-----------------------------------------------------------------------
514 * HID0 also contains cache control - initially enable both caches and 512 * HID0 also contains cache control - initially enable both caches and
515 * invalidate contents, then the final state leaves only the instruction 513 * invalidate contents, then the final state leaves only the instruction
516 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 514 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
517 * but Soft reset does not. 515 * but Soft reset does not.
518 * 516 *
519 * HID1 has only read-only information - nothing to set. 517 * HID1 has only read-only information - nothing to set.
520 */ 518 */
521 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 519 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
522 HID0_IFEM|HID0_ABE) 520 HID0_IFEM|HID0_ABE)
523 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) 521 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
524 #define CFG_HID2 0 522 #define CFG_HID2 0
525 523
526 /*----------------------------------------------------------------------- 524 /*-----------------------------------------------------------------------
527 * RMR - Reset Mode Register 5-5 525 * RMR - Reset Mode Register 5-5
528 *----------------------------------------------------------------------- 526 *-----------------------------------------------------------------------
529 * turn on Checkstop Reset Enable 527 * turn on Checkstop Reset Enable
530 */ 528 */
531 #define CFG_RMR RMR_CSRE 529 #define CFG_RMR RMR_CSRE
532 530
533 /*----------------------------------------------------------------------- 531 /*-----------------------------------------------------------------------
534 * BCR - Bus Configuration 4-25 532 * BCR - Bus Configuration 4-25
535 *----------------------------------------------------------------------- 533 *-----------------------------------------------------------------------
536 */ 534 */
537 #define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ 535 #define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
538 #define BCR_APD01 0x10000000 536 #define BCR_APD01 0x10000000
539 #define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ 537 #define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
540 538
541 /*----------------------------------------------------------------------- 539 /*-----------------------------------------------------------------------
542 * SIUMCR - SIU Module Configuration 4-31 540 * SIUMCR - SIU Module Configuration 4-31
543 *----------------------------------------------------------------------- 541 *-----------------------------------------------------------------------
544 */ 542 */
545 #if defined(CONFIG_BOARD_GET_CPU_CLK_F) 543 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
546 #define CFG_SIUMCR_LOW (SIUMCR_DPPC00) 544 #define CFG_SIUMCR_LOW (SIUMCR_DPPC00)
547 #define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) 545 #define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
548 #else 546 #else
549 #define CFG_SIUMCR (SIUMCR_DPPC00) 547 #define CFG_SIUMCR (SIUMCR_DPPC00)
550 #endif 548 #endif
551 549
552 /*----------------------------------------------------------------------- 550 /*-----------------------------------------------------------------------
553 * SYPCR - System Protection Control 4-35 551 * SYPCR - System Protection Control 4-35
554 * SYPCR can only be written once after reset! 552 * SYPCR can only be written once after reset!
555 *----------------------------------------------------------------------- 553 *-----------------------------------------------------------------------
556 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 554 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
557 */ 555 */
558 #if defined(CONFIG_WATCHDOG) 556 #if defined(CONFIG_WATCHDOG)
559 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 557 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
560 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 558 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
561 #else 559 #else
562 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 560 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
563 SYPCR_SWRI|SYPCR_SWP) 561 SYPCR_SWRI|SYPCR_SWP)
564 #endif /* CONFIG_WATCHDOG */ 562 #endif /* CONFIG_WATCHDOG */
565 563
566 /*----------------------------------------------------------------------- 564 /*-----------------------------------------------------------------------
567 * TMCNTSC - Time Counter Status and Control 4-40 565 * TMCNTSC - Time Counter Status and Control 4-40
568 *----------------------------------------------------------------------- 566 *-----------------------------------------------------------------------
569 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 567 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
570 * and enable Time Counter 568 * and enable Time Counter
571 */ 569 */
572 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 570 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
573 571
574 /*----------------------------------------------------------------------- 572 /*-----------------------------------------------------------------------
575 * PISCR - Periodic Interrupt Status and Control 4-42 573 * PISCR - Periodic Interrupt Status and Control 4-42
576 *----------------------------------------------------------------------- 574 *-----------------------------------------------------------------------
577 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 575 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
578 * Periodic timer 576 * Periodic timer
579 */ 577 */
580 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 578 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
581 579
582 /*----------------------------------------------------------------------- 580 /*-----------------------------------------------------------------------
583 * SCCR - System Clock Control 9-8 581 * SCCR - System Clock Control 9-8
584 *----------------------------------------------------------------------- 582 *-----------------------------------------------------------------------
585 * Ensure DFBRG is Divide by 16 583 * Ensure DFBRG is Divide by 16
586 */ 584 */
587 #define CFG_SCCR SCCR_DFBRG01 585 #define CFG_SCCR SCCR_DFBRG01
588 586
589 /*----------------------------------------------------------------------- 587 /*-----------------------------------------------------------------------
590 * RCCR - RISC Controller Configuration 13-7 588 * RCCR - RISC Controller Configuration 13-7
591 *----------------------------------------------------------------------- 589 *-----------------------------------------------------------------------
592 */ 590 */
593 #define CFG_RCCR 0 591 #define CFG_RCCR 0
594 592
595 /* 593 /*
596 * Init Memory Controller: 594 * Init Memory Controller:
597 * 595 *
598 * Bank Bus Machine PortSz Device 596 * Bank Bus Machine PortSz Device
599 * ---- --- ------- ------ ------ 597 * ---- --- ------- ------ ------
600 * 0 60x GPCM 32 bit FLASH 598 * 0 60x GPCM 32 bit FLASH
601 * 1 60x SDRAM 64 bit SDRAM 599 * 1 60x SDRAM 64 bit SDRAM
602 * 2 60x UPMB 8 bit NAND 600 * 2 60x UPMB 8 bit NAND
603 * 3 60x UPMC 8 bit CAN 601 * 3 60x UPMC 8 bit CAN
604 * 602 *
605 */ 603 */
606 604
607 /* Initialize SDRAM 605 /* Initialize SDRAM
608 */ 606 */
609 #undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ 607 #undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
610 608
611 #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ 609 #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
612 610
613 /* Minimum mask to separate preliminary 611 /* Minimum mask to separate preliminary
614 * address ranges for CS[0:2] 612 * address ranges for CS[0:2]
615 */ 613 */
616 #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ 614 #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
617 615
618 #define CFG_MPTPR 0x4000 616 #define CFG_MPTPR 0x4000
619 617
620 /*----------------------------------------------------------------------------- 618 /*-----------------------------------------------------------------------------
621 * Address for Mode Register Set (MRS) command 619 * Address for Mode Register Set (MRS) command
622 *----------------------------------------------------------------------------- 620 *-----------------------------------------------------------------------------
623 * In fact, the address is rather configuration data presented to the SDRAM on 621 * In fact, the address is rather configuration data presented to the SDRAM on
624 * its address lines. Because the address lines may be mux'ed externally either 622 * its address lines. Because the address lines may be mux'ed externally either
625 * for 8 column or 9 column devices, some bits appear twice in the 8260's 623 * for 8 column or 9 column devices, some bits appear twice in the 8260's
626 * address: 624 * address:
627 * 625 *
628 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | 626 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
629 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | 627 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
630 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | 628 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
631 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | 629 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
632 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | 630 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
633 *----------------------------------------------------------------------------- 631 *-----------------------------------------------------------------------------
634 */ 632 */
635 #define CFG_MRS_OFFS 0x00000110 633 #define CFG_MRS_OFFS 0x00000110
636 634
637
638 /* Bank 0 - FLASH 635 /* Bank 0 - FLASH
639 */ 636 */
640 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ 637 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
641 BRx_PS_32 |\ 638 BRx_PS_32 |\
642 BRx_MS_GPCM_P |\ 639 BRx_MS_GPCM_P |\
643 BRx_V) 640 BRx_V)
644 641
645 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ 642 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
646 ORxG_CSNT |\ 643 ORxG_CSNT |\
647 ORxG_ACS_DIV4 |\ 644 ORxG_ACS_DIV4 |\
648 ORxG_SCY_8_CLK |\ 645 ORxG_SCY_8_CLK |\
649 ORxG_TRLX) 646 ORxG_TRLX)
650 647
651 /* SDRAM on TQM8272 can have either 8 or 9 columns. 648 /* SDRAM on TQM8272 can have either 8 or 9 columns.
652 * The number affects configuration values. 649 * The number affects configuration values.
653 */ 650 */
654 651
655 /* Bank 1 - 60x bus SDRAM 652 /* Bank 1 - 60x bus SDRAM
656 */ 653 */
657 #define CFG_PSRT 0x20 /* Low Value */ 654 #define CFG_PSRT 0x20 /* Low Value */
658 /* #define CFG_PSRT 0x10 Fast Value */ 655 /* #define CFG_PSRT 0x10 Fast Value */
659 #define CFG_LSRT 0x20 /* Local Bus */ 656 #define CFG_LSRT 0x20 /* Local Bus */
660 #ifndef CFG_RAMBOOT 657 #ifndef CFG_RAMBOOT
661 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ 658 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
662 BRx_PS_64 |\ 659 BRx_PS_64 |\
663 BRx_MS_SDRAM_P |\ 660 BRx_MS_SDRAM_P |\
664 BRx_V) 661 BRx_V)
665 662
666 #define CFG_OR1_PRELIM CFG_OR1_8COL 663 #define CFG_OR1_PRELIM CFG_OR1_8COL
667 664
668 /* SDRAM initialization values for 8-column chips 665 /* SDRAM initialization values for 8-column chips
669 */ 666 */
670 #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 667 #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
671 ORxS_BPD_4 |\ 668 ORxS_BPD_4 |\
672 ORxS_ROWST_PBI1_A7 |\ 669 ORxS_ROWST_PBI1_A7 |\
673 ORxS_NUMR_12) 670 ORxS_NUMR_12)
674 671
675 #define CFG_PSDMR_8COL (PSDMR_PBI |\ 672 #define CFG_PSDMR_8COL (PSDMR_PBI |\
676 PSDMR_SDAM_A15_IS_A5 |\ 673 PSDMR_SDAM_A15_IS_A5 |\
677 PSDMR_BSMA_A12_A14 |\ 674 PSDMR_BSMA_A12_A14 |\
678 PSDMR_SDA10_PBI1_A8 |\ 675 PSDMR_SDA10_PBI1_A8 |\
679 PSDMR_RFRC_7_CLK |\ 676 PSDMR_RFRC_7_CLK |\
680 PSDMR_PRETOACT_2W |\ 677 PSDMR_PRETOACT_2W |\
681 PSDMR_ACTTORW_2W |\ 678 PSDMR_ACTTORW_2W |\
682 PSDMR_LDOTOPRE_1C |\ 679 PSDMR_LDOTOPRE_1C |\
683 PSDMR_WRC_2C |\ 680 PSDMR_WRC_2C |\
684 PSDMR_EAMUX |\ 681 PSDMR_EAMUX |\
685 PSDMR_BUFCMD |\ 682 PSDMR_BUFCMD |\
686 PSDMR_CL_2) 683 PSDMR_CL_2)
687 684
688 685
689 /* SDRAM initialization values for 9-column chips 686 /* SDRAM initialization values for 9-column chips
690 */ 687 */
691 #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 688 #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
692 ORxS_BPD_4 |\ 689 ORxS_BPD_4 |\
693 ORxS_ROWST_PBI1_A5 |\ 690 ORxS_ROWST_PBI1_A5 |\
694 ORxS_NUMR_13) 691 ORxS_NUMR_13)
695 692
696 #define CFG_PSDMR_9COL (PSDMR_PBI |\ 693 #define CFG_PSDMR_9COL (PSDMR_PBI |\
697 PSDMR_SDAM_A16_IS_A5 |\ 694 PSDMR_SDAM_A16_IS_A5 |\
698 PSDMR_BSMA_A12_A14 |\ 695 PSDMR_BSMA_A12_A14 |\
699 PSDMR_SDA10_PBI1_A7 |\ 696 PSDMR_SDA10_PBI1_A7 |\
700 PSDMR_RFRC_7_CLK |\ 697 PSDMR_RFRC_7_CLK |\
701 PSDMR_PRETOACT_2W |\ 698 PSDMR_PRETOACT_2W |\
702 PSDMR_ACTTORW_2W |\ 699 PSDMR_ACTTORW_2W |\
703 PSDMR_LDOTOPRE_1C |\ 700 PSDMR_LDOTOPRE_1C |\
704 PSDMR_WRC_2C |\ 701 PSDMR_WRC_2C |\
705 PSDMR_EAMUX |\ 702 PSDMR_EAMUX |\
706 PSDMR_BUFCMD |\ 703 PSDMR_BUFCMD |\
707 PSDMR_CL_2) 704 PSDMR_CL_2)
708 705
709 #define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 706 #define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
710 ORxS_BPD_4 |\ 707 ORxS_BPD_4 |\
711 ORxS_ROWST_PBI1_A4 |\ 708 ORxS_ROWST_PBI1_A4 |\
712 ORxS_NUMR_13) 709 ORxS_NUMR_13)
713 710
714 #define CFG_PSDMR_10COL (PSDMR_PBI |\ 711 #define CFG_PSDMR_10COL (PSDMR_PBI |\
715 PSDMR_SDAM_A17_IS_A5 |\ 712 PSDMR_SDAM_A17_IS_A5 |\
716 PSDMR_BSMA_A12_A14 |\ 713 PSDMR_BSMA_A12_A14 |\
717 PSDMR_SDA10_PBI1_A4 |\ 714 PSDMR_SDA10_PBI1_A4 |\
718 PSDMR_RFRC_6_CLK |\ 715 PSDMR_RFRC_6_CLK |\
719 PSDMR_PRETOACT_2W |\ 716 PSDMR_PRETOACT_2W |\
720 PSDMR_ACTTORW_2W |\ 717 PSDMR_ACTTORW_2W |\
721 PSDMR_LDOTOPRE_1C |\ 718 PSDMR_LDOTOPRE_1C |\
722 PSDMR_WRC_2C |\ 719 PSDMR_WRC_2C |\
723 PSDMR_EAMUX |\ 720 PSDMR_EAMUX |\
724 PSDMR_BUFCMD |\ 721 PSDMR_BUFCMD |\
725 PSDMR_CL_2) 722 PSDMR_CL_2)
726
727 723
728 #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ 724 #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
729 #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ 725 #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
730 #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ 726 #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
731 #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ 727 #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
732 #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ 728 #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
733 #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ 729 #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
734 730
735 #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ 731 #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
736 #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ 732 #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
737 #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ 733 #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
738 #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ 734 #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
739 #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ 735 #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
740 #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ 736 #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
741 737
742 #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ 738 #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
743 #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ 739 #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
744 #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ 740 #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
745 #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ 741 #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
746 #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ 742 #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
747 #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ 743 #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
748 744
749 #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ 745 #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
750 #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ 746 #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
751 #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ 747 #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
752 #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ 748 #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
753 #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ 749 #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
754 #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ 750 #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
755 751
756 #endif /* CFG_RAMBOOT */ 752 #endif /* CFG_RAMBOOT */
757 753
758 #endif /* __CONFIG_H */ 754 #endif /* __CONFIG_H */
759 755