Eric Lee / smarc-uboot

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Commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3

Authored by Wolfgang Denk
Committed by Wolfgang Denk
1 parent de8404441b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Minor code cleanup.

Showing 2 changed files with 322 additions and 328 deletions Side-by-side Diff

board/tqm8272/tqm8272.c
Diff comments   View file @ 9c0f42e
... ... @@ -12,7 +12,7 @@
12 12 *
13 13 * This program is distributed in the hope that it will be useful,
14 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 16 * GNU General Public License for more details.
17 17 *
18 18 * You should have received a copy of the GNU General Public License
... ... @@ -40,7 +40,7 @@
40 40 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
41 41 #else
42 42 #define deb_printf(fmt,arg...) \
43   - do { } while (0)
  43 + do { } while (0)
44 44 #endif
45 45  
46 46 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
47 47  
48 48  
49 49  
50 50  
51 51  
52 52  
53 53  
54 54  
55 55  
56 56  
57 57  
58 58  
59 59  
60 60  
61 61  
62 62  
63 63  
64 64  
65 65  
66 66  
67 67  
68 68  
69 69  
70 70  
71 71  
72 72  
73 73  
74 74  
75 75  
... ... @@ -58,261 +58,261 @@
58 58  
59 59 /* Port A configuration */
60 60 { /* conf ppar psor pdir podr pdat */
61   - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
62   - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
63   - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
64   - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
65   - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
66   - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
67   - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
68   - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
69   - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
70   - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
71   - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
72   - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
73   - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
74   - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
75   - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
76   - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
77   - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
78   - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
79   - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
80   - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
81   - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
82   - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
83   - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
84   - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
85   - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
86   - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
87   - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
88   - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
89   - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
90   - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
91   - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
92   - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  61 + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
  62 + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
  63 + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
  64 + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
  65 + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
  66 + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
  67 + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  68 + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  69 + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  70 + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  71 + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  72 + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  73 + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  74 + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  75 + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
  76 + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
  77 + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
  78 + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
  79 + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
  80 + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
  81 + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
  82 + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
  83 + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
  84 + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
  85 + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  86 + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
  87 + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  88 + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  89 + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  90 + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  91 + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
  92 + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
93 93 },
94 94  
95 95 /* Port B configuration */
96   - { /* conf ppar psor pdir podr pdat */
97   - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
98   - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
99   - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
100   - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
101   - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
102   - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
103   - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
104   - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
105   - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
106   - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
107   - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
108   - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
109   - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
110   - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
111   - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
112   - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
113   - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
114   - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
115   - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
116   - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
117   - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
118   - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
119   - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
120   - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
121   - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
122   - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
123   - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
124   - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
125   - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126   - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127   - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128   - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  96 + { /* conf ppar psor pdir podr pdat */
  97 + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  98 + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  99 + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  100 + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  101 + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  102 + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  103 + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  104 + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  105 + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  106 + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  107 + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  108 + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  109 + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  110 + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  111 + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
  112 + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
  113 + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
  114 + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
  115 + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
  116 + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
  117 + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
  118 + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
  119 + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
  120 + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
  121 + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
  122 + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
  123 + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
  124 + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
  125 + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  126 + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  127 + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  128 + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
129 129 },
130 130  
131 131 /* Port C */
132   - { /* conf ppar psor pdir podr pdat */
133   - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
134   - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
135   - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
136   - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
137   - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
138   - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
139   - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
140   - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
141   - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
142   - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
143   - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
144   - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
145   - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
146   - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
147   - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
148   - /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
149   - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
150   - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
151   - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
152   - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
153   - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
154   - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
155   - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
156   - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
157   - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
158   - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
159   - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
160   - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
161   - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
162   - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
163   - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
164   - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  132 + { /* conf ppar psor pdir podr pdat */
  133 + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  134 + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
  135 + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  136 + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  137 + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
  138 + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  139 + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  140 + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  141 + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  142 + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  143 + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  144 + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  145 + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
  146 + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
  147 + /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
  148 + /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
  149 + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
  150 + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  151 + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  152 + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
  153 + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
  154 + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
  155 + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
  156 + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  157 + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  158 + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  159 + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
  160 + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
  161 + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  162 + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  163 + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  164 + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
165 165 },
166 166  
167 167 /* Port D */
168   - { /* conf ppar psor pdir podr pdat */
169   - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
170   - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
171   - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
172   - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
173   - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
174   - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
175   - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
176   - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
177   - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
178   - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
179   - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
180   - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
181   - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
182   - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183   - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
184   - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  168 + { /* conf ppar psor pdir podr pdat */
  169 + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  170 + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  171 + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  172 + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
  173 + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
  174 + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  175 + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  176 + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  177 + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  178 + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  179 + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  180 + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  181 + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  182 + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  183 + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  184 + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
185 185 #if defined(CONFIG_SOFT_I2C)
186   - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
187   - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
  186 + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
  187 + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
188 188 #else
189 189 #if defined(CONFIG_HARD_I2C)
190   - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
191   - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
  190 + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  191 + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
192 192 #else /* normal I/O port pins */
193   - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
194   - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
  193 + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
  194 + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
195 195 #endif
196 196 #endif
197   - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
198   - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
199   - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
200   - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
201   - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
202   - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
203   - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
204   - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
205   - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
206   - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
207   - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
208   - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
209   - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
210   - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  197 + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  198 + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  199 + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  200 + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  201 + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  202 + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  203 + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  204 + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  205 + /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
  206 + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  207 + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  208 + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  209 + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  210 + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
211 211 }
212 212 };
213 213  
214   -#define _NOT_USED_ 0xFFFFFFFF
  214 +#define _NOT_USED_ 0xFFFFFFFF
215 215  
216 216 /* UPM pattern for bus clock = 66.7 MHz */
217 217 static const uint upmTable67[] =
218 218 {
219   - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
220   - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
221   - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
  219 + /* Offset UPM Read Single RAM array entry -> NAND Read Data */
  220 + /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
  221 + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
222 222  
223   - /* UPM Read Burst RAM array entry -> unused */
224   - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
225   - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  223 + /* UPM Read Burst RAM array entry -> unused */
  224 + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  225 + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
226 226  
227   - /* UPM Read Burst RAM array entry -> unused */
228   - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
229   - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  227 + /* UPM Read Burst RAM array entry -> unused */
  228 + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  229 + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
230 230  
231   - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
232   - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
233   - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
  231 + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
  232 + /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
  233 + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
234 234  
235   - /* UPM Write Burst RAM array entry -> unused */
236   - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
237   - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
238   - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
239   - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  235 + /* UPM Write Burst RAM array entry -> unused */
  236 + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  237 + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  238 + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  239 + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
240 240  
241   - /* UPM Refresh Timer RAM array entry -> unused */
242   - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
243   - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
244   - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  241 + /* UPM Refresh Timer RAM array entry -> unused */
  242 + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  243 + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  244 + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
245 245  
246   - /* UPM Exception RAM array entry -> unsused */
247   - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  246 + /* UPM Exception RAM array entry -> unsused */
  247 + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
248 248 };
249 249  
250 250 /* UPM pattern for bus clock = 100 MHz */
251 251 static const uint upmTable100[] =
252 252 {
253   - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
254   - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
255   - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
  253 + /* Offset UPM Read Single RAM array entry -> NAND Read Data */
  254 + /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
  255 + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
256 256  
257   - /* UPM Read Burst RAM array entry -> unused */
258   - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
259   - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  257 + /* UPM Read Burst RAM array entry -> unused */
  258 + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  259 + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
260 260  
261   - /* UPM Read Burst RAM array entry -> unused */
262   - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
263   - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  261 + /* UPM Read Burst RAM array entry -> unused */
  262 + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  263 + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
264 264  
265   - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
266   - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
267   - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
  265 + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
  266 + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
  267 + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
268 268  
269   - /* UPM Write Burst RAM array entry -> unused */
270   - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
271   - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
272   - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
273   - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  269 + /* UPM Write Burst RAM array entry -> unused */
  270 + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  271 + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  272 + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  273 + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
274 274  
275   - /* UPM Refresh Timer RAM array entry -> unused */
276   - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
277   - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
278   - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  275 + /* UPM Refresh Timer RAM array entry -> unused */
  276 + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  277 + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  278 + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
279 279  
280   - /* UPM Exception RAM array entry -> unsused */
281   - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  280 + /* UPM Exception RAM array entry -> unsused */
  281 + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
282 282 };
283 283  
284 284 /* UPM pattern for bus clock = 133.3 MHz */
285 285 static const uint upmTable133[] =
286 286 {
287   - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
288   - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
289   - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
  287 + /* Offset UPM Read Single RAM array entry -> NAND Read Data */
  288 + /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
  289 + /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
290 290  
291   - /* UPM Read Burst RAM array entry -> unused */
292   - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
293   - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  291 + /* UPM Read Burst RAM array entry -> unused */
  292 + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  293 + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
294 294  
295   - /* UPM Read Burst RAM array entry -> unused */
296   - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
297   - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  295 + /* UPM Read Burst RAM array entry -> unused */
  296 + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  297 + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
298 298  
299   - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
300   - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
301   - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
  299 + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
  300 + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
  301 + /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
302 302  
303   - /* UPM Write Burst RAM array entry -> unused */
304   - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
305   - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
306   - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
307   - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  303 + /* UPM Write Burst RAM array entry -> unused */
  304 + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  305 + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  306 + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  307 + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
308 308  
309   - /* UPM Refresh Timer RAM array entry -> unused */
310   - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
311   - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
312   - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  309 + /* UPM Refresh Timer RAM array entry -> unused */
  310 + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  311 + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  312 + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
313 313  
314   - /* UPM Exception RAM array entry -> unsused */
315   - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  314 + /* UPM Exception RAM array entry -> unsused */
  315 + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
316 316 };
317 317  
318 318 static int chipsel = 0;
319 319  
320 320  
321 321  
322 322  
323 323  
324 324  
325 325  
326 326  
327 327  
328 328  
329 329  
330 330  
331 331  
... ... @@ -320,69 +320,69 @@
320 320 /* UPM pattern for slow init */
321 321 static const uint upmTableSlow[] =
322 322 {
323   - /* Offset */ /* UPM Read Single RAM array entry */
324   - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
325   - /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
  323 + /* Offset UPM Read Single RAM array entry */
  324 + /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
  325 + /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
326 326  
327   - /* UPM Read Burst RAM array entry -> unused */
328   - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
329   - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  327 + /* UPM Read Burst RAM array entry -> unused */
  328 + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  329 + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
330 330  
331   - /* UPM Read Burst RAM array entry -> unused */
332   - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
333   - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  331 + /* UPM Read Burst RAM array entry -> unused */
  332 + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  333 + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
334 334  
335   - /* UPM Write Single RAM array entry */
336   - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
337   - /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
  335 + /* UPM Write Single RAM array entry */
  336 + /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
  337 + /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
338 338  
339   - /* UPM Write Burst RAM array entry -> unused */
340   - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
341   - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
342   - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
343   - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  339 + /* UPM Write Burst RAM array entry -> unused */
  340 + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  341 + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  342 + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  343 + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
344 344  
345   - /* UPM Refresh Timer RAM array entry -> unused */
346   - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
347   - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
348   - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  345 + /* UPM Refresh Timer RAM array entry -> unused */
  346 + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  347 + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  348 + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
349 349  
350   - /* UPM Exception RAM array entry -> unused */
351   - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  350 + /* UPM Exception RAM array entry -> unused */
  351 + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
352 352 };
353 353  
354 354 /* UPM pattern for fast init */
355 355 static const uint upmTableFast[] =
356 356 {
357   - /* Offset */ /* UPM Read Single RAM array entry */
358   - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
359   - /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
  357 + /* Offset UPM Read Single RAM array entry */
  358 + /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
  359 + /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
360 360  
361   - /* UPM Read Burst RAM array entry -> unused */
362   - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
363   - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  361 + /* UPM Read Burst RAM array entry -> unused */
  362 + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  363 + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
364 364  
365   - /* UPM Read Burst RAM array entry -> unused */
366   - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
367   - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  365 + /* UPM Read Burst RAM array entry -> unused */
  366 + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  367 + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
368 368  
369   - /* UPM Write Single RAM array entry */
370   - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
371   - /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
  369 + /* UPM Write Single RAM array entry */
  370 + /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
  371 + /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
372 372  
373   - /* UPM Write Burst RAM array entry -> unused */
374   - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
375   - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
376   - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
377   - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  373 + /* UPM Write Burst RAM array entry -> unused */
  374 + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  375 + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  376 + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  377 + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
378 378  
379   - /* UPM Refresh Timer RAM array entry -> unused */
380   - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
381   - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
382   - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  379 + /* UPM Refresh Timer RAM array entry -> unused */
  380 + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  381 + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  382 + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
383 383  
384   - /* UPM Exception RAM array entry -> unused */
385   - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  384 + /* UPM Exception RAM array entry -> unused */
  385 + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
386 386 };
387 387  
388 388  
... ... @@ -605,8 +605,7 @@
605 605 int akt = 0;
606 606  
607 607 *number = 0;
608   - while (akt < len)
609   - {
  608 + while (akt < len) {
610 609 if ((*p >= '0') && (*p <= '9')) {
611 610 *number *= 10;
612 611 *number += *p - '0';
613 612  
... ... @@ -655,14 +654,14 @@
655 654 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
656 655 printf ("serial : %s\n", s);
657 656 printf ("ethaddr: %s\n", hw->ethaddr);
658   - printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
659   - printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
660   - printf ("CPU : %d\n", hw->cpunr);
661   - printf ("CAN : %d\n", hw->can);
  657 + printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
  658 + printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
  659 + printf ("CPU : %d\n", hw->cpunr);
  660 + printf ("CAN : %d\n", hw->can);
662 661 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
663 662 else printf ("No EEprom\n");
664 663 if (hw->nand) {
665   - printf ("NAND : %x\n", hw->nand);
  664 + printf ("NAND : %x\n", hw->nand);
666 665 printf ("NAND CS: %d\n", hw->nand_cs);
667 666 } else { printf ("No NAND\n");}
668 667 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
... ... @@ -676,7 +675,7 @@
676 675 if (hw->busclk_real_ok) {
677 676 printf (" real Clk: %d\n", hw->busclk_real);
678 677 }
679   - printf ("CAS : %d\n", get_cas_latency());
  678 + printf ("CAS : %d\n", get_cas_latency());
680 679 } else {
681 680 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
682 681 }
683 682  
... ... @@ -764,16 +763,16 @@
764 763 p++;
765 764 }
766 765  
767   - if (*p == 'A') hw->can = 1;
768   - if (*p == 'B') hw->can = 2;
  766 + if (*p == 'A') hw->can = 1;
  767 + if (*p == 'B') hw->can = 2;
769 768 p +=1;
770 769 p +=1; /* connector */
771 770 if (*p != '0') {
772 771 hw->eeprom = 0x100 << (*p - 'A');
773 772 }
774 773 p++;
775   -
776   - if ((*p < '0') || (*p > '9')) {
  774 +
  775 + if ((*p < '0') || (*p > '9')) {
777 776 /* NAND before z-option */
778 777 hw->nand = 0x8000000 << (*p - 'A');
779 778 p++;
... ... @@ -913,7 +912,7 @@
913 912  
914 913 static int can_test (unsigned long off)
915 914 {
916   - volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off);
  915 + volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off);
917 916  
918 917 *(base + 0x17) = 'T';
919 918 *(base + 0x18) = 'Q';
920 919  
921 920  
... ... @@ -928,16 +927,16 @@
928 927  
929 928 static int can_config_one (unsigned long off)
930 929 {
931   - volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off);
932   - volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
933   - volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
  930 + volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off);
  931 + volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
  932 + volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
934 933 unsigned char temp;
935 934  
936   - *cpu_if = 0x45;
  935 + *cpu_if = 0x45;
937 936 temp = *ctrl;
938 937 temp |= 0x40;
939 938 *ctrl = temp;
940   - *clkout = 0x20;
  939 + *clkout = 0x20;
941 940 temp = *ctrl;
942 941 temp &= ~0x40;
943 942 *ctrl = temp;
... ... @@ -959,7 +958,7 @@
959 958  
960 959 static int init_can (void)
961 960 {
962   - volatile immap_t * immr = (immap_t *)CFG_IMMR;
  961 + volatile immap_t * immr = (immap_t *)CFG_IMMR;
963 962 volatile memctl8260_t *memctl = &immr->im_memctl;
964 963 int count = 0;
965 964  
966 965  
... ... @@ -976,10 +975,10 @@
976 975 MxMR_OP_NORM);
977 976 /* can configure */
978 977 count = can_config ();
979   - printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE);
  978 + printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE);
980 979 if (hwinf.can != count) printf("!!! difference to HWIB\n");
981 980 } else {
982   - printf ("CAN: No\n");
  981 + printf ("CAN: No\n");
983 982 }
984 983 return 0;
985 984 }
... ... @@ -999,8 +998,8 @@
999 998 }
1000 999  
1001 1000 U_BOOT_CMD(
1002   - hwib, 1, 1, do_hwib_dump,
1003   - "hwib - dump HWIB'\n",
  1001 + hwib, 1, 1, do_hwib_dump,
  1002 + "hwib - dump HWIB'\n",
1004 1003 "\n"
1005 1004 );
1006 1005  
... ... @@ -1049,7 +1048,7 @@
1049 1048 /* Update the Flash_Size and the Flash Timing */
1050 1049 int update_flash_size (int flash_size)
1051 1050 {
1052   - volatile immap_t * immr = (immap_t *)CFG_IMMR;
  1051 + volatile immap_t * immr = (immap_t *)CFG_IMMR;
1053 1052 volatile memctl8260_t *memctl = &immr->im_memctl;
1054 1053 unsigned long reg;
1055 1054 unsigned long tim;
1056 1055  
... ... @@ -1164,11 +1163,11 @@
1164 1163 int board_nand_init(struct nand_chip *nand)
1165 1164 {
1166 1165 static int UpmInit = 0;
1167   - volatile immap_t * immr = (immap_t *)CFG_IMMR;
  1166 + volatile immap_t * immr = (immap_t *)CFG_IMMR;
1168 1167 volatile memctl8260_t *memctl = &immr->im_memctl;
1169 1168  
1170 1169 if (hwinf.nand == 0) return -1;
1171   -
  1170 +
1172 1171 /* Setup the UPM */
1173 1172 if (UpmInit == 0) {
1174 1173 switch (hwinf.busclk_real) {
1175 1174  
1176 1175  
... ... @@ -1195,14 +1194,14 @@
1195 1194  
1196 1195 nand->eccmode = NAND_ECC_SOFT;
1197 1196  
1198   - nand->hwcontrol = upmnand_hwcontrol;
1199   - nand->read_byte = upmnand_read_byte;
  1197 + nand->hwcontrol = upmnand_hwcontrol;
  1198 + nand->read_byte = upmnand_read_byte;
1200 1199 nand->write_byte = upmnand_write_byte;
1201   - nand->dev_ready = tqm8272_dev_ready;
1202   -
  1200 + nand->dev_ready = tqm8272_dev_ready;
  1201 +
1203 1202 #ifndef CONFIG_NAND_SPL
1204   - nand->write_buf = tqm8272_write_buf;
1205   - nand->read_buf = tqm8272_read_buf;
  1203 + nand->write_buf = tqm8272_write_buf;
  1204 + nand->read_buf = tqm8272_read_buf;
1206 1205 nand->verify_buf = tqm8272_verify_buf;
1207 1206 #endif
1208 1207  
include/configs/TQM8272.h
Diff comments   View file @ 9c0f42e
... ... @@ -38,8 +38,8 @@
38 38 #define CONFIG_TQM8272 1
39 39  
40 40 #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
41   -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
42   -
  41 +#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
  42 +
43 43 #define STK82xx_150 1 /* on a STK82xx.150 */
44 44  
45 45 #define CONFIG_CPM2 1 /* Has a CPM2 */
46 46  
47 47  
... ... @@ -71,13 +71,13 @@
71 71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 72 ":${hostname}:${netdev}:off panic=1\0" \
73 73 "addcons=setenv bootargs ${bootargs} " \
74   - "console=$(consdev),$(baudrate)\0" \
75   - "flash_nfs=run nfsargs addip addcons;" \
  74 + "console=$(consdev),$(baudrate)\0" \
  75 + "flash_nfs=run nfsargs addip addcons;" \
76 76 "bootm ${kernel_addr}\0" \
77   - "flash_self=run ramargs addip addcons;" \
  77 + "flash_self=run ramargs addip addcons;" \
78 78 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 79 "net_nfs=tftp 300000 ${bootfile};" \
80   - "run nfsargs addip addcons;bootm\0" \
  80 + "run nfsargs addip addcons;bootm\0" \
81 81 "rootpath=/opt/eldk/ppc_82xx\0" \
82 82 "bootfile=/tftpboot/tqm8272/uImage\0" \
83 83 "kernel_addr=40080000\0" \
... ... @@ -86,7 +86,7 @@
86 86 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
87 87 "cp.b 300000 40000000 40000;" \
88 88 "setenv filesize;saveenv\0" \
89   - "cphwib=cp.b 4003fc00 33fc00 400\0" \
  89 + "cphwib=cp.b 4003fc00 33fc00 400\0" \
90 90 "upd=run load;run cphwib;run update\0" \
91 91 ""
92 92 #define CONFIG_BOOTCOMMAND "run flash_self"
... ... @@ -262,7 +262,6 @@
262 262 #define MIIDELAY udelay(1)
263 263  
264 264  
265   -
266 265 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
267 266 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
268 267  
... ... @@ -499,7 +498,6 @@
499 498 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
500 499 #define BOOTFLAG_WARM 0x02 /* Software reboot */
501 500  
502   -
503 501 /*-----------------------------------------------------------------------
504 502 * Cache Configuration
505 503 */
... ... @@ -600,7 +598,7 @@
600 598 * 0 60x GPCM 32 bit FLASH
601 599 * 1 60x SDRAM 64 bit SDRAM
602 600 * 2 60x UPMB 8 bit NAND
603   - * 3 60x UPMC 8 bit CAN
  601 + * 3 60x UPMC 8 bit CAN
604 602 *
605 603 */
606 604  
... ... @@ -634,7 +632,6 @@
634 632 */
635 633 #define CFG_MRS_OFFS 0x00000110
636 634  
637   -
638 635 /* Bank 0 - FLASH
639 636 */
640 637 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
... ... @@ -723,7 +720,6 @@
723 720 PSDMR_EAMUX |\
724 721 PSDMR_BUFCMD |\
725 722 PSDMR_CL_2)
726   -
727 723  
728 724 #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
729 725 #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */