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Commit 9c641a872aa54edc97d69281f705819e96a5c90e

Authored by Suresh Gupta
Committed by York Sun
1 parent 7af9a07403
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/usb: Workaround for erratum-A006261 

USB spec says that the minimum disconnect threshold should be
	over 525 mV. However, internal USB PHY threshold value is below
	this specified value. Due to this some devices disconnect at
	run-time. Hence, phy settings are tweaked to increased disconnect
	threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 5 changed files with 128 additions and 2 deletions Inline Diff

arch/powerpc/cpu/mpc85xx/cmd_errata.c
Diff comments   View file @ 9c641a8
1 /* 1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <command.h> 8 #include <command.h>
9 #include <linux/compiler.h> 9 #include <linux/compiler.h>
10 #include <asm/fsl_errata.h> 10 #include <asm/fsl_errata.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 #include "fsl_corenet_serdes.h" 12 #include "fsl_corenet_serdes.h"
13 13
14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
15 /* 15 /*
16 * This work-around is implemented in PBI, so just check to see if the 16 * This work-around is implemented in PBI, so just check to see if the
17 * work-around was actually applied. To do this, we check for specific data 17 * work-around was actually applied. To do this, we check for specific data
18 * at specific addresses in DCSR. 18 * at specific addresses in DCSR.
19 * 19 *
20 * Array offsets[] contains a list of offsets within DCSR. According to the 20 * Array offsets[] contains a list of offsets within DCSR. According to the
21 * erratum document, the value at each offset should be 2. 21 * erratum document, the value at each offset should be 2.
22 */ 22 */
23 static void check_erratum_a4849(uint32_t svr) 23 static void check_erratum_a4849(uint32_t svr)
24 { 24 {
25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; 25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
26 unsigned int i; 26 unsigned int i;
27 27
28 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 28 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
29 static const uint8_t offsets[] = { 29 static const uint8_t offsets[] = {
30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
31 }; 31 };
32 #endif 32 #endif
33 #ifdef CONFIG_PPC_P4080 33 #ifdef CONFIG_PPC_P4080
34 static const uint8_t offsets[] = { 34 static const uint8_t offsets[] = {
35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac 35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
36 }; 36 };
37 #endif 37 #endif
38 uint32_t x108; /* The value that should be at offset 0x108 */ 38 uint32_t x108; /* The value that should be at offset 0x108 */
39 39
40 for (i = 0; i < ARRAY_SIZE(offsets); i++) { 40 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
41 if (in_be32(dcsr + offsets[i]) != 2) { 41 if (in_be32(dcsr + offsets[i]) != 2) {
42 printf("Work-around for Erratum A004849 is not enabled\n"); 42 printf("Work-around for Erratum A004849 is not enabled\n");
43 return; 43 return;
44 } 44 }
45 } 45 }
46 46
47 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 47 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
48 x108 = 0x12; 48 x108 = 0x12;
49 #endif 49 #endif
50 50
51 #ifdef CONFIG_PPC_P4080 51 #ifdef CONFIG_PPC_P4080
52 /* 52 /*
53 * For P4080, the erratum document says that the value at offset 0x108 53 * For P4080, the erratum document says that the value at offset 0x108
54 * should be 0x12 on rev2, or 0x1c on rev3. 54 * should be 0x12 on rev2, or 0x1c on rev3.
55 */ 55 */
56 if (SVR_MAJ(svr) == 2) 56 if (SVR_MAJ(svr) == 2)
57 x108 = 0x12; 57 x108 = 0x12;
58 if (SVR_MAJ(svr) == 3) 58 if (SVR_MAJ(svr) == 3)
59 x108 = 0x1c; 59 x108 = 0x1c;
60 #endif 60 #endif
61 61
62 if (in_be32(dcsr + 0x108) != x108) { 62 if (in_be32(dcsr + 0x108) != x108) {
63 printf("Work-around for Erratum A004849 is not enabled\n"); 63 printf("Work-around for Erratum A004849 is not enabled\n");
64 return; 64 return;
65 } 65 }
66 66
67 /* Everything matches, so the erratum work-around was applied */ 67 /* Everything matches, so the erratum work-around was applied */
68 68
69 printf("Work-around for Erratum A004849 enabled\n"); 69 printf("Work-around for Erratum A004849 enabled\n");
70 } 70 }
71 #endif 71 #endif
72 72
73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
74 /* 74 /*
75 * This work-around is implemented in PBI, so just check to see if the 75 * This work-around is implemented in PBI, so just check to see if the
76 * work-around was actually applied. To do this, we check for specific data 76 * work-around was actually applied. To do this, we check for specific data
77 * at specific addresses in the SerDes register block. 77 * at specific addresses in the SerDes register block.
78 * 78 *
79 * The work-around says that for each SerDes lane, write BnTTLCRy0 = 79 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. 80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
81 81
82 */ 82 */
83 static void check_erratum_a4580(uint32_t svr) 83 static void check_erratum_a4580(uint32_t svr)
84 { 84 {
85 const serdes_corenet_t __iomem *srds_regs = 85 const serdes_corenet_t __iomem *srds_regs =
86 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 86 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
87 unsigned int lane; 87 unsigned int lane;
88 88
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
90 if (serdes_lane_enabled(lane)) { 90 if (serdes_lane_enabled(lane)) {
91 const struct serdes_lane __iomem *srds_lane = 91 const struct serdes_lane __iomem *srds_lane =
92 &srds_regs->lane[serdes_get_lane_idx(lane)]; 92 &srds_regs->lane[serdes_get_lane_idx(lane)];
93 93
94 /* 94 /*
95 * Verify that the values we were supposed to write in 95 * Verify that the values we were supposed to write in
96 * the PBI are actually there. Also, the lower 15 96 * the PBI are actually there. Also, the lower 15
97 * bits of res4[3] should be the same as the upper 15 97 * bits of res4[3] should be the same as the upper 15
98 * bits of res4[1]. 98 * bits of res4[1].
99 */ 99 */
100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || 100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
101 (in_be32(&srds_lane->res4[1]) != 0x880000) || 101 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { 102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
103 printf("Work-around for Erratum A004580 is " 103 printf("Work-around for Erratum A004580 is "
104 "not enabled\n"); 104 "not enabled\n");
105 return; 105 return;
106 } 106 }
107 } 107 }
108 } 108 }
109 109
110 /* Everything matches, so the erratum work-around was applied */ 110 /* Everything matches, so the erratum work-around was applied */
111 111
112 printf("Work-around for Erratum A004580 enabled\n"); 112 printf("Work-around for Erratum A004580 enabled\n");
113 } 113 }
114 #endif 114 #endif
115 115
116 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 116 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
117 { 117 {
118 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 118 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
119 extern int enable_cpu_a011_workaround; 119 extern int enable_cpu_a011_workaround;
120 #endif 120 #endif
121 __maybe_unused u32 svr = get_svr(); 121 __maybe_unused u32 svr = get_svr();
122 122
123 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 123 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
124 if (IS_SVR_REV(svr, 1, 0)) { 124 if (IS_SVR_REV(svr, 1, 0)) {
125 switch (SVR_SOC_VER(svr)) { 125 switch (SVR_SOC_VER(svr)) {
126 case SVR_P1013: 126 case SVR_P1013:
127 case SVR_P1022: 127 case SVR_P1022:
128 puts("Work-around for Erratum SATA A001 enabled\n"); 128 puts("Work-around for Erratum SATA A001 enabled\n");
129 } 129 }
130 } 130 }
131 #endif 131 #endif
132 132
133 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) 133 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
134 puts("Work-around for Erratum SERDES8 enabled\n"); 134 puts("Work-around for Erratum SERDES8 enabled\n");
135 #endif 135 #endif
136 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) 136 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
137 puts("Work-around for Erratum SERDES9 enabled\n"); 137 puts("Work-around for Erratum SERDES9 enabled\n");
138 #endif 138 #endif
139 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) 139 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
140 puts("Work-around for Erratum SERDES-A005 enabled\n"); 140 puts("Work-around for Erratum SERDES-A005 enabled\n");
141 #endif 141 #endif
142 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 142 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
143 if (SVR_MAJ(svr) < 3) 143 if (SVR_MAJ(svr) < 3)
144 puts("Work-around for Erratum CPU22 enabled\n"); 144 puts("Work-around for Erratum CPU22 enabled\n");
145 #endif 145 #endif
146 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 146 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
147 /* 147 /*
148 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 148 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
149 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 149 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
150 * The SVR has been checked by cpu_init_r(). 150 * The SVR has been checked by cpu_init_r().
151 */ 151 */
152 if (enable_cpu_a011_workaround) 152 if (enable_cpu_a011_workaround)
153 puts("Work-around for Erratum CPU-A011 enabled\n"); 153 puts("Work-around for Erratum CPU-A011 enabled\n");
154 #endif 154 #endif
155 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) 155 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
156 puts("Work-around for Erratum CPU-A003999 enabled\n"); 156 puts("Work-around for Erratum CPU-A003999 enabled\n");
157 #endif 157 #endif
158 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) 158 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
159 puts("Work-around for Erratum DDR-A003474 enabled\n"); 159 puts("Work-around for Erratum DDR-A003474 enabled\n");
160 #endif 160 #endif
161 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 161 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
162 puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); 162 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
163 #endif 163 #endif
164 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) 164 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
165 puts("Work-around for Erratum ESDHC111 enabled\n"); 165 puts("Work-around for Erratum ESDHC111 enabled\n");
166 #endif 166 #endif
167 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 167 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
168 puts("Work-around for Erratum A004468 enabled\n"); 168 puts("Work-around for Erratum A004468 enabled\n");
169 #endif 169 #endif
170 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) 170 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
171 puts("Work-around for Erratum ESDHC135 enabled\n"); 171 puts("Work-around for Erratum ESDHC135 enabled\n");
172 #endif 172 #endif
173 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) 173 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
174 if (SVR_MAJ(svr) < 3) 174 if (SVR_MAJ(svr) < 3)
175 puts("Work-around for Erratum ESDHC13 enabled\n"); 175 puts("Work-around for Erratum ESDHC13 enabled\n");
176 #endif 176 #endif
177 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) 177 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
178 puts("Work-around for Erratum ESDHC-A001 enabled\n"); 178 puts("Work-around for Erratum ESDHC-A001 enabled\n");
179 #endif 179 #endif
180 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 180 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
181 puts("Work-around for Erratum CPC-A002 enabled\n"); 181 puts("Work-around for Erratum CPC-A002 enabled\n");
182 #endif 182 #endif
183 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 183 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
184 puts("Work-around for Erratum CPC-A003 enabled\n"); 184 puts("Work-around for Erratum CPC-A003 enabled\n");
185 #endif 185 #endif
186 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
187 puts("Work-around for Erratum ELBC-A001 enabled\n"); 187 puts("Work-around for Erratum ELBC-A001 enabled\n");
188 #endif 188 #endif
189 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 189 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
190 puts("Work-around for Erratum DDR-A003 enabled\n"); 190 puts("Work-around for Erratum DDR-A003 enabled\n");
191 #endif 191 #endif
192 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 192 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
193 puts("Work-around for Erratum DDR115 enabled\n"); 193 puts("Work-around for Erratum DDR115 enabled\n");
194 #endif 194 #endif
195 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 195 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
196 puts("Work-around for Erratum DDR111 enabled\n"); 196 puts("Work-around for Erratum DDR111 enabled\n");
197 puts("Work-around for Erratum DDR134 enabled\n"); 197 puts("Work-around for Erratum DDR134 enabled\n");
198 #endif 198 #endif
199 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 199 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
200 puts("Work-around for Erratum IFC-A002769 enabled\n"); 200 puts("Work-around for Erratum IFC-A002769 enabled\n");
201 #endif 201 #endif
202 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 202 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
203 puts("Work-around for Erratum P1010-A003549 enabled\n"); 203 puts("Work-around for Erratum P1010-A003549 enabled\n");
204 #endif 204 #endif
205 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 205 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
206 puts("Work-around for Erratum IFC A-003399 enabled\n"); 206 puts("Work-around for Erratum IFC A-003399 enabled\n");
207 #endif 207 #endif
208 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 208 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
209 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 209 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
210 puts("Work-around for Erratum NMG DDR120 enabled\n"); 210 puts("Work-around for Erratum NMG DDR120 enabled\n");
211 #endif 211 #endif
212 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 212 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
213 puts("Work-around for Erratum NMG_LBC103 enabled\n"); 213 puts("Work-around for Erratum NMG_LBC103 enabled\n");
214 #endif 214 #endif
215 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 215 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
216 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 216 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
217 puts("Work-around for Erratum NMG ETSEC129 enabled\n"); 217 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
218 #endif 218 #endif
219 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 219 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
220 puts("Work-around for Erratum A004510 enabled\n"); 220 puts("Work-around for Erratum A004510 enabled\n");
221 #endif 221 #endif
222 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 222 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
223 puts("Work-around for Erratum SRIO-A004034 enabled\n"); 223 puts("Work-around for Erratum SRIO-A004034 enabled\n");
224 #endif 224 #endif
225 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
226 puts("Work-around for Erratum A004934 enabled\n"); 226 puts("Work-around for Erratum A004934 enabled\n");
227 #endif 227 #endif
228 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 228 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
229 if (IS_SVR_REV(svr, 1, 0)) 229 if (IS_SVR_REV(svr, 1, 0))
230 puts("Work-around for Erratum A005871 enabled\n"); 230 puts("Work-around for Erratum A005871 enabled\n");
231 #endif 231 #endif
232 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475 232 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475
233 if (SVR_MAJ(get_svr()) == 1) 233 if (SVR_MAJ(get_svr()) == 1)
234 puts("Work-around for Erratum A006475 enabled\n"); 234 puts("Work-around for Erratum A006475 enabled\n");
235 #endif 235 #endif
236 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384 236 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384
237 if (SVR_MAJ(get_svr()) == 1) 237 if (SVR_MAJ(get_svr()) == 1)
238 puts("Work-around for Erratum A006384 enabled\n"); 238 puts("Work-around for Erratum A006384 enabled\n");
239 #endif 239 #endif
240 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 240 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
241 /* This work-around is implemented in PBI, so just check for it */ 241 /* This work-around is implemented in PBI, so just check for it */
242 check_erratum_a4849(svr); 242 check_erratum_a4849(svr);
243 #endif 243 #endif
244 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 244 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
245 /* This work-around is implemented in PBI, so just check for it */ 245 /* This work-around is implemented in PBI, so just check for it */
246 check_erratum_a4580(svr); 246 check_erratum_a4580(svr);
247 #endif 247 #endif
248 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 248 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
249 puts("Work-around for Erratum PCIe-A003 enabled\n"); 249 puts("Work-around for Erratum PCIe-A003 enabled\n");
250 #endif 250 #endif
251 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 251 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
252 puts("Work-around for Erratum USB14 enabled\n"); 252 puts("Work-around for Erratum USB14 enabled\n");
253 #endif 253 #endif
254 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 254 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
255 puts("Work-around for Erratum A006593 enabled\n"); 255 puts("Work-around for Erratum A006593 enabled\n");
256 #endif 256 #endif
257 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 257 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
258 if (has_erratum_a006379()) 258 if (has_erratum_a006379())
259 puts("Work-around for Erratum A006379 enabled\n"); 259 puts("Work-around for Erratum A006379 enabled\n");
260 #endif 260 #endif
261 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 261 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
262 if (IS_SVR_REV(svr, 1, 0)) 262 if (IS_SVR_REV(svr, 1, 0))
263 puts("Work-around for Erratum A003571 enabled\n"); 263 puts("Work-around for Erratum A003571 enabled\n");
264 #endif 264 #endif
265 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 265 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
266 puts("Work-around for Erratum A-005812 enabled\n"); 266 puts("Work-around for Erratum A-005812 enabled\n");
267 #endif 267 #endif
268 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125 268 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
269 puts("Work-around for Erratum A005125 enabled\n"); 269 puts("Work-around for Erratum A005125 enabled\n");
270 #endif 270 #endif
271 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 271 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
272 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || 272 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
273 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) 273 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
274 puts("Work-around for Erratum I2C-A004447 enabled\n"); 274 puts("Work-around for Erratum I2C-A004447 enabled\n");
275 #endif 275 #endif
276 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
277 if (has_erratum_a006261())
278 puts("Work-around for Erratum A006261 enabled\n");
279 #endif
276 return 0; 280 return 0;
277 } 281 }
278 282
279 U_BOOT_CMD( 283 U_BOOT_CMD(
280 errata, 1, 0, do_errata, 284 errata, 1, 0, do_errata,
281 "Report errata workarounds", 285 "Report errata workarounds",
282 "" 286 ""
283 ); 287 );
284 288
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 9c641a8
1 /* 1 /*
2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * (C) Copyright 2003 Motorola Inc. 4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 * 6 *
7 * (C) Copyright 2000 7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <watchdog.h> 14 #include <watchdog.h>
15 #include <asm/processor.h> 15 #include <asm/processor.h>
16 #include <ioports.h> 16 #include <ioports.h>
17 #include <sata.h> 17 #include <sata.h>
18 #include <fm_eth.h> 18 #include <fm_eth.h>
19 #include <asm/io.h> 19 #include <asm/io.h>
20 #include <asm/cache.h> 20 #include <asm/cache.h>
21 #include <asm/mmu.h> 21 #include <asm/mmu.h>
22 #include <asm/fsl_errata.h> 22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h> 23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h> 25 #include <asm/fsl_srio.h>
26 #include <fsl_usb.h> 26 #include <fsl_usb.h>
27 #include <hwconfig.h> 27 #include <hwconfig.h>
28 #include <linux/compiler.h> 28 #include <linux/compiler.h>
29 #include "mp.h" 29 #include "mp.h"
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
31 #include <nand.h> 31 #include <nand.h>
32 #include <errno.h> 32 #include <errno.h>
33 #endif 33 #endif
34 34
35 #include "../../../../drivers/block/fsl_sata.h" 35 #include "../../../../drivers/block/fsl_sata.h"
36 36
37 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
38 38
39 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
40 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
41 {
42 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
43 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
44
45 /* Increase Disconnect Threshold by 50mV */
46 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
47 INC_DCNT_THRESHOLD_50MV;
48 /* Enable programming of USB High speed Disconnect threshold */
49 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
50 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
51
52 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
53 /* Increase Disconnect Threshold by 50mV */
54 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
55 INC_DCNT_THRESHOLD_50MV;
56 /* Enable programming of USB High speed Disconnect threshold */
57 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
58 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
59 #else
60
61 u32 temp = 0;
62 u32 status = in_be32(&usb_phy->status1);
63
64 u32 squelch_prog_rd_0_2 =
65 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
66 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
67
68 u32 squelch_prog_rd_3_5 =
69 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
70 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
71
72 setbits_be32(&usb_phy->config1,
73 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
74 setbits_be32(&usb_phy->config2,
75 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
76
77 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
78 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
79
80 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
82 #endif
83 }
84 #endif
85
86
39 #ifdef CONFIG_QE 87 #ifdef CONFIG_QE
40 extern qe_iop_conf_t qe_iop_conf_tab[]; 88 extern qe_iop_conf_t qe_iop_conf_tab[];
41 extern void qe_config_iopin(u8 port, u8 pin, int dir, 89 extern void qe_config_iopin(u8 port, u8 pin, int dir,
42 int open_drain, int assign); 90 int open_drain, int assign);
43 extern void qe_init(uint qe_base); 91 extern void qe_init(uint qe_base);
44 extern void qe_reset(void); 92 extern void qe_reset(void);
45 93
46 static void config_qe_ioports(void) 94 static void config_qe_ioports(void)
47 { 95 {
48 u8 port, pin; 96 u8 port, pin;
49 int dir, open_drain, assign; 97 int dir, open_drain, assign;
50 int i; 98 int i;
51 99
52 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 100 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
53 port = qe_iop_conf_tab[i].port; 101 port = qe_iop_conf_tab[i].port;
54 pin = qe_iop_conf_tab[i].pin; 102 pin = qe_iop_conf_tab[i].pin;
55 dir = qe_iop_conf_tab[i].dir; 103 dir = qe_iop_conf_tab[i].dir;
56 open_drain = qe_iop_conf_tab[i].open_drain; 104 open_drain = qe_iop_conf_tab[i].open_drain;
57 assign = qe_iop_conf_tab[i].assign; 105 assign = qe_iop_conf_tab[i].assign;
58 qe_config_iopin(port, pin, dir, open_drain, assign); 106 qe_config_iopin(port, pin, dir, open_drain, assign);
59 } 107 }
60 } 108 }
61 #endif 109 #endif
62 110
63 #ifdef CONFIG_CPM2 111 #ifdef CONFIG_CPM2
64 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 112 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
65 { 113 {
66 int portnum; 114 int portnum;
67 115
68 for (portnum = 0; portnum < 4; portnum++) { 116 for (portnum = 0; portnum < 4; portnum++) {
69 uint pmsk = 0, 117 uint pmsk = 0,
70 ppar = 0, 118 ppar = 0,
71 psor = 0, 119 psor = 0,
72 pdir = 0, 120 pdir = 0,
73 podr = 0, 121 podr = 0,
74 pdat = 0; 122 pdat = 0;
75 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 123 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
76 iop_conf_t *eiopc = iopc + 32; 124 iop_conf_t *eiopc = iopc + 32;
77 uint msk = 1; 125 uint msk = 1;
78 126
79 /* 127 /*
80 * NOTE: 128 * NOTE:
81 * index 0 refers to pin 31, 129 * index 0 refers to pin 31,
82 * index 31 refers to pin 0 130 * index 31 refers to pin 0
83 */ 131 */
84 while (iopc < eiopc) { 132 while (iopc < eiopc) {
85 if (iopc->conf) { 133 if (iopc->conf) {
86 pmsk |= msk; 134 pmsk |= msk;
87 if (iopc->ppar) 135 if (iopc->ppar)
88 ppar |= msk; 136 ppar |= msk;
89 if (iopc->psor) 137 if (iopc->psor)
90 psor |= msk; 138 psor |= msk;
91 if (iopc->pdir) 139 if (iopc->pdir)
92 pdir |= msk; 140 pdir |= msk;
93 if (iopc->podr) 141 if (iopc->podr)
94 podr |= msk; 142 podr |= msk;
95 if (iopc->pdat) 143 if (iopc->pdat)
96 pdat |= msk; 144 pdat |= msk;
97 } 145 }
98 146
99 msk <<= 1; 147 msk <<= 1;
100 iopc++; 148 iopc++;
101 } 149 }
102 150
103 if (pmsk != 0) { 151 if (pmsk != 0) {
104 volatile ioport_t *iop = ioport_addr (cpm, portnum); 152 volatile ioport_t *iop = ioport_addr (cpm, portnum);
105 uint tpmsk = ~pmsk; 153 uint tpmsk = ~pmsk;
106 154
107 /* 155 /*
108 * the (somewhat confused) paragraph at the 156 * the (somewhat confused) paragraph at the
109 * bottom of page 35-5 warns that there might 157 * bottom of page 35-5 warns that there might
110 * be "unknown behaviour" when programming 158 * be "unknown behaviour" when programming
111 * PSORx and PDIRx, if PPARx = 1, so I 159 * PSORx and PDIRx, if PPARx = 1, so I
112 * decided this meant I had to disable the 160 * decided this meant I had to disable the
113 * dedicated function first, and enable it 161 * dedicated function first, and enable it
114 * last. 162 * last.
115 */ 163 */
116 iop->ppar &= tpmsk; 164 iop->ppar &= tpmsk;
117 iop->psor = (iop->psor & tpmsk) | psor; 165 iop->psor = (iop->psor & tpmsk) | psor;
118 iop->podr = (iop->podr & tpmsk) | podr; 166 iop->podr = (iop->podr & tpmsk) | podr;
119 iop->pdat = (iop->pdat & tpmsk) | pdat; 167 iop->pdat = (iop->pdat & tpmsk) | pdat;
120 iop->pdir = (iop->pdir & tpmsk) | pdir; 168 iop->pdir = (iop->pdir & tpmsk) | pdir;
121 iop->ppar |= ppar; 169 iop->ppar |= ppar;
122 } 170 }
123 } 171 }
124 } 172 }
125 #endif 173 #endif
126 174
127 #ifdef CONFIG_SYS_FSL_CPC 175 #ifdef CONFIG_SYS_FSL_CPC
128 static void enable_cpc(void) 176 static void enable_cpc(void)
129 { 177 {
130 int i; 178 int i;
131 u32 size = 0; 179 u32 size = 0;
132 180
133 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 181 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
134 182
135 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 183 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
136 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 184 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
137 size += CPC_CFG0_SZ_K(cpccfg0); 185 size += CPC_CFG0_SZ_K(cpccfg0);
138 #ifdef CONFIG_RAMBOOT_PBL 186 #ifdef CONFIG_RAMBOOT_PBL
139 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
140 /* find and disable LAW of SRAM */ 188 /* find and disable LAW of SRAM */
141 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
142 190
143 if (law.index == -1) { 191 if (law.index == -1) {
144 printf("\nFatal error happened\n"); 192 printf("\nFatal error happened\n");
145 return; 193 return;
146 } 194 }
147 disable_law(law.index); 195 disable_law(law.index);
148 196
149 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
150 out_be32(&cpc->cpccsr0, 0); 198 out_be32(&cpc->cpccsr0, 0);
151 out_be32(&cpc->cpcsrcr0, 0); 199 out_be32(&cpc->cpcsrcr0, 0);
152 } 200 }
153 #endif 201 #endif
154 202
155 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 203 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
156 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 204 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
157 #endif 205 #endif
158 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 206 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
159 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 207 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
160 #endif 208 #endif
161 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 209 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
162 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 210 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
163 #endif 211 #endif
164 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 212 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
165 if (has_erratum_a006379()) { 213 if (has_erratum_a006379()) {
166 setbits_be32(&cpc->cpchdbcr0, 214 setbits_be32(&cpc->cpchdbcr0,
167 CPC_HDBCR0_SPLRU_LEVEL_EN); 215 CPC_HDBCR0_SPLRU_LEVEL_EN);
168 } 216 }
169 #endif 217 #endif
170 218
171 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 219 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
172 /* Read back to sync write */ 220 /* Read back to sync write */
173 in_be32(&cpc->cpccsr0); 221 in_be32(&cpc->cpccsr0);
174 222
175 } 223 }
176 224
177 puts("Corenet Platform Cache: "); 225 puts("Corenet Platform Cache: ");
178 print_size(size * 1024, " enabled\n"); 226 print_size(size * 1024, " enabled\n");
179 } 227 }
180 228
181 static void invalidate_cpc(void) 229 static void invalidate_cpc(void)
182 { 230 {
183 int i; 231 int i;
184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 232 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
185 233
186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 234 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
187 /* skip CPC when it used as all SRAM */ 235 /* skip CPC when it used as all SRAM */
188 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 236 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
189 continue; 237 continue;
190 /* Flash invalidate the CPC and clear all the locks */ 238 /* Flash invalidate the CPC and clear all the locks */
191 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 239 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
192 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 240 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
193 ; 241 ;
194 } 242 }
195 } 243 }
196 #else 244 #else
197 #define enable_cpc() 245 #define enable_cpc()
198 #define invalidate_cpc() 246 #define invalidate_cpc()
199 #endif /* CONFIG_SYS_FSL_CPC */ 247 #endif /* CONFIG_SYS_FSL_CPC */
200 248
201 /* 249 /*
202 * Breathe some life into the CPU... 250 * Breathe some life into the CPU...
203 * 251 *
204 * Set up the memory map 252 * Set up the memory map
205 * initialize a bunch of registers 253 * initialize a bunch of registers
206 */ 254 */
207 255
208 #ifdef CONFIG_FSL_CORENET 256 #ifdef CONFIG_FSL_CORENET
209 static void corenet_tb_init(void) 257 static void corenet_tb_init(void)
210 { 258 {
211 volatile ccsr_rcpm_t *rcpm = 259 volatile ccsr_rcpm_t *rcpm =
212 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 260 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
213 volatile ccsr_pic_t *pic = 261 volatile ccsr_pic_t *pic =
214 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 262 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
215 u32 whoami = in_be32(&pic->whoami); 263 u32 whoami = in_be32(&pic->whoami);
216 264
217 /* Enable the timebase register for this core */ 265 /* Enable the timebase register for this core */
218 out_be32(&rcpm->ctbenrl, (1 << whoami)); 266 out_be32(&rcpm->ctbenrl, (1 << whoami));
219 } 267 }
220 #endif 268 #endif
221 269
222 void cpu_init_f (void) 270 void cpu_init_f (void)
223 { 271 {
224 extern void m8560_cpm_reset (void); 272 extern void m8560_cpm_reset (void);
225 #ifdef CONFIG_SYS_DCSRBAR_PHYS 273 #ifdef CONFIG_SYS_DCSRBAR_PHYS
226 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 274 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
227 #endif 275 #endif
228 #if defined(CONFIG_SECURE_BOOT) 276 #if defined(CONFIG_SECURE_BOOT)
229 struct law_entry law; 277 struct law_entry law;
230 #endif 278 #endif
231 #ifdef CONFIG_MPC8548 279 #ifdef CONFIG_MPC8548
232 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 280 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
233 uint svr = get_svr(); 281 uint svr = get_svr();
234 282
235 /* 283 /*
236 * CPU2 errata workaround: A core hang possible while executing 284 * CPU2 errata workaround: A core hang possible while executing
237 * a msync instruction and a snoopable transaction from an I/O 285 * a msync instruction and a snoopable transaction from an I/O
238 * master tagged to make quick forward progress is present. 286 * master tagged to make quick forward progress is present.
239 * Fixed in silicon rev 2.1. 287 * Fixed in silicon rev 2.1.
240 */ 288 */
241 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 289 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
242 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 290 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
243 #endif 291 #endif
244 292
245 disable_tlb(14); 293 disable_tlb(14);
246 disable_tlb(15); 294 disable_tlb(15);
247 295
248 #if defined(CONFIG_SECURE_BOOT) 296 #if defined(CONFIG_SECURE_BOOT)
249 /* Disable the LAW created for NOR flash by the PBI commands */ 297 /* Disable the LAW created for NOR flash by the PBI commands */
250 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 298 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
251 if (law.index != -1) 299 if (law.index != -1)
252 disable_law(law.index); 300 disable_law(law.index);
253 #endif 301 #endif
254 302
255 #ifdef CONFIG_CPM2 303 #ifdef CONFIG_CPM2
256 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 304 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
257 #endif 305 #endif
258 306
259 init_early_memctl_regs(); 307 init_early_memctl_regs();
260 308
261 #if defined(CONFIG_CPM2) 309 #if defined(CONFIG_CPM2)
262 m8560_cpm_reset(); 310 m8560_cpm_reset();
263 #endif 311 #endif
264 #ifdef CONFIG_QE 312 #ifdef CONFIG_QE
265 /* Config QE ioports */ 313 /* Config QE ioports */
266 config_qe_ioports(); 314 config_qe_ioports();
267 #endif 315 #endif
268 #if defined(CONFIG_FSL_DMA) 316 #if defined(CONFIG_FSL_DMA)
269 dma_init(); 317 dma_init();
270 #endif 318 #endif
271 #ifdef CONFIG_FSL_CORENET 319 #ifdef CONFIG_FSL_CORENET
272 corenet_tb_init(); 320 corenet_tb_init();
273 #endif 321 #endif
274 init_used_tlb_cams(); 322 init_used_tlb_cams();
275 323
276 /* Invalidate the CPC before DDR gets enabled */ 324 /* Invalidate the CPC before DDR gets enabled */
277 invalidate_cpc(); 325 invalidate_cpc();
278 326
279 #ifdef CONFIG_SYS_DCSRBAR_PHYS 327 #ifdef CONFIG_SYS_DCSRBAR_PHYS
280 /* set DCSRCR so that DCSR space is 1G */ 328 /* set DCSRCR so that DCSR space is 1G */
281 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 329 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
282 in_be32(&gur->dcsrcr); 330 in_be32(&gur->dcsrcr);
283 #endif 331 #endif
284 332
285 } 333 }
286 334
287 /* Implement a dummy function for those platforms w/o SERDES */ 335 /* Implement a dummy function for those platforms w/o SERDES */
288 static void __fsl_serdes__init(void) 336 static void __fsl_serdes__init(void)
289 { 337 {
290 return ; 338 return ;
291 } 339 }
292 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 340 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
293 341
294 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 342 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
295 int enable_cluster_l2(void) 343 int enable_cluster_l2(void)
296 { 344 {
297 int i = 0; 345 int i = 0;
298 u32 cluster; 346 u32 cluster;
299 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 347 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
300 struct ccsr_cluster_l2 __iomem *l2cache; 348 struct ccsr_cluster_l2 __iomem *l2cache;
301 349
302 cluster = in_be32(&gur->tp_cluster[i].lower); 350 cluster = in_be32(&gur->tp_cluster[i].lower);
303 if (cluster & TP_CLUSTER_EOC) 351 if (cluster & TP_CLUSTER_EOC)
304 return 0; 352 return 0;
305 353
306 /* The first cache has already been set up, so skip it */ 354 /* The first cache has already been set up, so skip it */
307 i++; 355 i++;
308 356
309 /* Look through the remaining clusters, and set up their caches */ 357 /* Look through the remaining clusters, and set up their caches */
310 do { 358 do {
311 int j, cluster_valid = 0; 359 int j, cluster_valid = 0;
312 360
313 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 361 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
314 362
315 cluster = in_be32(&gur->tp_cluster[i].lower); 363 cluster = in_be32(&gur->tp_cluster[i].lower);
316 364
317 /* check that at least one core/accel is enabled in cluster */ 365 /* check that at least one core/accel is enabled in cluster */
318 for (j = 0; j < 4; j++) { 366 for (j = 0; j < 4; j++) {
319 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 367 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
320 u32 type = in_be32(&gur->tp_ityp[idx]); 368 u32 type = in_be32(&gur->tp_ityp[idx]);
321 369
322 if (type & TP_ITYP_AV) 370 if (type & TP_ITYP_AV)
323 cluster_valid = 1; 371 cluster_valid = 1;
324 } 372 }
325 373
326 if (cluster_valid) { 374 if (cluster_valid) {
327 /* set stash ID to (cluster) * 2 + 32 + 1 */ 375 /* set stash ID to (cluster) * 2 + 32 + 1 */
328 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 376 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
329 377
330 printf("enable l2 for cluster %d %p\n", i, l2cache); 378 printf("enable l2 for cluster %d %p\n", i, l2cache);
331 379
332 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 380 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
333 while ((in_be32(&l2cache->l2csr0) 381 while ((in_be32(&l2cache->l2csr0)
334 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 382 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
335 ; 383 ;
336 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 384 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
337 } 385 }
338 i++; 386 i++;
339 } while (!(cluster & TP_CLUSTER_EOC)); 387 } while (!(cluster & TP_CLUSTER_EOC));
340 388
341 return 0; 389 return 0;
342 } 390 }
343 #endif 391 #endif
344 392
345 /* 393 /*
346 * Initialize L2 as cache. 394 * Initialize L2 as cache.
347 * 395 *
348 * The newer 8548, etc, parts have twice as much cache, but 396 * The newer 8548, etc, parts have twice as much cache, but
349 * use the same bit-encoding as the older 8555, etc, parts. 397 * use the same bit-encoding as the older 8555, etc, parts.
350 * 398 *
351 */ 399 */
352 int cpu_init_r(void) 400 int cpu_init_r(void)
353 { 401 {
354 __maybe_unused u32 svr = get_svr(); 402 __maybe_unused u32 svr = get_svr();
355 #ifdef CONFIG_SYS_LBC_LCRR 403 #ifdef CONFIG_SYS_LBC_LCRR
356 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 404 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
357 #endif 405 #endif
358 #ifdef CONFIG_L2_CACHE 406 #ifdef CONFIG_L2_CACHE
359 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 407 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
360 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 408 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
361 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 409 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
362 #endif 410 #endif
363 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 411 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
364 extern int spin_table_compat; 412 extern int spin_table_compat;
365 const char *spin; 413 const char *spin;
366 #endif 414 #endif
367 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 415 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
368 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 416 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
369 #endif 417 #endif
370 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 418 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
371 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 419 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
372 /* 420 /*
373 * CPU22 and NMG_CPU_A011 share the same workaround. 421 * CPU22 and NMG_CPU_A011 share the same workaround.
374 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 422 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
375 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 423 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
376 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 424 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
377 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 425 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
378 * be disabled by hwconfig with syntax: 426 * be disabled by hwconfig with syntax:
379 * 427 *
380 * fsl_cpu_a011:disable 428 * fsl_cpu_a011:disable
381 */ 429 */
382 extern int enable_cpu_a011_workaround; 430 extern int enable_cpu_a011_workaround;
383 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 431 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
384 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 432 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
385 #else 433 #else
386 char buffer[HWCONFIG_BUFFER_SIZE]; 434 char buffer[HWCONFIG_BUFFER_SIZE];
387 char *buf = NULL; 435 char *buf = NULL;
388 int n, res; 436 int n, res;
389 437
390 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 438 n = getenv_f("hwconfig", buffer, sizeof(buffer));
391 if (n > 0) 439 if (n > 0)
392 buf = buffer; 440 buf = buffer;
393 441
394 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 442 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
395 if (res > 0) 443 if (res > 0)
396 enable_cpu_a011_workaround = 0; 444 enable_cpu_a011_workaround = 0;
397 else { 445 else {
398 if (n >= HWCONFIG_BUFFER_SIZE) { 446 if (n >= HWCONFIG_BUFFER_SIZE) {
399 printf("fsl_cpu_a011 was not found. hwconfig variable " 447 printf("fsl_cpu_a011 was not found. hwconfig variable "
400 "may be too long\n"); 448 "may be too long\n");
401 } 449 }
402 enable_cpu_a011_workaround = 450 enable_cpu_a011_workaround =
403 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 451 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
404 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 452 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
405 } 453 }
406 #endif 454 #endif
407 if (enable_cpu_a011_workaround) { 455 if (enable_cpu_a011_workaround) {
408 flush_dcache(); 456 flush_dcache();
409 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 457 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
410 sync(); 458 sync();
411 } 459 }
412 #endif 460 #endif
413 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 461 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
414 /* 462 /*
415 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 463 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
416 * in write shadow mode. Checking DCWS before setting SPR 976. 464 * in write shadow mode. Checking DCWS before setting SPR 976.
417 */ 465 */
418 if (mfspr(L1CSR2) & L1CSR2_DCWS) 466 if (mfspr(L1CSR2) & L1CSR2_DCWS)
419 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 467 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
420 #endif 468 #endif
421 469
422 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 470 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
423 spin = getenv("spin_table_compat"); 471 spin = getenv("spin_table_compat");
424 if (spin && (*spin == 'n')) 472 if (spin && (*spin == 'n'))
425 spin_table_compat = 0; 473 spin_table_compat = 0;
426 else 474 else
427 spin_table_compat = 1; 475 spin_table_compat = 1;
428 #endif 476 #endif
429 477
430 puts ("L2: "); 478 puts ("L2: ");
431 479
432 #if defined(CONFIG_L2_CACHE) 480 #if defined(CONFIG_L2_CACHE)
433 volatile uint cache_ctl; 481 volatile uint cache_ctl;
434 uint ver; 482 uint ver;
435 u32 l2siz_field; 483 u32 l2siz_field;
436 484
437 ver = SVR_SOC_VER(svr); 485 ver = SVR_SOC_VER(svr);
438 486
439 asm("msync;isync"); 487 asm("msync;isync");
440 cache_ctl = l2cache->l2ctl; 488 cache_ctl = l2cache->l2ctl;
441 489
442 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 490 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
443 if (cache_ctl & MPC85xx_L2CTL_L2E) { 491 if (cache_ctl & MPC85xx_L2CTL_L2E) {
444 /* Clear L2 SRAM memory-mapped base address */ 492 /* Clear L2 SRAM memory-mapped base address */
445 out_be32(&l2cache->l2srbar0, 0x0); 493 out_be32(&l2cache->l2srbar0, 0x0);
446 out_be32(&l2cache->l2srbar1, 0x0); 494 out_be32(&l2cache->l2srbar1, 0x0);
447 495
448 /* set MBECCDIS=0, SBECCDIS=0 */ 496 /* set MBECCDIS=0, SBECCDIS=0 */
449 clrbits_be32(&l2cache->l2errdis, 497 clrbits_be32(&l2cache->l2errdis,
450 (MPC85xx_L2ERRDIS_MBECC | 498 (MPC85xx_L2ERRDIS_MBECC |
451 MPC85xx_L2ERRDIS_SBECC)); 499 MPC85xx_L2ERRDIS_SBECC));
452 500
453 /* set L2E=0, L2SRAM=0 */ 501 /* set L2E=0, L2SRAM=0 */
454 clrbits_be32(&l2cache->l2ctl, 502 clrbits_be32(&l2cache->l2ctl,
455 (MPC85xx_L2CTL_L2E | 503 (MPC85xx_L2CTL_L2E |
456 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 504 MPC85xx_L2CTL_L2SRAM_ENTIRE));
457 } 505 }
458 #endif 506 #endif
459 507
460 l2siz_field = (cache_ctl >> 28) & 0x3; 508 l2siz_field = (cache_ctl >> 28) & 0x3;
461 509
462 switch (l2siz_field) { 510 switch (l2siz_field) {
463 case 0x0: 511 case 0x0:
464 printf(" unknown size (0x%08x)\n", cache_ctl); 512 printf(" unknown size (0x%08x)\n", cache_ctl);
465 return -1; 513 return -1;
466 break; 514 break;
467 case 0x1: 515 case 0x1:
468 if (ver == SVR_8540 || ver == SVR_8560 || 516 if (ver == SVR_8540 || ver == SVR_8560 ||
469 ver == SVR_8541 || ver == SVR_8555) { 517 ver == SVR_8541 || ver == SVR_8555) {
470 puts("128 KiB "); 518 puts("128 KiB ");
471 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 519 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
472 cache_ctl = 0xc4000000; 520 cache_ctl = 0xc4000000;
473 } else { 521 } else {
474 puts("256 KiB "); 522 puts("256 KiB ");
475 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 523 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
476 } 524 }
477 break; 525 break;
478 case 0x2: 526 case 0x2:
479 if (ver == SVR_8540 || ver == SVR_8560 || 527 if (ver == SVR_8540 || ver == SVR_8560 ||
480 ver == SVR_8541 || ver == SVR_8555) { 528 ver == SVR_8541 || ver == SVR_8555) {
481 puts("256 KiB "); 529 puts("256 KiB ");
482 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 530 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
483 cache_ctl = 0xc8000000; 531 cache_ctl = 0xc8000000;
484 } else { 532 } else {
485 puts("512 KiB "); 533 puts("512 KiB ");
486 /* set L2E=1, L2I=1, & L2SRAM=0 */ 534 /* set L2E=1, L2I=1, & L2SRAM=0 */
487 cache_ctl = 0xc0000000; 535 cache_ctl = 0xc0000000;
488 } 536 }
489 break; 537 break;
490 case 0x3: 538 case 0x3:
491 puts("1024 KiB "); 539 puts("1024 KiB ");
492 /* set L2E=1, L2I=1, & L2SRAM=0 */ 540 /* set L2E=1, L2I=1, & L2SRAM=0 */
493 cache_ctl = 0xc0000000; 541 cache_ctl = 0xc0000000;
494 break; 542 break;
495 } 543 }
496 544
497 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 545 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
498 puts("already enabled"); 546 puts("already enabled");
499 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 547 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
500 u32 l2srbar = l2cache->l2srbar0; 548 u32 l2srbar = l2cache->l2srbar0;
501 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 549 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
502 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 550 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
503 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 551 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
504 l2cache->l2srbar0 = l2srbar; 552 l2cache->l2srbar0 = l2srbar;
505 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 553 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
506 } 554 }
507 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 555 #endif /* CONFIG_SYS_INIT_L2_ADDR */
508 puts("\n"); 556 puts("\n");
509 } else { 557 } else {
510 asm("msync;isync"); 558 asm("msync;isync");
511 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 559 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
512 asm("msync;isync"); 560 asm("msync;isync");
513 puts("enabled\n"); 561 puts("enabled\n");
514 } 562 }
515 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 563 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
516 if (SVR_SOC_VER(svr) == SVR_P2040) { 564 if (SVR_SOC_VER(svr) == SVR_P2040) {
517 puts("N/A\n"); 565 puts("N/A\n");
518 goto skip_l2; 566 goto skip_l2;
519 } 567 }
520 568
521 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 569 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
522 570
523 /* invalidate the L2 cache */ 571 /* invalidate the L2 cache */
524 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 572 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
525 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 573 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
526 ; 574 ;
527 575
528 #ifdef CONFIG_SYS_CACHE_STASHING 576 #ifdef CONFIG_SYS_CACHE_STASHING
529 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 577 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
530 mtspr(SPRN_L2CSR1, (32 + 1)); 578 mtspr(SPRN_L2CSR1, (32 + 1));
531 #endif 579 #endif
532 580
533 /* enable the cache */ 581 /* enable the cache */
534 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 582 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
535 583
536 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 584 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
537 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 585 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
538 ; 586 ;
539 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 587 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
540 } 588 }
541 589
542 skip_l2: 590 skip_l2:
543 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 591 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
544 if (l2cache->l2csr0 & L2CSR0_L2E) 592 if (l2cache->l2csr0 & L2CSR0_L2E)
545 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 593 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
546 " enabled\n"); 594 " enabled\n");
547 595
548 enable_cluster_l2(); 596 enable_cluster_l2();
549 #else 597 #else
550 puts("disabled\n"); 598 puts("disabled\n");
551 #endif 599 #endif
552 600
553 enable_cpc(); 601 enable_cpc();
554 602
555 #ifndef CONFIG_SYS_FSL_NO_SERDES 603 #ifndef CONFIG_SYS_FSL_NO_SERDES
556 /* needs to be in ram since code uses global static vars */ 604 /* needs to be in ram since code uses global static vars */
557 fsl_serdes_init(); 605 fsl_serdes_init();
558 #endif 606 #endif
559 607
560 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 608 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
561 #define MCFGR_AXIPIPE 0x000000f0 609 #define MCFGR_AXIPIPE 0x000000f0
562 if (IS_SVR_REV(svr, 1, 0)) 610 if (IS_SVR_REV(svr, 1, 0))
563 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 611 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
564 #endif 612 #endif
565 613
566 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 614 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
567 if (IS_SVR_REV(svr, 1, 0)) { 615 if (IS_SVR_REV(svr, 1, 0)) {
568 int i; 616 int i;
569 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 617 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
570 618
571 for (i = 0; i < 12; i++) { 619 for (i = 0; i < 12; i++) {
572 p += i + (i > 5 ? 11 : 0); 620 p += i + (i > 5 ? 11 : 0);
573 out_be32(p, 0x2); 621 out_be32(p, 0x2);
574 } 622 }
575 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 623 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
576 out_be32(p, 0x34); 624 out_be32(p, 0x34);
577 } 625 }
578 #endif 626 #endif
579 627
580 #ifdef CONFIG_SYS_SRIO 628 #ifdef CONFIG_SYS_SRIO
581 srio_init(); 629 srio_init();
582 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 630 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
583 char *s = getenv("bootmaster"); 631 char *s = getenv("bootmaster");
584 if (s) { 632 if (s) {
585 if (!strcmp(s, "SRIO1")) { 633 if (!strcmp(s, "SRIO1")) {
586 srio_boot_master(1); 634 srio_boot_master(1);
587 srio_boot_master_release_slave(1); 635 srio_boot_master_release_slave(1);
588 } 636 }
589 if (!strcmp(s, "SRIO2")) { 637 if (!strcmp(s, "SRIO2")) {
590 srio_boot_master(2); 638 srio_boot_master(2);
591 srio_boot_master_release_slave(2); 639 srio_boot_master_release_slave(2);
592 } 640 }
593 } 641 }
594 #endif 642 #endif
595 #endif 643 #endif
596 644
597 #if defined(CONFIG_MP) 645 #if defined(CONFIG_MP)
598 setup_mp(); 646 setup_mp();
599 #endif 647 #endif
600 648
601 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 649 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
602 { 650 {
603 if (SVR_MAJ(svr) < 3) { 651 if (SVR_MAJ(svr) < 3) {
604 void *p; 652 void *p;
605 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 653 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
606 setbits_be32(p, 1 << (31 - 14)); 654 setbits_be32(p, 1 << (31 - 14));
607 } 655 }
608 } 656 }
609 #endif 657 #endif
610 658
611 #ifdef CONFIG_SYS_LBC_LCRR 659 #ifdef CONFIG_SYS_LBC_LCRR
612 /* 660 /*
613 * Modify the CLKDIV field of LCRR register to improve the writing 661 * Modify the CLKDIV field of LCRR register to improve the writing
614 * speed for NOR flash. 662 * speed for NOR flash.
615 */ 663 */
616 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 664 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
617 __raw_readl(&lbc->lcrr); 665 __raw_readl(&lbc->lcrr);
618 isync(); 666 isync();
619 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 667 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
620 udelay(100); 668 udelay(100);
621 #endif 669 #endif
622 #endif 670 #endif
623 671
624 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 672 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
625 { 673 {
626 struct ccsr_usb_phy __iomem *usb_phy1 = 674 struct ccsr_usb_phy __iomem *usb_phy1 =
627 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 675 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
676 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
677 if (has_erratum_a006261())
678 fsl_erratum_a006261_workaround(usb_phy1);
679 #endif
628 out_be32(&usb_phy1->usb_enable_override, 680 out_be32(&usb_phy1->usb_enable_override,
629 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 681 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
630 } 682 }
631 #endif 683 #endif
632 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 684 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
633 { 685 {
634 struct ccsr_usb_phy __iomem *usb_phy2 = 686 struct ccsr_usb_phy __iomem *usb_phy2 =
635 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 687 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
688 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
689 if (has_erratum_a006261())
690 fsl_erratum_a006261_workaround(usb_phy2);
691 #endif
636 out_be32(&usb_phy2->usb_enable_override, 692 out_be32(&usb_phy2->usb_enable_override,
637 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 693 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
638 } 694 }
639 #endif 695 #endif
640 696
641 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 697 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
642 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 698 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
643 * multi-bit ECC errors which has impact on performance, so software 699 * multi-bit ECC errors which has impact on performance, so software
644 * should disable all ECC reporting from USB1 and USB2. 700 * should disable all ECC reporting from USB1 and USB2.
645 */ 701 */
646 if (IS_SVR_REV(get_svr(), 1, 0)) { 702 if (IS_SVR_REV(get_svr(), 1, 0)) {
647 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 703 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
648 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 704 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
649 setbits_be32(&dcfg->ecccr1, 705 setbits_be32(&dcfg->ecccr1,
650 (DCSR_DCFG_ECC_DISABLE_USB1 | 706 (DCSR_DCFG_ECC_DISABLE_USB1 |
651 DCSR_DCFG_ECC_DISABLE_USB2)); 707 DCSR_DCFG_ECC_DISABLE_USB2));
652 } 708 }
653 #endif 709 #endif
654 710
655 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 711 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
656 struct ccsr_usb_phy __iomem *usb_phy = 712 struct ccsr_usb_phy __iomem *usb_phy =
657 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 713 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
658 setbits_be32(&usb_phy->pllprg[1], 714 setbits_be32(&usb_phy->pllprg[1],
659 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 715 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
660 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 716 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
661 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 717 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
662 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 718 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
663 setbits_be32(&usb_phy->port1.ctrl, 719 setbits_be32(&usb_phy->port1.ctrl,
664 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 720 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
665 setbits_be32(&usb_phy->port1.drvvbuscfg, 721 setbits_be32(&usb_phy->port1.drvvbuscfg,
666 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 722 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
667 setbits_be32(&usb_phy->port1.pwrfltcfg, 723 setbits_be32(&usb_phy->port1.pwrfltcfg,
668 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 724 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
669 setbits_be32(&usb_phy->port2.ctrl, 725 setbits_be32(&usb_phy->port2.ctrl,
670 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 726 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
671 setbits_be32(&usb_phy->port2.drvvbuscfg, 727 setbits_be32(&usb_phy->port2.drvvbuscfg,
672 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 728 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
673 setbits_be32(&usb_phy->port2.pwrfltcfg, 729 setbits_be32(&usb_phy->port2.pwrfltcfg,
674 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 730 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
731
732 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
733 if (has_erratum_a006261())
734 fsl_erratum_a006261_workaround(usb_phy);
675 #endif 735 #endif
736
737 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
676 738
677 #ifdef CONFIG_FMAN_ENET 739 #ifdef CONFIG_FMAN_ENET
678 fman_enet_init(); 740 fman_enet_init();
679 #endif 741 #endif
680 742
681 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 743 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
682 /* 744 /*
683 * For P1022/1013 Rev1.0 silicon, after power on SATA host 745 * For P1022/1013 Rev1.0 silicon, after power on SATA host
684 * controller is configured in legacy mode instead of the 746 * controller is configured in legacy mode instead of the
685 * expected enterprise mode. Software needs to clear bit[28] 747 * expected enterprise mode. Software needs to clear bit[28]
686 * of HControl register to change to enterprise mode from 748 * of HControl register to change to enterprise mode from
687 * legacy mode. We assume that the controller is offline. 749 * legacy mode. We assume that the controller is offline.
688 */ 750 */
689 if (IS_SVR_REV(svr, 1, 0) && 751 if (IS_SVR_REV(svr, 1, 0) &&
690 ((SVR_SOC_VER(svr) == SVR_P1022) || 752 ((SVR_SOC_VER(svr) == SVR_P1022) ||
691 (SVR_SOC_VER(svr) == SVR_P1013))) { 753 (SVR_SOC_VER(svr) == SVR_P1013))) {
692 fsl_sata_reg_t *reg; 754 fsl_sata_reg_t *reg;
693 755
694 /* first SATA controller */ 756 /* first SATA controller */
695 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 757 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
696 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN); 758 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
697 759
698 /* second SATA controller */ 760 /* second SATA controller */
699 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 761 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
700 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN); 762 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
701 } 763 }
702 #endif 764 #endif
703 765
704 766
705 return 0; 767 return 0;
706 } 768 }
707 769
708 extern void setup_ivors(void); 770 extern void setup_ivors(void);
709 771
710 void arch_preboot_os(void) 772 void arch_preboot_os(void)
711 { 773 {
712 u32 msr; 774 u32 msr;
713 775
714 /* 776 /*
715 * We are changing interrupt offsets and are about to boot the OS so 777 * We are changing interrupt offsets and are about to boot the OS so
716 * we need to make sure we disable all async interrupts. EE is already 778 * we need to make sure we disable all async interrupts. EE is already
717 * disabled by the time we get called. 779 * disabled by the time we get called.
718 */ 780 */
719 msr = mfmsr(); 781 msr = mfmsr();
720 msr &= ~(MSR_ME|MSR_CE); 782 msr &= ~(MSR_ME|MSR_CE);
721 mtmsr(msr); 783 mtmsr(msr);
722 784
723 setup_ivors(); 785 setup_ivors();
724 } 786 }
725 787
726 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 788 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
727 int sata_initialize(void) 789 int sata_initialize(void)
728 { 790 {
729 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 791 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
730 return __sata_initialize(); 792 return __sata_initialize();
731 793
732 return 1; 794 return 1;
733 } 795 }
734 #endif 796 #endif
735 797
736 void cpu_secondary_init_r(void) 798 void cpu_secondary_init_r(void)
737 { 799 {
738 #ifdef CONFIG_QE 800 #ifdef CONFIG_QE
739 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 801 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
740 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 802 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
741 int ret; 803 int ret;
742 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 804 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
743 805
744 /* load QE firmware from NAND flash to DDR first */ 806 /* load QE firmware from NAND flash to DDR first */
745 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 807 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
746 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 808 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
747 809
748 if (ret && ret == -EUCLEAN) { 810 if (ret && ret == -EUCLEAN) {
749 printf ("NAND read for QE firmware at offset %x failed %d\n", 811 printf ("NAND read for QE firmware at offset %x failed %d\n",
750 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 812 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
751 } 813 }
752 #endif 814 #endif
753 qe_init(qe_base); 815 qe_init(qe_base);
754 qe_reset(); 816 qe_reset();
755 #endif 817 #endif
756 } 818 }
757 819
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ 9c641a8
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _ASM_MPC85xx_CONFIG_H_ 7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_
9 9
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11 11
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14 #endif 14 #endif
15 15
16 /* 16 /*
17 * This macro should be removed when we no longer care about backwards 17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems. 18 * compatibility with older operating systems.
19 */ 19 */
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
21 21
22 #define FSL_DDR_VER_4_7 47 22 #define FSL_DDR_VER_4_7 47
23 #define FSL_DDR_VER_5_0 50 23 #define FSL_DDR_VER_5_0 50
24 24
25 /* IP endianness */ 25 /* IP endianness */
26 #define CONFIG_SYS_FSL_IFC_BE 26 #define CONFIG_SYS_FSL_IFC_BE
27 27
28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 28 /* Number of TLB CAM entries we have on FSL Book-E chips */
29 #if defined(CONFIG_E500MC) 29 #if defined(CONFIG_E500MC)
30 #define CONFIG_SYS_NUM_TLBCAMS 64 30 #define CONFIG_SYS_NUM_TLBCAMS 64
31 #elif defined(CONFIG_E500) 31 #elif defined(CONFIG_E500)
32 #define CONFIG_SYS_NUM_TLBCAMS 16 32 #define CONFIG_SYS_NUM_TLBCAMS 16
33 #endif 33 #endif
34 34
35 #if defined(CONFIG_MPC8536) 35 #if defined(CONFIG_MPC8536)
36 #define CONFIG_MAX_CPUS 1 36 #define CONFIG_MAX_CPUS 1
37 #define CONFIG_SYS_FSL_NUM_LAWS 12 37 #define CONFIG_SYS_FSL_NUM_LAWS 12
38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2
40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
41 #define CONFIG_SYS_FSL_ERRATUM_A005125 41 #define CONFIG_SYS_FSL_ERRATUM_A005125
42 42
43 #elif defined(CONFIG_MPC8540) 43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_DDRC_GEN1 46 #define CONFIG_SYS_FSL_DDRC_GEN1
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
48 48
49 #elif defined(CONFIG_MPC8541) 49 #elif defined(CONFIG_MPC8541)
50 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_NUM_LAWS 8
52 #define CONFIG_SYS_FSL_DDRC_GEN1 52 #define CONFIG_SYS_FSL_DDRC_GEN1
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
55 55
56 #elif defined(CONFIG_MPC8544) 56 #elif defined(CONFIG_MPC8544)
57 #define CONFIG_MAX_CPUS 1 57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10 58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2 59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
63 #define CONFIG_SYS_FSL_ERRATUM_A005125 63 #define CONFIG_SYS_FSL_ERRATUM_A005125
64 64
65 #elif defined(CONFIG_MPC8548) 65 #elif defined(CONFIG_MPC8548)
66 #define CONFIG_MAX_CPUS 1 66 #define CONFIG_MAX_CPUS 1
67 #define CONFIG_SYS_FSL_NUM_LAWS 10 67 #define CONFIG_SYS_FSL_NUM_LAWS 10
68 #define CONFIG_SYS_FSL_DDRC_GEN2 68 #define CONFIG_SYS_FSL_DDRC_GEN2
69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
70 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_FSL_SEC_COMPAT 2
71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
78 #define CONFIG_SYS_FSL_RMU 78 #define CONFIG_SYS_FSL_RMU
79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
80 #define CONFIG_SYS_FSL_ERRATUM_A005125 80 #define CONFIG_SYS_FSL_ERRATUM_A005125
81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
83 83
84 #elif defined(CONFIG_MPC8555) 84 #elif defined(CONFIG_MPC8555)
85 #define CONFIG_MAX_CPUS 1 85 #define CONFIG_MAX_CPUS 1
86 #define CONFIG_SYS_FSL_NUM_LAWS 8 86 #define CONFIG_SYS_FSL_NUM_LAWS 8
87 #define CONFIG_SYS_FSL_DDRC_GEN1 87 #define CONFIG_SYS_FSL_DDRC_GEN1
88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
90 90
91 #elif defined(CONFIG_MPC8560) 91 #elif defined(CONFIG_MPC8560)
92 #define CONFIG_MAX_CPUS 1 92 #define CONFIG_MAX_CPUS 1
93 #define CONFIG_SYS_FSL_NUM_LAWS 8 93 #define CONFIG_SYS_FSL_NUM_LAWS 8
94 #define CONFIG_SYS_FSL_DDRC_GEN1 94 #define CONFIG_SYS_FSL_DDRC_GEN1
95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
96 96
97 #elif defined(CONFIG_MPC8568) 97 #elif defined(CONFIG_MPC8568)
98 #define CONFIG_MAX_CPUS 1 98 #define CONFIG_MAX_CPUS 1
99 #define CONFIG_SYS_FSL_NUM_LAWS 10 99 #define CONFIG_SYS_FSL_NUM_LAWS 10
100 #define CONFIG_SYS_FSL_DDRC_GEN2 100 #define CONFIG_SYS_FSL_DDRC_GEN2
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define QE_MURAM_SIZE 0x10000UL 102 #define QE_MURAM_SIZE 0x10000UL
103 #define MAX_QE_RISC 2 103 #define MAX_QE_RISC 2
104 #define QE_NUM_OF_SNUM 28 104 #define QE_NUM_OF_SNUM 28
105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109 #define CONFIG_SYS_FSL_RMU 109 #define CONFIG_SYS_FSL_RMU
110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
111 111
112 #elif defined(CONFIG_MPC8569) 112 #elif defined(CONFIG_MPC8569)
113 #define CONFIG_MAX_CPUS 1 113 #define CONFIG_MAX_CPUS 1
114 #define CONFIG_SYS_FSL_NUM_LAWS 10 114 #define CONFIG_SYS_FSL_NUM_LAWS 10
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2 115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define QE_MURAM_SIZE 0x20000UL 116 #define QE_MURAM_SIZE 0x20000UL
117 #define MAX_QE_RISC 4 117 #define MAX_QE_RISC 4
118 #define QE_NUM_OF_SNUM 46 118 #define QE_NUM_OF_SNUM 46
119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
123 #define CONFIG_SYS_FSL_RMU 123 #define CONFIG_SYS_FSL_RMU
124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
125 #define CONFIG_SYS_FSL_ERRATUM_A005125 125 #define CONFIG_SYS_FSL_ERRATUM_A005125
126 126
127 #elif defined(CONFIG_MPC8572) 127 #elif defined(CONFIG_MPC8572)
128 #define CONFIG_MAX_CPUS 2 128 #define CONFIG_MAX_CPUS 2
129 #define CONFIG_SYS_FSL_NUM_LAWS 12 129 #define CONFIG_SYS_FSL_NUM_LAWS 12
130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
131 #define CONFIG_SYS_FSL_SEC_COMPAT 2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 2
132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
135 #define CONFIG_SYS_FSL_ERRATUM_A005125 135 #define CONFIG_SYS_FSL_ERRATUM_A005125
136 136
137 #elif defined(CONFIG_P1010) 137 #elif defined(CONFIG_P1010)
138 #define CONFIG_MAX_CPUS 1 138 #define CONFIG_MAX_CPUS 1
139 #define CONFIG_FSL_SDHC_V2_3 139 #define CONFIG_FSL_SDHC_V2_3
140 #define CONFIG_SYS_FSL_NUM_LAWS 12 140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
142 #define CONFIG_TSECV2 142 #define CONFIG_TSECV2
143 #define CONFIG_SYS_FSL_SEC_COMPAT 4 143 #define CONFIG_SYS_FSL_SEC_COMPAT 4
144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145 #define CONFIG_NUM_DDR_CONTROLLERS 1 145 #define CONFIG_NUM_DDR_CONTROLLERS 1
146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155 #define CONFIG_SYS_FSL_ERRATUM_A005125 155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
157 #define CONFIG_SYS_FSL_ERRATUM_A006261
157 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 158 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
158 #define CONFIG_ESDHC_HC_BLK_ADDR 159 #define CONFIG_ESDHC_HC_BLK_ADDR
159 160
160 /* P1011 is single core version of P1020 */ 161 /* P1011 is single core version of P1020 */
161 #elif defined(CONFIG_P1011) 162 #elif defined(CONFIG_P1011)
162 #define CONFIG_MAX_CPUS 1 163 #define CONFIG_MAX_CPUS 1
163 #define CONFIG_SYS_FSL_NUM_LAWS 12 164 #define CONFIG_SYS_FSL_NUM_LAWS 12
164 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
165 #define CONFIG_TSECV2 166 #define CONFIG_TSECV2
166 #define CONFIG_FSL_PCIE_DISABLE_ASPM 167 #define CONFIG_FSL_PCIE_DISABLE_ASPM
167 #define CONFIG_SYS_FSL_SEC_COMPAT 2 168 #define CONFIG_SYS_FSL_SEC_COMPAT 2
168 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 169 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
169 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 #define CONFIG_SYS_FSL_ERRATUM_A005125 173 #define CONFIG_SYS_FSL_ERRATUM_A005125
173 174
174 /* P1012 is single core version of P1021 */ 175 /* P1012 is single core version of P1021 */
175 #elif defined(CONFIG_P1012) 176 #elif defined(CONFIG_P1012)
176 #define CONFIG_MAX_CPUS 1 177 #define CONFIG_MAX_CPUS 1
177 #define CONFIG_SYS_FSL_NUM_LAWS 12 178 #define CONFIG_SYS_FSL_NUM_LAWS 12
178 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
179 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
180 #define CONFIG_TSECV2 181 #define CONFIG_TSECV2
181 #define CONFIG_FSL_PCIE_DISABLE_ASPM 182 #define CONFIG_FSL_PCIE_DISABLE_ASPM
182 #define CONFIG_SYS_FSL_SEC_COMPAT 2 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2
183 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186 #define QE_MURAM_SIZE 0x6000UL 187 #define QE_MURAM_SIZE 0x6000UL
187 #define MAX_QE_RISC 1 188 #define MAX_QE_RISC 1
188 #define QE_NUM_OF_SNUM 28 189 #define QE_NUM_OF_SNUM 28
189 #define CONFIG_SYS_FSL_ERRATUM_A005125 190 #define CONFIG_SYS_FSL_ERRATUM_A005125
190 191
191 /* P1013 is single core version of P1022 */ 192 /* P1013 is single core version of P1022 */
192 #elif defined(CONFIG_P1013) 193 #elif defined(CONFIG_P1013)
193 #define CONFIG_MAX_CPUS 1 194 #define CONFIG_MAX_CPUS 1
194 #define CONFIG_SYS_FSL_NUM_LAWS 12 195 #define CONFIG_SYS_FSL_NUM_LAWS 12
195 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 196 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
196 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 197 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
197 #define CONFIG_TSECV2 198 #define CONFIG_TSECV2
198 #define CONFIG_SYS_FSL_SEC_COMPAT 2 199 #define CONFIG_SYS_FSL_SEC_COMPAT 2
199 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 200 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
200 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 201 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
201 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 202 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
202 #define CONFIG_FSL_SATA_ERRATUM_A001 203 #define CONFIG_FSL_SATA_ERRATUM_A001
203 #define CONFIG_SYS_FSL_ERRATUM_A005125 204 #define CONFIG_SYS_FSL_ERRATUM_A005125
204 205
205 #elif defined(CONFIG_P1014) 206 #elif defined(CONFIG_P1014)
206 #define CONFIG_MAX_CPUS 1 207 #define CONFIG_MAX_CPUS 1
207 #define CONFIG_FSL_SDHC_V2_3 208 #define CONFIG_FSL_SDHC_V2_3
208 #define CONFIG_SYS_FSL_NUM_LAWS 12 209 #define CONFIG_SYS_FSL_NUM_LAWS 12
209 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 210 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
210 #define CONFIG_TSECV2 211 #define CONFIG_TSECV2
211 #define CONFIG_SYS_FSL_SEC_COMPAT 4 212 #define CONFIG_SYS_FSL_SEC_COMPAT 4
212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
213 #define CONFIG_NUM_DDR_CONTROLLERS 1 214 #define CONFIG_NUM_DDR_CONTROLLERS 1
214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 215 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
216 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 217 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
217 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 218 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
218 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 219 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
219 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 220 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
220 221
221 /* P1017 is single core version of P1023 */ 222 /* P1017 is single core version of P1023 */
222 #elif defined(CONFIG_P1017) 223 #elif defined(CONFIG_P1017)
223 #define CONFIG_MAX_CPUS 1 224 #define CONFIG_MAX_CPUS 1
224 #define CONFIG_SYS_FSL_NUM_LAWS 12 225 #define CONFIG_SYS_FSL_NUM_LAWS 12
225 #define CONFIG_SYS_FSL_SEC_COMPAT 4 226 #define CONFIG_SYS_FSL_SEC_COMPAT 4
226 #define CONFIG_SYS_NUM_FMAN 1 227 #define CONFIG_SYS_NUM_FMAN 1
227 #define CONFIG_SYS_NUM_FM1_DTSEC 2 228 #define CONFIG_SYS_NUM_FM1_DTSEC 2
228 #define CONFIG_NUM_DDR_CONTROLLERS 1 229 #define CONFIG_NUM_DDR_CONTROLLERS 1
229 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 230 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
230 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 231 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
231 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 232 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
232 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 233 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
233 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 234 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
234 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
235 #define CONFIG_SYS_FSL_ERRATUM_A005125 236 #define CONFIG_SYS_FSL_ERRATUM_A005125
236 237
237 #elif defined(CONFIG_P1020) 238 #elif defined(CONFIG_P1020)
238 #define CONFIG_MAX_CPUS 2 239 #define CONFIG_MAX_CPUS 2
239 #define CONFIG_SYS_FSL_NUM_LAWS 12 240 #define CONFIG_SYS_FSL_NUM_LAWS 12
240 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 241 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
241 #define CONFIG_TSECV2 242 #define CONFIG_TSECV2
242 #define CONFIG_FSL_PCIE_DISABLE_ASPM 243 #define CONFIG_FSL_PCIE_DISABLE_ASPM
243 #define CONFIG_SYS_FSL_SEC_COMPAT 2 244 #define CONFIG_SYS_FSL_SEC_COMPAT 2
244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 245 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 246 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247 #define CONFIG_SYS_FSL_ERRATUM_A005125 248 #define CONFIG_SYS_FSL_ERRATUM_A005125
248 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 249 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
249 250
250 #elif defined(CONFIG_P1021) 251 #elif defined(CONFIG_P1021)
251 #define CONFIG_MAX_CPUS 2 252 #define CONFIG_MAX_CPUS 2
252 #define CONFIG_SYS_FSL_NUM_LAWS 12 253 #define CONFIG_SYS_FSL_NUM_LAWS 12
253 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
254 #define CONFIG_TSECV2 255 #define CONFIG_TSECV2
255 #define CONFIG_FSL_PCIE_DISABLE_ASPM 256 #define CONFIG_FSL_PCIE_DISABLE_ASPM
256 #define CONFIG_SYS_FSL_SEC_COMPAT 2 257 #define CONFIG_SYS_FSL_SEC_COMPAT 2
257 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
258 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
259 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
260 #define QE_MURAM_SIZE 0x6000UL 261 #define QE_MURAM_SIZE 0x6000UL
261 #define MAX_QE_RISC 1 262 #define MAX_QE_RISC 1
262 #define QE_NUM_OF_SNUM 28 263 #define QE_NUM_OF_SNUM 28
263 #define CONFIG_SYS_FSL_ERRATUM_A005125 264 #define CONFIG_SYS_FSL_ERRATUM_A005125
264 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 265 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
265 266
266 #elif defined(CONFIG_P1022) 267 #elif defined(CONFIG_P1022)
267 #define CONFIG_MAX_CPUS 2 268 #define CONFIG_MAX_CPUS 2
268 #define CONFIG_SYS_FSL_NUM_LAWS 12 269 #define CONFIG_SYS_FSL_NUM_LAWS 12
269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
270 #define CONFIG_TSECV2 271 #define CONFIG_TSECV2
271 #define CONFIG_SYS_FSL_SEC_COMPAT 2 272 #define CONFIG_SYS_FSL_SEC_COMPAT 2
272 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 273 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
276 #define CONFIG_FSL_SATA_ERRATUM_A001 277 #define CONFIG_FSL_SATA_ERRATUM_A001
277 #define CONFIG_SYS_FSL_ERRATUM_A005125 278 #define CONFIG_SYS_FSL_ERRATUM_A005125
278 279
279 #elif defined(CONFIG_P1023) 280 #elif defined(CONFIG_P1023)
280 #define CONFIG_MAX_CPUS 2 281 #define CONFIG_MAX_CPUS 2
281 #define CONFIG_SYS_FSL_NUM_LAWS 12 282 #define CONFIG_SYS_FSL_NUM_LAWS 12
282 #define CONFIG_SYS_FSL_SEC_COMPAT 4 283 #define CONFIG_SYS_FSL_SEC_COMPAT 4
283 #define CONFIG_SYS_NUM_FMAN 1 284 #define CONFIG_SYS_NUM_FMAN 1
284 #define CONFIG_SYS_NUM_FM1_DTSEC 2 285 #define CONFIG_SYS_NUM_FM1_DTSEC 2
285 #define CONFIG_NUM_DDR_CONTROLLERS 1 286 #define CONFIG_NUM_DDR_CONTROLLERS 1
286 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
287 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 288 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
288 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 289 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
289 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 290 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
290 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 291 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
292 #define CONFIG_SYS_FSL_ERRATUM_A005125 293 #define CONFIG_SYS_FSL_ERRATUM_A005125
293 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 294 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
294 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 295 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
295 296
296 /* P1024 is lower end variant of P1020 */ 297 /* P1024 is lower end variant of P1020 */
297 #elif defined(CONFIG_P1024) 298 #elif defined(CONFIG_P1024)
298 #define CONFIG_MAX_CPUS 2 299 #define CONFIG_MAX_CPUS 2
299 #define CONFIG_SYS_FSL_NUM_LAWS 12 300 #define CONFIG_SYS_FSL_NUM_LAWS 12
300 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
301 #define CONFIG_TSECV2 302 #define CONFIG_TSECV2
302 #define CONFIG_FSL_PCIE_DISABLE_ASPM 303 #define CONFIG_FSL_PCIE_DISABLE_ASPM
303 #define CONFIG_SYS_FSL_SEC_COMPAT 2 304 #define CONFIG_SYS_FSL_SEC_COMPAT 2
304 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
305 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
306 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 307 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
308 #define CONFIG_SYS_FSL_ERRATUM_A005125 309 #define CONFIG_SYS_FSL_ERRATUM_A005125
309 310
310 /* P1025 is lower end variant of P1021 */ 311 /* P1025 is lower end variant of P1021 */
311 #elif defined(CONFIG_P1025) 312 #elif defined(CONFIG_P1025)
312 #define CONFIG_MAX_CPUS 2 313 #define CONFIG_MAX_CPUS 2
313 #define CONFIG_SYS_FSL_NUM_LAWS 12 314 #define CONFIG_SYS_FSL_NUM_LAWS 12
314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
315 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 316 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
316 #define CONFIG_TSECV2 317 #define CONFIG_TSECV2
317 #define CONFIG_FSL_PCIE_DISABLE_ASPM 318 #define CONFIG_FSL_PCIE_DISABLE_ASPM
318 #define CONFIG_SYS_FSL_SEC_COMPAT 2 319 #define CONFIG_SYS_FSL_SEC_COMPAT 2
319 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
320 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 321 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
322 #define QE_MURAM_SIZE 0x6000UL 323 #define QE_MURAM_SIZE 0x6000UL
323 #define MAX_QE_RISC 1 324 #define MAX_QE_RISC 1
324 #define QE_NUM_OF_SNUM 28 325 #define QE_NUM_OF_SNUM 28
325 #define CONFIG_SYS_FSL_ERRATUM_A005125 326 #define CONFIG_SYS_FSL_ERRATUM_A005125
326 327
327 /* P2010 is single core version of P2020 */ 328 /* P2010 is single core version of P2020 */
328 #elif defined(CONFIG_P2010) 329 #elif defined(CONFIG_P2010)
329 #define CONFIG_MAX_CPUS 1 330 #define CONFIG_MAX_CPUS 1
330 #define CONFIG_SYS_FSL_NUM_LAWS 12 331 #define CONFIG_SYS_FSL_NUM_LAWS 12
331 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 332 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
332 #define CONFIG_SYS_FSL_SEC_COMPAT 2 333 #define CONFIG_SYS_FSL_SEC_COMPAT 2
333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 334 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
334 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
337 #define CONFIG_SYS_FSL_ERRATUM_A005125 338 #define CONFIG_SYS_FSL_ERRATUM_A005125
338 339
339 #elif defined(CONFIG_P2020) 340 #elif defined(CONFIG_P2020)
340 #define CONFIG_MAX_CPUS 2 341 #define CONFIG_MAX_CPUS 2
341 #define CONFIG_SYS_FSL_NUM_LAWS 12 342 #define CONFIG_SYS_FSL_NUM_LAWS 12
342 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 343 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
343 #define CONFIG_SYS_FSL_SEC_COMPAT 2 344 #define CONFIG_SYS_FSL_SEC_COMPAT 2
344 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 345 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
345 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
347 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 348 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
348 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 349 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
349 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 350 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
350 #define CONFIG_SYS_FSL_RMU 351 #define CONFIG_SYS_FSL_RMU
351 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 352 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
352 #define CONFIG_SYS_FSL_ERRATUM_A005125 353 #define CONFIG_SYS_FSL_ERRATUM_A005125
353 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
354 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 355 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
355 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 356 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
356 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 357 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
357 #define CONFIG_MAX_CPUS 4 358 #define CONFIG_MAX_CPUS 4
358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 359 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
359 #define CONFIG_SYS_FSL_NUM_LAWS 32 360 #define CONFIG_SYS_FSL_NUM_LAWS 32
360 #define CONFIG_SYS_FSL_SEC_COMPAT 4 361 #define CONFIG_SYS_FSL_SEC_COMPAT 4
361 #define CONFIG_SYS_NUM_FMAN 1 362 #define CONFIG_SYS_NUM_FMAN 1
362 #define CONFIG_SYS_NUM_FM1_DTSEC 5 363 #define CONFIG_SYS_NUM_FM1_DTSEC 5
363 #define CONFIG_SYS_NUM_FM1_10GEC 1 364 #define CONFIG_SYS_NUM_FM1_10GEC 1
364 #define CONFIG_NUM_DDR_CONTROLLERS 1 365 #define CONFIG_NUM_DDR_CONTROLLERS 1
365 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 366 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
366 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
367 #define CONFIG_SYS_FSL_TBCLK_DIV 32 368 #define CONFIG_SYS_FSL_TBCLK_DIV 32
368 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
369 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
370 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 371 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
371 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
372 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
373 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
374 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 375 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
375 #define CONFIG_SYS_FSL_ERRATUM_USB14 376 #define CONFIG_SYS_FSL_ERRATUM_USB14
376 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
377 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
379 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
380 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
381 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
382 #define CONFIG_SYS_FSL_ERRATUM_A004510 383 #define CONFIG_SYS_FSL_ERRATUM_A004510
383 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
385 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 386 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
386 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
387 #define CONFIG_SYS_FSL_ERRATUM_A004849 388 #define CONFIG_SYS_FSL_ERRATUM_A004849
388 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 389 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
390 #define CONFIG_SYS_FSL_ERRATUM_A006261
389 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 391 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
390 392
391 #elif defined(CONFIG_PPC_P3041) 393 #elif defined(CONFIG_PPC_P3041)
392 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 394 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
393 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 395 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
394 #define CONFIG_MAX_CPUS 4 396 #define CONFIG_MAX_CPUS 4
395 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 397 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
396 #define CONFIG_SYS_FSL_NUM_LAWS 32 398 #define CONFIG_SYS_FSL_NUM_LAWS 32
397 #define CONFIG_SYS_FSL_SEC_COMPAT 4 399 #define CONFIG_SYS_FSL_SEC_COMPAT 4
398 #define CONFIG_SYS_NUM_FMAN 1 400 #define CONFIG_SYS_NUM_FMAN 1
399 #define CONFIG_SYS_NUM_FM1_DTSEC 5 401 #define CONFIG_SYS_NUM_FM1_DTSEC 5
400 #define CONFIG_SYS_NUM_FM1_10GEC 1 402 #define CONFIG_SYS_NUM_FM1_10GEC 1
401 #define CONFIG_NUM_DDR_CONTROLLERS 1 403 #define CONFIG_NUM_DDR_CONTROLLERS 1
402 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 404 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
403 #define CONFIG_SYS_FSL_TBCLK_DIV 32 405 #define CONFIG_SYS_FSL_TBCLK_DIV 32
404 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 406 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
405 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 407 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
406 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 408 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
407 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 409 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
408 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 410 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 411 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
410 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 412 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
411 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 413 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
412 #define CONFIG_SYS_FSL_ERRATUM_USB14 414 #define CONFIG_SYS_FSL_ERRATUM_USB14
413 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 415 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
414 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 416 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
415 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
416 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 418 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
417 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 419 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
418 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 420 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
419 #define CONFIG_SYS_FSL_ERRATUM_A004510 421 #define CONFIG_SYS_FSL_ERRATUM_A004510
420 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 422 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 423 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
422 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 424 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
423 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 425 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
424 #define CONFIG_SYS_FSL_ERRATUM_A004849 426 #define CONFIG_SYS_FSL_ERRATUM_A004849
425 #define CONFIG_SYS_FSL_ERRATUM_A005812 427 #define CONFIG_SYS_FSL_ERRATUM_A005812
426 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
429 #define CONFIG_SYS_FSL_ERRATUM_A006261
427 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
428 431
429 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 432 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
430 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 433 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
431 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 434 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
432 #define CONFIG_MAX_CPUS 8 435 #define CONFIG_MAX_CPUS 8
433 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 436 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
434 #define CONFIG_SYS_FSL_NUM_LAWS 32 437 #define CONFIG_SYS_FSL_NUM_LAWS 32
435 #define CONFIG_SYS_FSL_SEC_COMPAT 4 438 #define CONFIG_SYS_FSL_SEC_COMPAT 4
436 #define CONFIG_SYS_NUM_FMAN 2 439 #define CONFIG_SYS_NUM_FMAN 2
437 #define CONFIG_SYS_NUM_FM1_DTSEC 4 440 #define CONFIG_SYS_NUM_FM1_DTSEC 4
438 #define CONFIG_SYS_NUM_FM2_DTSEC 4 441 #define CONFIG_SYS_NUM_FM2_DTSEC 4
439 #define CONFIG_SYS_NUM_FM1_10GEC 1 442 #define CONFIG_SYS_NUM_FM1_10GEC 1
440 #define CONFIG_SYS_NUM_FM2_10GEC 1 443 #define CONFIG_SYS_NUM_FM2_10GEC 1
441 #define CONFIG_NUM_DDR_CONTROLLERS 2 444 #define CONFIG_NUM_DDR_CONTROLLERS 2
442 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 445 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
443 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 446 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
444 #define CONFIG_SYS_FSL_TBCLK_DIV 16 447 #define CONFIG_SYS_FSL_TBCLK_DIV 16
445 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 448 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
446 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 449 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
447 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 450 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
448 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 451 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
449 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 452 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
450 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 453 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
451 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 454 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
452 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 455 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
453 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 456 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
454 #define CONFIG_SYS_P4080_ERRATUM_CPU22 457 #define CONFIG_SYS_P4080_ERRATUM_CPU22
455 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 458 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
456 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 459 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
457 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 460 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
458 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 461 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
459 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 462 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
460 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 463 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
461 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 464 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
462 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 465 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
463 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 466 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
464 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 467 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
465 #define CONFIG_SYS_FSL_RMU 468 #define CONFIG_SYS_FSL_RMU
466 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 469 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
467 #define CONFIG_SYS_FSL_ERRATUM_A004510 470 #define CONFIG_SYS_FSL_ERRATUM_A004510
468 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 471 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
469 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 472 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
470 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 473 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
471 #define CONFIG_SYS_FSL_ERRATUM_A004849 474 #define CONFIG_SYS_FSL_ERRATUM_A004849
472 #define CONFIG_SYS_FSL_ERRATUM_A004580 475 #define CONFIG_SYS_FSL_ERRATUM_A004580
473 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 476 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
474 #define CONFIG_SYS_FSL_ERRATUM_A005812 477 #define CONFIG_SYS_FSL_ERRATUM_A005812
475 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 478 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
476 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 479 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
477 480
478 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 481 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
479 #define CONFIG_SYS_PPC64 /* 64-bit core */ 482 #define CONFIG_SYS_PPC64 /* 64-bit core */
480 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 483 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
481 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 484 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
482 #define CONFIG_MAX_CPUS 2 485 #define CONFIG_MAX_CPUS 2
483 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 486 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
484 #define CONFIG_SYS_FSL_NUM_LAWS 32 487 #define CONFIG_SYS_FSL_NUM_LAWS 32
485 #define CONFIG_SYS_FSL_SEC_COMPAT 4 488 #define CONFIG_SYS_FSL_SEC_COMPAT 4
486 #define CONFIG_SYS_NUM_FMAN 1 489 #define CONFIG_SYS_NUM_FMAN 1
487 #define CONFIG_SYS_NUM_FM1_DTSEC 5 490 #define CONFIG_SYS_NUM_FM1_DTSEC 5
488 #define CONFIG_SYS_NUM_FM1_10GEC 1 491 #define CONFIG_SYS_NUM_FM1_10GEC 1
489 #define CONFIG_NUM_DDR_CONTROLLERS 2 492 #define CONFIG_NUM_DDR_CONTROLLERS 2
490 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 493 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
491 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 494 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
492 #define CONFIG_SYS_FSL_TBCLK_DIV 32 495 #define CONFIG_SYS_FSL_TBCLK_DIV 32
493 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 496 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
494 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 497 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
495 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 498 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
496 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 499 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
497 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 500 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
498 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 501 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
499 #define CONFIG_SYS_FSL_ERRATUM_USB14 502 #define CONFIG_SYS_FSL_ERRATUM_USB14
500 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 503 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
501 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 504 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
502 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 505 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
503 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 506 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
504 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 507 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
505 #define CONFIG_SYS_FSL_ERRATUM_A004510 508 #define CONFIG_SYS_FSL_ERRATUM_A004510
506 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 509 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
507 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 510 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
508 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 511 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
509 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 512 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
513 #define CONFIG_SYS_FSL_ERRATUM_A006261
510 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 514 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
511 515
512 #elif defined(CONFIG_PPC_P5040) 516 #elif defined(CONFIG_PPC_P5040)
513 #define CONFIG_SYS_PPC64 517 #define CONFIG_SYS_PPC64
514 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 518 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
515 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 519 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
516 #define CONFIG_MAX_CPUS 4 520 #define CONFIG_MAX_CPUS 4
517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 521 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
518 #define CONFIG_SYS_FSL_NUM_LAWS 32 522 #define CONFIG_SYS_FSL_NUM_LAWS 32
519 #define CONFIG_SYS_FSL_SEC_COMPAT 4 523 #define CONFIG_SYS_FSL_SEC_COMPAT 4
520 #define CONFIG_SYS_NUM_FMAN 2 524 #define CONFIG_SYS_NUM_FMAN 2
521 #define CONFIG_SYS_NUM_FM1_DTSEC 5 525 #define CONFIG_SYS_NUM_FM1_DTSEC 5
522 #define CONFIG_SYS_NUM_FM1_10GEC 1 526 #define CONFIG_SYS_NUM_FM1_10GEC 1
523 #define CONFIG_SYS_NUM_FM2_DTSEC 5 527 #define CONFIG_SYS_NUM_FM2_DTSEC 5
524 #define CONFIG_SYS_NUM_FM2_10GEC 1 528 #define CONFIG_SYS_NUM_FM2_10GEC 1
525 #define CONFIG_NUM_DDR_CONTROLLERS 2 529 #define CONFIG_NUM_DDR_CONTROLLERS 2
526 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 530 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
527 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 531 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
528 #define CONFIG_SYS_FSL_TBCLK_DIV 16 532 #define CONFIG_SYS_FSL_TBCLK_DIV 16
529 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 533 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
530 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 534 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
531 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 535 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
532 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 536 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
533 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 537 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
534 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 538 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
535 #define CONFIG_SYS_FSL_ERRATUM_USB14 539 #define CONFIG_SYS_FSL_ERRATUM_USB14
536 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 540 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
537 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 541 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
538 #define CONFIG_SYS_FSL_ERRATUM_A004699 542 #define CONFIG_SYS_FSL_ERRATUM_A004699
539 #define CONFIG_SYS_FSL_ERRATUM_A004510 543 #define CONFIG_SYS_FSL_ERRATUM_A004510
540 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 544 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
545 #define CONFIG_SYS_FSL_ERRATUM_A006261
541 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 546 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
542 #define CONFIG_SYS_FSL_ERRATUM_A005812 547 #define CONFIG_SYS_FSL_ERRATUM_A005812
543 548
544 #elif defined(CONFIG_BSC9131) 549 #elif defined(CONFIG_BSC9131)
545 #define CONFIG_MAX_CPUS 1 550 #define CONFIG_MAX_CPUS 1
546 #define CONFIG_FSL_SDHC_V2_3 551 #define CONFIG_FSL_SDHC_V2_3
547 #define CONFIG_SYS_FSL_NUM_LAWS 12 552 #define CONFIG_SYS_FSL_NUM_LAWS 12
548 #define CONFIG_TSECV2 553 #define CONFIG_TSECV2
549 #define CONFIG_SYS_FSL_SEC_COMPAT 4 554 #define CONFIG_SYS_FSL_SEC_COMPAT 4
550 #define CONFIG_NUM_DDR_CONTROLLERS 1 555 #define CONFIG_NUM_DDR_CONTROLLERS 1
551 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 556 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
552 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 557 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
553 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 558 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
554 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 559 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
555 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 560 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
556 #define CONFIG_NAND_FSL_IFC 561 #define CONFIG_NAND_FSL_IFC
557 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 562 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
558 #define CONFIG_SYS_FSL_ERRATUM_A005125 563 #define CONFIG_SYS_FSL_ERRATUM_A005125
559 #define CONFIG_ESDHC_HC_BLK_ADDR 564 #define CONFIG_ESDHC_HC_BLK_ADDR
560 565
561 #elif defined(CONFIG_BSC9132) 566 #elif defined(CONFIG_BSC9132)
562 #define CONFIG_MAX_CPUS 2 567 #define CONFIG_MAX_CPUS 2
563 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 568 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
564 #define CONFIG_FSL_SDHC_V2_3 569 #define CONFIG_FSL_SDHC_V2_3
565 #define CONFIG_SYS_FSL_NUM_LAWS 12 570 #define CONFIG_SYS_FSL_NUM_LAWS 12
566 #define CONFIG_TSECV2 571 #define CONFIG_TSECV2
567 #define CONFIG_SYS_FSL_SEC_COMPAT 4 572 #define CONFIG_SYS_FSL_SEC_COMPAT 4
568 #define CONFIG_NUM_DDR_CONTROLLERS 2 573 #define CONFIG_NUM_DDR_CONTROLLERS 2
569 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 574 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
570 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 575 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
571 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 576 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
572 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 577 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
573 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 578 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
574 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 579 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
575 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 580 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
576 #define CONFIG_NAND_FSL_IFC 581 #define CONFIG_NAND_FSL_IFC
577 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 582 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
578 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 583 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
579 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 584 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
580 #define CONFIG_SYS_FSL_ERRATUM_A005125 585 #define CONFIG_SYS_FSL_ERRATUM_A005125
581 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 586 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
582 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 587 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
583 #define CONFIG_ESDHC_HC_BLK_ADDR 588 #define CONFIG_ESDHC_HC_BLK_ADDR
584 589
585 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 590 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
586 #define CONFIG_E6500 591 #define CONFIG_E6500
587 #define CONFIG_SYS_PPC64 /* 64-bit core */ 592 #define CONFIG_SYS_PPC64 /* 64-bit core */
588 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 593 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
589 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 594 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
590 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 595 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
591 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 596 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
592 #ifdef CONFIG_PPC_T4240 597 #ifdef CONFIG_PPC_T4240
593 #define CONFIG_MAX_CPUS 12 598 #define CONFIG_MAX_CPUS 12
594 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 599 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
595 #define CONFIG_SYS_NUM_FM1_DTSEC 8 600 #define CONFIG_SYS_NUM_FM1_DTSEC 8
596 #define CONFIG_SYS_NUM_FM1_10GEC 2 601 #define CONFIG_SYS_NUM_FM1_10GEC 2
597 #define CONFIG_SYS_NUM_FM2_DTSEC 8 602 #define CONFIG_SYS_NUM_FM2_DTSEC 8
598 #define CONFIG_SYS_NUM_FM2_10GEC 2 603 #define CONFIG_SYS_NUM_FM2_10GEC 2
599 #define CONFIG_NUM_DDR_CONTROLLERS 3 604 #define CONFIG_NUM_DDR_CONTROLLERS 3
600 #else 605 #else
601 #define CONFIG_MAX_CPUS 8 606 #define CONFIG_MAX_CPUS 8
602 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 607 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
603 #define CONFIG_SYS_NUM_FM1_DTSEC 7 608 #define CONFIG_SYS_NUM_FM1_DTSEC 7
604 #define CONFIG_SYS_NUM_FM1_10GEC 1 609 #define CONFIG_SYS_NUM_FM1_10GEC 1
605 #define CONFIG_SYS_NUM_FM2_DTSEC 7 610 #define CONFIG_SYS_NUM_FM2_DTSEC 7
606 #define CONFIG_SYS_NUM_FM2_10GEC 1 611 #define CONFIG_SYS_NUM_FM2_10GEC 1
607 #define CONFIG_NUM_DDR_CONTROLLERS 2 612 #define CONFIG_NUM_DDR_CONTROLLERS 2
608 #endif 613 #endif
609 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 614 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
610 #define CONFIG_SYS_FSL_NUM_LAWS 32 615 #define CONFIG_SYS_FSL_NUM_LAWS 32
611 #define CONFIG_SYS_FSL_SRDS_1 616 #define CONFIG_SYS_FSL_SRDS_1
612 #define CONFIG_SYS_FSL_SRDS_2 617 #define CONFIG_SYS_FSL_SRDS_2
613 #define CONFIG_SYS_FSL_SRDS_3 618 #define CONFIG_SYS_FSL_SRDS_3
614 #define CONFIG_SYS_FSL_SRDS_4 619 #define CONFIG_SYS_FSL_SRDS_4
615 #define CONFIG_SYS_FSL_SEC_COMPAT 4 620 #define CONFIG_SYS_FSL_SEC_COMPAT 4
616 #define CONFIG_SYS_NUM_FMAN 2 621 #define CONFIG_SYS_NUM_FMAN 2
617 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 622 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
618 #define CONFIG_SYS_PME_CLK 0 623 #define CONFIG_SYS_PME_CLK 0
619 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 624 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
620 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 625 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
621 #define CONFIG_SYS_FMAN_V3 626 #define CONFIG_SYS_FMAN_V3
622 #define CONFIG_SYS_FM1_CLK 3 627 #define CONFIG_SYS_FM1_CLK 3
623 #define CONFIG_SYS_FM2_CLK 3 628 #define CONFIG_SYS_FM2_CLK 3
624 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 629 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
625 #define CONFIG_SYS_FSL_TBCLK_DIV 16 630 #define CONFIG_SYS_FSL_TBCLK_DIV 16
626 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 631 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
627 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 632 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
628 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 633 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
629 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 634 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
630 #define CONFIG_SYS_FSL_SRIO_LIODN 635 #define CONFIG_SYS_FSL_SRIO_LIODN
631 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 636 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
632 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 637 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
633 #define CONFIG_SYS_FSL_ERRATUM_A004468 638 #define CONFIG_SYS_FSL_ERRATUM_A004468
634 #define CONFIG_SYS_FSL_ERRATUM_A_004934 639 #define CONFIG_SYS_FSL_ERRATUM_A_004934
635 #define CONFIG_SYS_FSL_ERRATUM_A005871 640 #define CONFIG_SYS_FSL_ERRATUM_A005871
641 #define CONFIG_SYS_FSL_ERRATUM_A006261
636 #define CONFIG_SYS_FSL_ERRATUM_A006379 642 #define CONFIG_SYS_FSL_ERRATUM_A006379
637 #define CONFIG_SYS_FSL_ERRATUM_A006593 643 #define CONFIG_SYS_FSL_ERRATUM_A006593
638 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 644 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
639 #define CONFIG_SYS_FSL_PCI_VER_3_X 645 #define CONFIG_SYS_FSL_PCI_VER_3_X
640 646
641 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 647 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
642 #define CONFIG_E6500 648 #define CONFIG_E6500
643 #define CONFIG_SYS_PPC64 /* 64-bit core */ 649 #define CONFIG_SYS_PPC64 /* 64-bit core */
644 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 650 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
645 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 651 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
646 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 652 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
647 #define CONFIG_SYS_FSL_NUM_LAWS 32 653 #define CONFIG_SYS_FSL_NUM_LAWS 32
648 #define CONFIG_SYS_FSL_SRDS_1 654 #define CONFIG_SYS_FSL_SRDS_1
649 #define CONFIG_SYS_FSL_SRDS_2 655 #define CONFIG_SYS_FSL_SRDS_2
650 #define CONFIG_SYS_FSL_SEC_COMPAT 4 656 #define CONFIG_SYS_FSL_SEC_COMPAT 4
651 #define CONFIG_SYS_NUM_FMAN 1 657 #define CONFIG_SYS_NUM_FMAN 1
652 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 658 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
653 #define CONFIG_SYS_FM1_CLK 0 659 #define CONFIG_SYS_FM1_CLK 0
654 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 660 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
655 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 661 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
656 #define CONFIG_SYS_FMAN_V3 662 #define CONFIG_SYS_FMAN_V3
657 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 663 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
658 #define CONFIG_SYS_FSL_TBCLK_DIV 16 664 #define CONFIG_SYS_FSL_TBCLK_DIV 16
659 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 665 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
660 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 666 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
661 #define CONFIG_SYS_FSL_ERRATUM_A_004934 667 #define CONFIG_SYS_FSL_ERRATUM_A_004934
662 #define CONFIG_SYS_FSL_ERRATUM_A005871 668 #define CONFIG_SYS_FSL_ERRATUM_A005871
663 #define CONFIG_SYS_FSL_ERRATUM_A006379 669 #define CONFIG_SYS_FSL_ERRATUM_A006379
664 #define CONFIG_SYS_FSL_ERRATUM_A006593 670 #define CONFIG_SYS_FSL_ERRATUM_A006593
665 #define CONFIG_SYS_FSL_ERRATUM_A006475 671 #define CONFIG_SYS_FSL_ERRATUM_A006475
666 #define CONFIG_SYS_FSL_ERRATUM_A006384 672 #define CONFIG_SYS_FSL_ERRATUM_A006384
667 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 673 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
668 674
669 #ifdef CONFIG_PPC_B4860 675 #ifdef CONFIG_PPC_B4860
670 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
671 #define CONFIG_MAX_CPUS 4 677 #define CONFIG_MAX_CPUS 4
672 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 678 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
673 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 679 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
674 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 680 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
675 #define CONFIG_SYS_NUM_FM1_DTSEC 6 681 #define CONFIG_SYS_NUM_FM1_DTSEC 6
676 #define CONFIG_SYS_NUM_FM1_10GEC 2 682 #define CONFIG_SYS_NUM_FM1_10GEC 2
677 #define CONFIG_NUM_DDR_CONTROLLERS 2 683 #define CONFIG_NUM_DDR_CONTROLLERS 2
678 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 684 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
679 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 685 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
680 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 686 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
681 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 687 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
682 #define CONFIG_SYS_FSL_SRIO_LIODN 688 #define CONFIG_SYS_FSL_SRIO_LIODN
683 #else 689 #else
684 #define CONFIG_MAX_CPUS 2 690 #define CONFIG_MAX_CPUS 2
685 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 691 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
686 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 692 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
687 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 693 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
688 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 694 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
689 #define CONFIG_SYS_NUM_FM1_DTSEC 4 695 #define CONFIG_SYS_NUM_FM1_DTSEC 4
690 #define CONFIG_SYS_NUM_FM1_10GEC 0 696 #define CONFIG_SYS_NUM_FM1_10GEC 0
691 #define CONFIG_NUM_DDR_CONTROLLERS 1 697 #define CONFIG_NUM_DDR_CONTROLLERS 1
692 #endif 698 #endif
693 699
694 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 700 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
695 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 701 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
696 #define CONFIG_E5500 702 #define CONFIG_E5500
697 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 703 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
698 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 704 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
699 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 705 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
700 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 706 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
701 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 707 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
702 #define CONFIG_MAX_CPUS 4 708 #define CONFIG_MAX_CPUS 4
703 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 709 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
704 #define CONFIG_MAX_CPUS 2 710 #define CONFIG_MAX_CPUS 2
705 #endif 711 #endif
706 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 712 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
707 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 713 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
708 #define CONFIG_SYS_SDHC_CLOCK 0 714 #define CONFIG_SYS_SDHC_CLOCK 0
709 #define CONFIG_SYS_FSL_NUM_LAWS 16 715 #define CONFIG_SYS_FSL_NUM_LAWS 16
710 #define CONFIG_SYS_FSL_SRDS_1 716 #define CONFIG_SYS_FSL_SRDS_1
711 #define CONFIG_SYS_FSL_SEC_COMPAT 5 717 #define CONFIG_SYS_FSL_SEC_COMPAT 5
712 #define CONFIG_SYS_NUM_FMAN 1 718 #define CONFIG_SYS_NUM_FMAN 1
713 #define CONFIG_SYS_NUM_FM1_DTSEC 5 719 #define CONFIG_SYS_NUM_FM1_DTSEC 5
714 #define CONFIG_NUM_DDR_CONTROLLERS 1 720 #define CONFIG_NUM_DDR_CONTROLLERS 1
715 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 721 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
716 #define CONFIG_PME_PLAT_CLK_DIV 2 722 #define CONFIG_PME_PLAT_CLK_DIV 2
717 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 723 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
718 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 724 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
719 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 725 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
720 #define CONFIG_SYS_FMAN_V3 726 #define CONFIG_SYS_FMAN_V3
721 #define CONFIG_FM_PLAT_CLK_DIV 1 727 #define CONFIG_FM_PLAT_CLK_DIV 1
722 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 728 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
723 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 729 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
724 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 730 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
725 #define CONFIG_SYS_FSL_TBCLK_DIV 16 731 #define CONFIG_SYS_FSL_TBCLK_DIV 16
726 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 732 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
727 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 733 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
728 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 734 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
735 #define CONFIG_SYS_FSL_ERRATUM_A006261
729 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 736 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
730 737
731 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 738 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
732 #define CONFIG_E6500 739 #define CONFIG_E6500
733 #define CONFIG_SYS_PPC64 /* 64-bit core */ 740 #define CONFIG_SYS_PPC64 /* 64-bit core */
734 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 741 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
735 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 742 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
736 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 743 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
737 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 744 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
738 #define CONFIG_SYS_FSL_QMAN_V3 745 #define CONFIG_SYS_FSL_QMAN_V3
739 #define CONFIG_MAX_CPUS 4 746 #define CONFIG_MAX_CPUS 4
740 #define CONFIG_SYS_FSL_NUM_LAWS 32 747 #define CONFIG_SYS_FSL_NUM_LAWS 32
741 #define CONFIG_SYS_FSL_SEC_COMPAT 4 748 #define CONFIG_SYS_FSL_SEC_COMPAT 4
742 #define CONFIG_SYS_NUM_FMAN 1 749 #define CONFIG_SYS_NUM_FMAN 1
743 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 750 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
744 #define CONFIG_SYS_FSL_SRDS_1 751 #define CONFIG_SYS_FSL_SRDS_1
745 #define CONFIG_SYS_FSL_PCI_VER_3_X 752 #define CONFIG_SYS_FSL_PCI_VER_3_X
746 #if defined(CONFIG_PPC_T2080) 753 #if defined(CONFIG_PPC_T2080)
747 #define CONFIG_SYS_NUM_FM1_DTSEC 8 754 #define CONFIG_SYS_NUM_FM1_DTSEC 8
748 #define CONFIG_SYS_NUM_FM1_10GEC 4 755 #define CONFIG_SYS_NUM_FM1_10GEC 4
749 #define CONFIG_SYS_FSL_SRDS_2 756 #define CONFIG_SYS_FSL_SRDS_2
750 #define CONFIG_SYS_FSL_SRIO_LIODN 757 #define CONFIG_SYS_FSL_SRIO_LIODN
751 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 758 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
752 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 759 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
753 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 760 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
754 #elif defined(CONFIG_PPC_T2081) 761 #elif defined(CONFIG_PPC_T2081)
755 #define CONFIG_SYS_NUM_FM1_DTSEC 6 762 #define CONFIG_SYS_NUM_FM1_DTSEC 6
756 #define CONFIG_SYS_NUM_FM1_10GEC 2 763 #define CONFIG_SYS_NUM_FM1_10GEC 2
757 #endif 764 #endif
758 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 765 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
759 #define CONFIG_NUM_DDR_CONTROLLERS 1 766 #define CONFIG_NUM_DDR_CONTROLLERS 1
760 #define CONFIG_PME_PLAT_CLK_DIV 1 767 #define CONFIG_PME_PLAT_CLK_DIV 1
761 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 768 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
762 #define CONFIG_SYS_FM1_CLK 0 769 #define CONFIG_SYS_FM1_CLK 0
763 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 770 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
764 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 771 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
765 #define CONFIG_SYS_FMAN_V3 772 #define CONFIG_SYS_FMAN_V3
766 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 773 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
767 #define CONFIG_SYS_FSL_TBCLK_DIV 16 774 #define CONFIG_SYS_FSL_TBCLK_DIV 16
768 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 775 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
769 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 776 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
770 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 777 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
771 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 778 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
772 #define CONFIG_SYS_FSL_SFP_VER_3_0 779 #define CONFIG_SYS_FSL_SFP_VER_3_0
773 #define CONFIG_SYS_FSL_ISBC_VER 2 780 #define CONFIG_SYS_FSL_ISBC_VER 2
774 781
775 #elif defined(CONFIG_PPC_C29X) 782 #elif defined(CONFIG_PPC_C29X)
776 #define CONFIG_MAX_CPUS 1 783 #define CONFIG_MAX_CPUS 1
777 #define CONFIG_FSL_SDHC_V2_3 784 #define CONFIG_FSL_SDHC_V2_3
778 #define CONFIG_SYS_FSL_NUM_LAWS 12 785 #define CONFIG_SYS_FSL_NUM_LAWS 12
779 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 786 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
780 #define CONFIG_TSECV2_1 787 #define CONFIG_TSECV2_1
781 #define CONFIG_SYS_FSL_SEC_COMPAT 6 788 #define CONFIG_SYS_FSL_SEC_COMPAT 6
782 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 789 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
783 #define CONFIG_NUM_DDR_CONTROLLERS 1 790 #define CONFIG_NUM_DDR_CONTROLLERS 1
784 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 791 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
785 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 792 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
786 #define CONFIG_SYS_FSL_ERRATUM_A005125 793 #define CONFIG_SYS_FSL_ERRATUM_A005125
787 794
788 #else 795 #else
789 #error Processor type not defined for this platform 796 #error Processor type not defined for this platform
790 #endif 797 #endif
791 798
792 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 799 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
793 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 800 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
794 #endif 801 #endif
795 802
796 #ifdef CONFIG_E6500 803 #ifdef CONFIG_E6500
797 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 804 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
798 #else 805 #else
799 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 806 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
800 #endif 807 #endif
801 808
802 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 809 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
803 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 810 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
804 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 811 !defined(CONFIG_SYS_FSL_DDRC_GEN3)
805 #define CONFIG_SYS_FSL_DDRC_GEN3 812 #define CONFIG_SYS_FSL_DDRC_GEN3
806 #endif 813 #endif
807 814
808 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 815 #endif /* _ASM_MPC85xx_CONFIG_H_ */
809 816
arch/powerpc/include/asm/fsl_errata.h
Diff comments   View file @ 9c641a8
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _ASM_FSL_ERRATA_H 7 #ifndef _ASM_FSL_ERRATA_H
8 #define _ASM_FSL_ERRATA_H 8 #define _ASM_FSL_ERRATA_H
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 12
13 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 13 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
14 static inline bool has_erratum_a006379(void) 14 static inline bool has_erratum_a006379(void)
15 { 15 {
16 u32 svr = get_svr(); 16 u32 svr = get_svr();
17 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || 17 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
18 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || 18 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
19 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || 19 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
20 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || 20 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
21 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || 21 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
22 ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) 22 ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
23 return true; 23 return true;
24 24
25 return false; 25 return false;
26 } 26 }
27 #endif 27 #endif
28 28
29 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
30 static inline bool has_erratum_a006261(void)
31 {
32 u32 svr = get_svr();
33 u32 soc = SVR_SOC_VER(svr);
34
35 switch (soc) {
36 case SVR_P1010:
37 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
38 case SVR_P2041:
39 case SVR_P2040:
40 return IS_SVR_REV(svr, 1, 0) ||
41 IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
42 case SVR_P3041:
43 return IS_SVR_REV(svr, 1, 0) ||
44 IS_SVR_REV(svr, 1, 1) ||
45 IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
46 case SVR_P5010:
47 case SVR_P5020:
48 case SVR_P5021:
49 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
50 case SVR_T4240:
51 case SVR_T4160:
52 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
53 case SVR_T1040:
54 return IS_SVR_REV(svr, 1, 0);
55 case SVR_P5040:
56 return IS_SVR_REV(svr, 1, 0);
57 }
58
59 return false;
60 }
61 #endif
62
29 #endif 63 #endif
30 64
1 /* 1 /*
2 * Freescale USB Controller 2 * Freescale USB Controller
3 * 3 *
4 * Copyright 2013 Freescale Semiconductor, Inc. 4 * Copyright 2013 Freescale Semiconductor, Inc.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef _ASM_FSL_USB_H_ 9 #ifndef _ASM_FSL_USB_H_
10 #define _ASM_FSL_USB_H_ 10 #define _ASM_FSL_USB_H_
11 11
12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
13 struct ccsr_usb_port_ctrl { 13 struct ccsr_usb_port_ctrl {
14 u32 ctrl; 14 u32 ctrl;
15 u32 drvvbuscfg; 15 u32 drvvbuscfg;
16 u32 pwrfltcfg; 16 u32 pwrfltcfg;
17 u32 sts; 17 u32 sts;
18 u8 res_14[0xc]; 18 u8 res_14[0xc];
19 u32 bistcfg; 19 u32 bistcfg;
20 u32 biststs; 20 u32 biststs;
21 u32 abistcfg; 21 u32 abistcfg;
22 u32 abiststs; 22 u32 abiststs;
23 u8 res_30[0x10]; 23 u8 res_30[0x10];
24 u32 xcvrprg; 24 u32 xcvrprg;
25 u32 anaprg; 25 u32 anaprg;
26 u32 anadrv; 26 u32 anadrv;
27 u32 anasts; 27 u32 anasts;
28 }; 28 };
29 29
30 struct ccsr_usb_phy { 30 struct ccsr_usb_phy {
31 u32 id; 31 u32 id;
32 struct ccsr_usb_port_ctrl port1; 32 struct ccsr_usb_port_ctrl port1;
33 u8 res_50[0xc]; 33 u8 res_50[0xc];
34 u32 tvr; 34 u32 tvr;
35 u32 pllprg[4]; 35 u32 pllprg[4];
36 u8 res_70[0x4]; 36 u8 res_70[0x4];
37 u32 anaccfg; 37 u32 anaccfg;
38 u32 dbg; 38 u32 dbg;
39 u8 res_7c[0x4]; 39 u8 res_7c[0x4];
40 struct ccsr_usb_port_ctrl port2; 40 struct ccsr_usb_port_ctrl port2;
41 u8 res_dc[0x334]; 41 u8 res_dc[0x334];
42 }; 42 };
43 43
44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) 44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) 45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) 46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) 47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) 48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) 49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) 50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) 51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) 52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) 53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) 54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
55 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
56 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
57
58 #define INC_DCNT_THRESHOLD_25MV (0 << 4)
59 #define INC_DCNT_THRESHOLD_50MV (1 << 4)
60 #define DEC_DCNT_THRESHOLD_25MV (2 << 4)
61 #define DEC_DCNT_THRESHOLD_50MV (3 << 4)
55 #else 62 #else
56 struct ccsr_usb_phy { 63 struct ccsr_usb_phy {
57 u8 res0[0x18]; 64 u32 config1;
65 u32 config2;
66 u32 config3;
67 u32 config4;
68 u32 config5;
69 u32 status1;
58 u32 usb_enable_override; 70 u32 usb_enable_override;
59 u8 res[0xe4]; 71 u8 res[0xe4];
60 }; 72 };
61 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 73 #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
74 #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
75 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
76 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
77 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
78 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
79 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
80 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
62 #endif 81 #endif
63 82
64 #endif /*_ASM_FSL_USB_H_ */ 83 #endif /*_ASM_FSL_USB_H_ */
65 84