powerpc/usb: Workaround for erratum-A006261

USB spec says that the minimum disconnect threshold should be over 525 mV. However, internal USB PHY threshold value is below this specified value. Due to this some devices disconnect at run-time. Hence, phy settings are tweaked to increased disconnect threshold to be above 525mV by using this workaround. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

powerpc/usb: Workaround for erratum-A006261
USB spec says that the minimum disconnect threshold should be over 525 mV. However, internal USB PHY threshold value is below this specified value. Due to this some devices disconnect at run-time. Hence, phy settings are tweaked to increased disconnect threshold to be above 525mV by using this workaround. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Suresh Gupta · York Sun
1 parent 7af9a07403
Showing 5 changed files with 128 additions and 2 deletions Side-by-side Diff
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_errata.h
include/fsl_usb.h
@@ -273,6 +273,10 @@
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
 		puts("Work-around for Erratum I2C-A004447 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+	if (has_erratum_a006261())
+		puts("Work-around for Erratum A006261 enabled\n");
+#endif
 	return 0;
 }
  
@@ -36,6 +36,54 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+	u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
+
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
+
+	xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
+#else
+
+	u32 temp = 0;
+	u32 status = in_be32(&usb_phy->status1);
+
+	u32 squelch_prog_rd_0_2 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	u32 squelch_prog_rd_3_5 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	setbits_be32(&usb_phy->config1,
+		     CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+	setbits_be32(&usb_phy->config2,
+		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+
+	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+#endif
+}
+#endif
+
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -625,6 +673,10 @@
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy1);
+#endif
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
@@ -633,6 +685,10 @@
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy2);
+#endif
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
  
@@ -672,7 +728,13 @@
 			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port2.pwrfltcfg,
 			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy);
 #endif
+
+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
  
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
@@ -154,6 +154,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
 #define CONFIG_ESDHC_HC_BLK_ADDR
  
@@ -386,6 +387,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
  
 #elif defined(CONFIG_PPC_P3041)
@@ -424,6 +426,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
  
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
@@ -507,6 +510,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
  
 #elif defined(CONFIG_PPC_P5040)
@@ -538,6 +542,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004699
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
  
@@ -633,6 +638,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
@@ -726,6 +732,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
  
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
@@ -26,5 +26,39 @@
 }
 #endif
  
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+static inline bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+	}
+
+	return false;
+}
+#endif
+
 #endif
@@ -52,13 +52,32 @@
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
 #else
 struct ccsr_usb_phy {
-	u8	res0[0x18];
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
 	u32	usb_enable_override;
 	u8	res[0xe4];
 };
-#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
  
 #endif /*_ASM_FSL_USB_H_ */
...	...	@@ -273,6 +273,10 @@
273	273	(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
274	274	puts("Work-around for Erratum I2C-A004447 enabled\n");
275	275	#endif
	276	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	277	+ if (has_erratum_a006261())
	278	+ puts("Work-around for Erratum A006261 enabled\n");
	279	+#endif
276	280	return 0;
277	281	}
278	282
...	...	@@ -36,6 +36,54 @@
36	36
37	37	DECLARE_GLOBAL_DATA_PTR;
38	38
	39	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	40	+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
	41	+{
	42	+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
	43	+ u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
	44	+
	45	+ /* Increase Disconnect Threshold by 50mV */
	46	+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK \|
	47	+ INC_DCNT_THRESHOLD_50MV;
	48	+ /* Enable programming of USB High speed Disconnect threshold */
	49	+ xcvrprg \|= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
	50	+ out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
	51	+
	52	+ xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
	53	+ /* Increase Disconnect Threshold by 50mV */
	54	+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK \|
	55	+ INC_DCNT_THRESHOLD_50MV;
	56	+ /* Enable programming of USB High speed Disconnect threshold */
	57	+ xcvrprg \|= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
	58	+ out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
	59	+#else
	60	+
	61	+ u32 temp = 0;
	62	+ u32 status = in_be32(&usb_phy->status1);
	63	+
	64	+ u32 squelch_prog_rd_0_2 =
	65	+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
	66	+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
	67	+
	68	+ u32 squelch_prog_rd_3_5 =
	69	+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
	70	+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
	71	+
	72	+ setbits_be32(&usb_phy->config1,
	73	+ CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
	74	+ setbits_be32(&usb_phy->config2,
	75	+ CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
	76	+
	77	+ temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
	78	+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) \| temp);
	79	+
	80	+ temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
	81	+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) \| temp);
	82	+#endif
	83	+}
	84	+#endif
	85	+
	86	+
39	87	#ifdef CONFIG_QE
40	88	extern qe_iop_conf_t qe_iop_conf_tab[];
41	89	extern void qe_config_iopin(u8 port, u8 pin, int dir,
...	...	@@ -625,6 +673,10 @@
625	673	{
626	674	struct ccsr_usb_phy __iomem *usb_phy1 =
627	675	(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
	676	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	677	+ if (has_erratum_a006261())
	678	+ fsl_erratum_a006261_workaround(usb_phy1);
	679	+#endif
628	680	out_be32(&usb_phy1->usb_enable_override,
629	681	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
630	682	}
...	...	@@ -633,6 +685,10 @@
633	685	{
634	686	struct ccsr_usb_phy __iomem *usb_phy2 =
635	687	(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
	688	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	689	+ if (has_erratum_a006261())
	690	+ fsl_erratum_a006261_workaround(usb_phy2);
	691	+#endif
636	692	out_be32(&usb_phy2->usb_enable_override,
637	693	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
638	694	}
639	695
...	...	@@ -672,7 +728,13 @@
672	728	CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
673	729	setbits_be32(&usb_phy->port2.pwrfltcfg,
674	730	CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
	731	+
	732	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	733	+ if (has_erratum_a006261())
	734	+ fsl_erratum_a006261_workaround(usb_phy);
675	735	#endif
	736	+
	737	+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
676	738
677	739	#ifdef CONFIG_FMAN_ENET
678	740	fman_enet_init();
...	...	@@ -154,6 +154,7 @@
154	154	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155	155	#define CONFIG_SYS_FSL_ERRATUM_A005125
156	156	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	157	+#define CONFIG_SYS_FSL_ERRATUM_A006261
157	158	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
158	159	#define CONFIG_ESDHC_HC_BLK_ADDR
159	160
...	...	@@ -386,6 +387,7 @@
386	387	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
387	388	#define CONFIG_SYS_FSL_ERRATUM_A004849
388	389	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	390	+#define CONFIG_SYS_FSL_ERRATUM_A006261
389	391	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
390	392
391	393	#elif defined(CONFIG_PPC_P3041)
...	...	@@ -424,6 +426,7 @@
424	426	#define CONFIG_SYS_FSL_ERRATUM_A004849
425	427	#define CONFIG_SYS_FSL_ERRATUM_A005812
426	428	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	429	+#define CONFIG_SYS_FSL_ERRATUM_A006261
427	430	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
428	431
429	432	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
...	...	@@ -507,6 +510,7 @@
507	510	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
508	511	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
509	512	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	513	+#define CONFIG_SYS_FSL_ERRATUM_A006261
510	514	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
511	515
512	516	#elif defined(CONFIG_PPC_P5040)
...	...	@@ -538,6 +542,7 @@
538	542	#define CONFIG_SYS_FSL_ERRATUM_A004699
539	543	#define CONFIG_SYS_FSL_ERRATUM_A004510
540	544	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
	545	+#define CONFIG_SYS_FSL_ERRATUM_A006261
541	546	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
542	547	#define CONFIG_SYS_FSL_ERRATUM_A005812
543	548
...	...	@@ -633,6 +638,7 @@
633	638	#define CONFIG_SYS_FSL_ERRATUM_A004468
634	639	#define CONFIG_SYS_FSL_ERRATUM_A_004934
635	640	#define CONFIG_SYS_FSL_ERRATUM_A005871
	641	+#define CONFIG_SYS_FSL_ERRATUM_A006261
636	642	#define CONFIG_SYS_FSL_ERRATUM_A006379
637	643	#define CONFIG_SYS_FSL_ERRATUM_A006593
638	644	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
...	...	@@ -726,6 +732,7 @@
726	732	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
727	733	#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
728	734	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	735	+#define CONFIG_SYS_FSL_ERRATUM_A006261
729	736	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
730	737
731	738	#elif defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
...	...	@@ -26,5 +26,39 @@
26	26	}
27	27	#endif
28	28
	29	+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
	30	+static inline bool has_erratum_a006261(void)
	31	+{
	32	+ u32 svr = get_svr();
	33	+ u32 soc = SVR_SOC_VER(svr);
	34	+
	35	+ switch (soc) {
	36	+ case SVR_P1010:
	37	+ return IS_SVR_REV(svr, 1, 0) \|\| IS_SVR_REV(svr, 2, 0);
	38	+ case SVR_P2041:
	39	+ case SVR_P2040:
	40	+ return IS_SVR_REV(svr, 1, 0) \|\|
	41	+ IS_SVR_REV(svr, 1, 1) \|\| IS_SVR_REV(svr, 2, 1);
	42	+ case SVR_P3041:
	43	+ return IS_SVR_REV(svr, 1, 0) \|\|
	44	+ IS_SVR_REV(svr, 1, 1) \|\|
	45	+ IS_SVR_REV(svr, 2, 0) \|\| IS_SVR_REV(svr, 2, 1);
	46	+ case SVR_P5010:
	47	+ case SVR_P5020:
	48	+ case SVR_P5021:
	49	+ return IS_SVR_REV(svr, 1, 0) \|\| IS_SVR_REV(svr, 2, 0);
	50	+ case SVR_T4240:
	51	+ case SVR_T4160:
	52	+ return IS_SVR_REV(svr, 1, 0) \|\| IS_SVR_REV(svr, 2, 0);
	53	+ case SVR_T1040:
	54	+ return IS_SVR_REV(svr, 1, 0);
	55	+ case SVR_P5040:
	56	+ return IS_SVR_REV(svr, 1, 0);
	57	+ }
	58	+
	59	+ return false;
	60	+}
	61	+#endif
	62	+
29	63	#endif
...	...	@@ -52,13 +52,32 @@
52	52	#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
53	53	#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
54	54	#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
	55	+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
	56	+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
	57	+
	58	+#define INC_DCNT_THRESHOLD_25MV (0 << 4)
	59	+#define INC_DCNT_THRESHOLD_50MV (1 << 4)
	60	+#define DEC_DCNT_THRESHOLD_25MV (2 << 4)
	61	+#define DEC_DCNT_THRESHOLD_50MV (3 << 4)
55	62	#else
56	63	struct ccsr_usb_phy {
57		- u8 res0[0x18];
	64	+ u32 config1;
	65	+ u32 config2;
	66	+ u32 config3;
	67	+ u32 config4;
	68	+ u32 config5;
	69	+ u32 status1;
58	70	u32 usb_enable_override;
59	71	u8 res[0xe4];
60	72	};
61		-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
	73	+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
	74	+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
	75	+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
	76	+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
	77	+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
	78	+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
	79	+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
	80	+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
62	81	#endif
63	82
64	83	#endif /_ASM_FSL_USB_H_ /