arm: kirkwood: fix kirkwood initial setup

Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>

arm: kirkwood: fix kirkwood initial setup
Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
Walter Schweizer · Stefan Roese
1 parent 0c3a2d9492
Showing 1 changed file with 16 additions and 11 deletions Side-by-side Diff
board/Synology/ds109/kwbimage.cfg
@@ -19,8 +19,11 @@
 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  
 # Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b9b9b
+DATA 0xFFD100e0 0x1b1b1b9b
  
+DATA 0xFFD20134 0xbbbbbbbb
+DATA 0xFFD20138 0x00bbbbbb
+
 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
 DATA 0xFFD01400 0x43000c30	# DDR Configuration register
 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
@@ -30,7 +33,7 @@
 # bit29-26: zero
 # bit31-30: 01
  
-DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
 # bit 4:    0=addr/cmd in smame cycle
 # bit 5:    0=clk is driven during self refresh, we don't care for APX
 # bit 6:    0=use recommended falling edge of clk for addr/cmd
  
@@ -52,14 +55,14 @@
 # bit27-24: TRRD
 # bit31-28: TRTP
  
-DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
 # bit6-0:   TRFC
 # bit8-7:   TR2R
 # bit10-9:  TR2W
 # bit12-11: TW2W
 # bit31-13: zero required
  
-DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
 # bit1-0:   01, Cs0width=x8
 # bit3-2:   10, Cs0size=1Gb
 # bit5-4:   01, Cs1width=x8
@@ -92,7 +95,7 @@
 # bit12:    0, PD must be zero
 # bit31-13: 0 required
  
-DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
 # bit0:    0,  DDR DLL enabled
 # bit1:    0,  DDR drive strenght normal
 # bit2:    0,  DDR ODT control lsd (disabled)
@@ -104,7 +107,7 @@
 # bit12:   0, DDR output buffer enabled
 # bit31-13: 0 required
  
-DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+DATA 0xFFD01424 0x0000F1FF	#  DDR Controller Control High
 # bit2-0:  111, required
 # bit3  :  1  , MBUS Burst Chop disabled
 # bit6-4:  111, required
  
  
  
  
  
  
@@ -120,26 +123,28 @@
 DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
  
 DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
 # bit0:    1,  Window enabled
 # bit1:    0,  Write Protect disabled
 # bit3-2:  00, CS0 hit selected
 # bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
+# bit31-24: 0x07, Size (i.e. 128MB)
  
 DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
  
+DATA 0xFFD01510 0x20000000	# CS[2]n Base address to 256Mb
 DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD01518 0x30000000	# CS[3]n Base address to 256Mb
 DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
  
-DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01494 0x003C0000	#  DDR ODT Control (Low)
 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
 # bit3-2:  01, ODT1 active NEVER!
 # bit31-4: zero, required
  
-DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD0149C 0x0000F80F	# CPU ODT Control
 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
 #bit0=1, enable DDR init upon this register write
...	...	@@ -19,8 +19,11 @@
19	19	# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
20	20
21	21	# Configure RGMII-0/1 interface pad voltage to 1.8V
22		-DATA 0xFFD100e0 0x1b1b9b9b
	22	+DATA 0xFFD100e0 0x1b1b1b9b
23	23
	24	+DATA 0xFFD20134 0xbbbbbbbb
	25	+DATA 0xFFD20138 0x00bbbbbb
	26	+
24	27	#Dram initalization for SINGLE x16 CL=5 @ 400MHz
25	28	DATA 0xFFD01400 0x43000c30 # DDR Configuration register
26	29	# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
...	...	@@ -30,7 +33,7 @@
30	33	# bit29-26: zero
31	34	# bit31-30: 01
32	35
33		-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
	36	+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
34	37	# bit 4: 0=addr/cmd in smame cycle
35	38	# bit 5: 0=clk is driven during self refresh, we don't care for APX
36	39	# bit 6: 0=use recommended falling edge of clk for addr/cmd
37	40
...	...	@@ -52,14 +55,14 @@
52	55	# bit27-24: TRRD
53	56	# bit31-28: TRTP
54	57
55		-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
	58	+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
56	59	# bit6-0: TRFC
57	60	# bit8-7: TR2R
58	61	# bit10-9: TR2W
59	62	# bit12-11: TW2W
60	63	# bit31-13: zero required
61	64
62		-DATA 0xFFD01410 0x000000cc # DDR Address Control
	65	+DATA 0xFFD01410 0x0000000d # DDR Address Control
63	66	# bit1-0: 01, Cs0width=x8
64	67	# bit3-2: 10, Cs0size=1Gb
65	68	# bit5-4: 01, Cs1width=x8
...	...	@@ -92,7 +95,7 @@
92	95	# bit12: 0, PD must be zero
93	96	# bit31-13: 0 required
94	97
95		-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
	98	+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
96	99	# bit0: 0, DDR DLL enabled
97	100	# bit1: 0, DDR drive strenght normal
98	101	# bit2: 0, DDR ODT control lsd (disabled)
...	...	@@ -104,7 +107,7 @@
104	107	# bit12: 0, DDR output buffer enabled
105	108	# bit31-13: 0 required
106	109
107		-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
	110	+DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
108	111	# bit2-0: 111, required
109	112	# bit3 : 1 , MBUS Burst Chop disabled
110	113	# bit6-4: 111, required
111	114
112	115
113	116
114	117
115	118
116	119
...	...	@@ -120,26 +123,28 @@
120	123	DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
121	124
122	125	DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
123		-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
	126	+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
124	127	# bit0: 1, Window enabled
125	128	# bit1: 0, Write Protect disabled
126	129	# bit3-2: 00, CS0 hit selected
127	130	# bit23-4: ones, required
128		-# bit31-24: 0x0F, Size (i.e. 256MB)
	131	+# bit31-24: 0x07, Size (i.e. 128MB)
129	132
130	133	DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
131		-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
	134	+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
132	135
	136	+DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
133	137	DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
	138	+DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
134	139	DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
135	140
136		-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
	141	+DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
137	142	DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
138	143	# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
139	144	# bit3-2: 01, ODT1 active NEVER!
140	145	# bit31-4: zero, required
141	146
142		-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
	147	+DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
143	148	DATA 0xFFD01480 0x00000001 # DDR Initialization Control
144	149	#bit0=1, enable DDR init upon this register write
145	150