p1014rdb: set ddr bus width properly depending on SVR

Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>

p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock · Andy Fleming
1 parent be7bebeac2
Showing 2 changed files with 12 additions and 0 deletions Side-by-side Diff
arch/powerpc/include/asm/fsl_ddr_sdram.h
nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -88,6 +88,7 @@
 #define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_DBW_MASK		0x00180000
 #define SDRAM_CFG_32_BE			0x00080000
 #define SDRAM_CFG_16_BE			0x00100000
 #define SDRAM_CFG_8_BE			0x00040000
@@ -35,6 +35,7 @@
 void sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	u32 svr = mfspr(SPRN_SVR);
  
 	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
 	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
@@ -69,6 +70,16 @@
 	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
 	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
 	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+
+	/* P1014 and it's derivatives support max 16bit DDR width */
+	if (svr == SVR_P1014) {
+		__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
+		__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
+		/* For CS0_BNDS we divide the start and end address by 2, so we can just
+		 * shift the entire register to achieve the desired result and the mask
+		 * the value so we don't write reserved fields */
+		__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
+	}
  
 	/* mimic 500us delay, with busy isync() loop */
 	udelay(100);
...	...	@@ -88,6 +88,7 @@
88	88	#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
89	89	#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
90	90	#define SDRAM_CFG_DYN_PWR 0x00200000
	91	+#define SDRAM_CFG_DBW_MASK 0x00180000
91	92	#define SDRAM_CFG_32_BE 0x00080000
92	93	#define SDRAM_CFG_16_BE 0x00100000
93	94	#define SDRAM_CFG_8_BE 0x00040000
...	...	@@ -35,6 +35,7 @@
35	35	void sdram_init(void)
36	36	{
37	37	ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC85xx_DDR_ADDR;
	38	+ u32 svr = mfspr(SPRN_SVR);
38	39
39	40	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL \| SDRAM_CFG_32_BE);
40	41	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
...	...	@@ -69,6 +70,16 @@
69	70	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
70	71	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
71	72	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
	73	+
	74	+ /* P1014 and it's derivatives support max 16bit DDR width */
	75	+ if (svr == SVR_P1014) {
	76	+ __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
	77	+ __raw_writel(ddr->sdram_cfg \| SDRAM_CFG_16_BE, &ddr->sdram_cfg);
	78	+ /* For CS0_BNDS we divide the start and end address by 2, so we can just
	79	+ * shift the entire register to achieve the desired result and the mask
	80	+ * the value so we don't write reserved fields */
	81	+ __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
	82	+ }
72	83
73	84	/* mimic 500us delay, with busy isync() loop */
74	85	udelay(100);