arm: mvebu: Add basic Armada 38x support

This patch adds support for the Marvell Armada 38x SoC family. Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash) Tested on Marvell DB-88F6820-GP evaluation board. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>

arm: mvebu: Add basic Armada 38x support
This patch adds support for the Marvell Armada 38x SoC family. Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash) Tested on Marvell DB-88F6820-GP evaluation board. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Stefan Roese · Luka Perkov
1 parent 880b15a37b
Showing 3 changed files with 73 additions and 16 deletions Side-by-side Diff
arch/arm/mach-mvebu/cpu.c
arch/arm/mach-mvebu/include/mach/cpu.h
arch/arm/mach-mvebu/include/mach/soc.h
 /*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -40,6 +40,20 @@
 		;
 }
  
+int mvebu_soc_family(void)
+{
+	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+
+	if (devid == SOC_MV78460_ID)
+		return MVEBU_SOC_AXP;
+
+	if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+	    devid == SOC_88F6828_ID)
+		return MVEBU_SOC_A38X;
+
+	return MVEBU_SOC_UNKNOWN;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
  
  
  
  
@@ -52,23 +66,48 @@
 	case SOC_MV78460_ID:
 		puts("MV78460-");
 		break;
-	default:
-		puts("Unknown-");
+	case SOC_88F6810_ID:
+		puts("MV88F6810-");
 		break;
-	}
-
-	switch (revid) {
-	case 1:
-		puts("A0\n");
+	case SOC_88F6820_ID:
+		puts("MV88F6820-");
 		break;
-	case 2:
-		puts("B0\n");
+	case SOC_88F6828_ID:
+		puts("MV88F6828-");
 		break;
 	default:
-		puts("??\n");
+		puts("Unknown-");
 		break;
 	}
  
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+		switch (revid) {
+		case 1:
+			puts("A0\n");
+			break;
+		case 2:
+			puts("B0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
+	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+		switch (revid) {
+		case MV_88F68XX_Z1_ID:
+			puts("Z1\n");
+			break;
+		case MV_88F68XX_A0_ID:
+			puts("A0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -145,11 +184,13 @@
 	 */
 	mvebu_mbus_probe(NULL, 0);
  
-	/*
-	 * Now the SDRAM access windows can be reconfigured using
-	 * the information in the SDRAM scratch pad registers
-	 */
-	update_sdram_window_sizes();
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+		/*
+		 * Now the SDRAM access windows can be reconfigured using
+		 * the information in the SDRAM scratch pad registers
+		 */
+		update_sdram_window_sizes();
+	}
  
 	/*
 	 * Finally the mbus windows can be configured with the
@@ -56,6 +56,12 @@
 	CPU_ATTR_DEV_CS3 = 0x37,
 };
  
+enum {
+	MVEBU_SOC_AXP,
+	MVEBU_SOC_A38X,
+	MVEBU_SOC_UNKNOWN,
+};
+
 /*
  * Default Device Address MAP BAR values
  */
@@ -106,6 +112,7 @@
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
  
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
@@ -12,7 +12,14 @@
 #define _MVEBU_SOC_H
  
 #define SOC_MV78460_ID		0x7846
+#define SOC_88F6810_ID		0x6810
+#define SOC_88F6820_ID		0x6820
+#define SOC_88F6828_ID		0x6828
  
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID	0x0
+#define MV_88F68XX_A0_ID	0x4
+
 /* TCLK Core Clock definition */
 #ifndef CONFIG_SYS_TCLK
 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
@@ -25,6 +32,8 @@
 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
  
 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
 #define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
1	1	/*
2		- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
	2	+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
3	3	*
4	4	* SPDX-License-Identifier: GPL-2.0+
5	5	*/
...	...	@@ -40,6 +40,20 @@
40	40	;
41	41	}
42	42
	43	+int mvebu_soc_family(void)
	44	+{
	45	+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
	46	+
	47	+ if (devid == SOC_MV78460_ID)
	48	+ return MVEBU_SOC_AXP;
	49	+
	50	+ if (devid == SOC_88F6810_ID \|\| devid == SOC_88F6820_ID \|\|
	51	+ devid == SOC_88F6828_ID)
	52	+ return MVEBU_SOC_A38X;
	53	+
	54	+ return MVEBU_SOC_UNKNOWN;
	55	+}
	56	+
43	57	#if defined(CONFIG_DISPLAY_CPUINFO)
44	58	int print_cpuinfo(void)
45	59	{
46	60
47	61
48	62
49	63
...	...	@@ -52,23 +66,48 @@
52	66	case SOC_MV78460_ID:
53	67	puts("MV78460-");
54	68	break;
55		- default:
56		- puts("Unknown-");
	69	+ case SOC_88F6810_ID:
	70	+ puts("MV88F6810-");
57	71	break;
58		- }
59		-
60		- switch (revid) {
61		- case 1:
62		- puts("A0\n");
	72	+ case SOC_88F6820_ID:
	73	+ puts("MV88F6820-");
63	74	break;
64		- case 2:
65		- puts("B0\n");
	75	+ case SOC_88F6828_ID:
	76	+ puts("MV88F6828-");
66	77	break;
67	78	default:
68		- puts("??\n");
	79	+ puts("Unknown-");
69	80	break;
70	81	}
71	82
	83	+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
	84	+ switch (revid) {
	85	+ case 1:
	86	+ puts("A0\n");
	87	+ break;
	88	+ case 2:
	89	+ puts("B0\n");
	90	+ break;
	91	+ default:
	92	+ printf("?? (%x)\n", revid);
	93	+ break;
	94	+ }
	95	+ }
	96	+
	97	+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
	98	+ switch (revid) {
	99	+ case MV_88F68XX_Z1_ID:
	100	+ puts("Z1\n");
	101	+ break;
	102	+ case MV_88F68XX_A0_ID:
	103	+ puts("A0\n");
	104	+ break;
	105	+ default:
	106	+ printf("?? (%x)\n", revid);
	107	+ break;
	108	+ }
	109	+ }
	110	+
72	111	return 0;
73	112	}
74	113	#endif /* CONFIG_DISPLAY_CPUINFO */
...	...	@@ -145,11 +184,13 @@
145	184	*/
146	185	mvebu_mbus_probe(NULL, 0);
147	186
148		- /*
149		- * Now the SDRAM access windows can be reconfigured using
150		- * the information in the SDRAM scratch pad registers
151		- */
152		- update_sdram_window_sizes();
	187	+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
	188	+ /*
	189	+ * Now the SDRAM access windows can be reconfigured using
	190	+ * the information in the SDRAM scratch pad registers
	191	+ */
	192	+ update_sdram_window_sizes();
	193	+ }
153	194
154	195	/*
155	196	* Finally the mbus windows can be configured with the
...	...	@@ -56,6 +56,12 @@
56	56	CPU_ATTR_DEV_CS3 = 0x37,
57	57	};
58	58
	59	+enum {
	60	+ MVEBU_SOC_AXP,
	61	+ MVEBU_SOC_A38X,
	62	+ MVEBU_SOC_UNKNOWN,
	63	+};
	64	+
59	65	/*
60	66	* Default Device Address MAP BAR values
61	67	*/
...	...	@@ -106,6 +112,7 @@
106	112	unsigned int mvebu_sdram_bs(enum memory_bank bank);
107	113	void mvebu_sdram_size_adjust(enum memory_bank bank);
108	114	int mvebu_mbus_probe(struct mbus_win windows[], int count);
	115	+int mvebu_soc_family(void);
109	116
110	117	/*
111	118	* Highspeed SERDES PHY config init, ported from bin_hdr
...	...	@@ -12,7 +12,14 @@
12	12	#define _MVEBU_SOC_H
13	13
14	14	#define SOC_MV78460_ID 0x7846
	15	+#define SOC_88F6810_ID 0x6810
	16	+#define SOC_88F6820_ID 0x6820
	17	+#define SOC_88F6828_ID 0x6828
15	18
	19	+/* A38x revisions */
	20	+#define MV_88F68XX_Z1_ID 0x0
	21	+#define MV_88F68XX_A0_ID 0x4
	22	+
16	23	/* TCLK Core Clock definition */
17	24	#ifndef CONFIG_SYS_TCLK
18	25	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
...	...	@@ -25,6 +32,8 @@
25	32	#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
26	33
27	34	#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
	35	+#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
	36	+#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
28	37	#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
29	38	#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
30	39	#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))