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Commit 9d0c2ceb35be7016977560a92fc67e3e704e5c9f

Authored by Masahiro Yamada
1 parent 881aa5a79a
Exists in v2017.01-smarct4x and in 29 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: uniphier: add PH1-LD20 SoC support 

This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 37 changed files with 956 additions and 10 deletions Side-by-side Diff

arch/arm/mach-uniphier/Kconfig
Diff comments   View file @ 9d0c2ce
... ... @@ -23,6 +23,11 @@
23 23 bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
24 24 select CPU_V7
25 25  
  26 +config ARCH_UNIPHIER_LD20
  27 + bool "UniPhier PH1-LD20 SoC"
  28 + select ARM64
  29 + select SPL_SEPARATE_BSS
  30 +
26 31 endchoice
27 32  
28 33 config ARCH_UNIPHIER_LD4
arch/arm/mach-uniphier/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -31,4 +31,5 @@
31 31 obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
32 32  
33 33 obj-$(CONFIG_CPU_V7) += arm32/
  34 +obj-$(CONFIG_ARM64) += arm64/
arch/arm/mach-uniphier/arm64/Makefile
Diff comments   View file @ 9d0c2ce
  1 +#
  2 +# SPDX-License-Identifier: GPL-2.0+
  3 +#
  4 +
  5 +ifdef CONFIG_SPL_BUILD
  6 +obj-y += timer.o
  7 +else
  8 +obj-y += mem_map.o smp.o smp_kick_cpus.o
  9 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
  10 +endif
arch/arm/mach-uniphier/arm64/arm-cci500.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
  3 + *
  4 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <mapmem.h>
  11 +#include <linux/bitops.h>
  12 +#include <linux/io.h>
  13 +#include <linux/sizes.h>
  14 +
  15 +#define CCI500_BASE 0x5FD00000
  16 +#define CCI500_SLAVE_OFFSET 0x1000
  17 +
  18 +#define CCI500_SNOOP_CTRL
  19 +#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
  20 +#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
  21 +
  22 +void cci500_init(unsigned int nr_slaves)
  23 +{
  24 + unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
  25 + int i;
  26 +
  27 + for (i = 0; i < nr_slaves; i++) {
  28 + void __iomem *base;
  29 + u32 tmp;
  30 +
  31 + base = map_sysmem(slave_base, SZ_4K);
  32 +
  33 + tmp = readl(base);
  34 + tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
  35 + writel(tmp, base);
  36 +
  37 + unmap_sysmem(base);
  38 +
  39 + slave_base += CCI500_SLAVE_OFFSET;
  40 + }
  41 +}
arch/arm/mach-uniphier/arm64/mem_map.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <linux/types.h>
  9 +#include <asm/armv8/mmu.h>
  10 +
  11 +static struct mm_region uniphier_mem_map[] = {
  12 + {
  13 + .base = 0x00000000,
  14 + .size = 0x80000000,
  15 + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  16 + PTE_BLOCK_NON_SHARE |
  17 + PTE_BLOCK_PXN | PTE_BLOCK_UXN
  18 + },
  19 + {
  20 + .base = 0x80000000,
  21 + .size = 0xc0000000,
  22 + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  23 + PTE_BLOCK_INNER_SHARE
  24 + },
  25 + { /* sentinel */ }
  26 +};
  27 +
  28 +struct mm_region *mem_map = uniphier_mem_map;
arch/arm/mach-uniphier/arm64/smp.S
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <linux/linkage.h>
  8 +
  9 +ENTRY(uniphier_smp_setup)
  10 + mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */
  11 + orr x0, x0, #(1 << 6) /* SMPEN */
  12 + msr s3_1_c15_c2_1, x0
  13 + ret
  14 +ENDPROC(uniphier_smp_setup)
  15 +
  16 +ENTRY(uniphier_secondary_startup)
  17 + bl uniphier_smp_setup
  18 + b _start
  19 +ENDPROC(uniphier_secondary_startup)
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <mapmem.h>
  9 +#include <linux/io.h>
  10 +#include <linux/sizes.h>
  11 +
  12 +#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
  13 +
  14 +void uniphier_smp_setup(void);
  15 +void uniphier_secondary_startup(void);
  16 +
  17 +void uniphier_smp_kick_all_cpus(void)
  18 +{
  19 + void __iomem *rom_boot_rsv0;
  20 +
  21 + rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
  22 +
  23 + writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
  24 + readq(rom_boot_rsv0); /* relax */
  25 +
  26 + unmap_sysmem(rom_boot_rsv0);
  27 +
  28 + uniphier_smp_setup();
  29 +
  30 + asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
  31 +}
arch/arm/mach-uniphier/arm64/timer.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <mapmem.h>
  9 +#include <linux/bitops.h>
  10 +#include <linux/io.h>
  11 +#include <linux/sizes.h>
  12 +
  13 +#define CNT_CONTROL_BASE 0x60E00000
  14 +
  15 +#define CNTCR 0x000
  16 +#define CNTCR_EN BIT(0)
  17 +
  18 +/* setup ARMv8 Generic Timer */
  19 +int timer_init(void)
  20 +{
  21 + void __iomem *base;
  22 + u32 tmp;
  23 +
  24 + base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
  25 +
  26 + /*
  27 + * Note:
  28 + * In a system that implements both Secure and Non-secure states,
  29 + * this register is only writable in Secure state.
  30 + */
  31 + tmp = readl(base + CNTCR);
  32 + tmp |= CNTCR_EN;
  33 + writel(tmp, base + CNTCR);
  34 +
  35 + unmap_sysmem(base);
  36 +
  37 + return 0;
  38 +}
arch/arm/mach-uniphier/board_common.c
Diff comments   View file @ 9d0c2ce
... ... @@ -8,10 +8,14 @@
8 8  
9 9 #include "micro-support-card.h"
10 10  
  11 +void uniphier_smp_kick_all_cpus(void);
  12 +
11 13 int board_init(void)
12 14 {
13 15 led_puts("Uboo");
14   -
  16 +#ifdef CONFIG_ARM64
  17 + uniphier_smp_kick_all_cpus();
  18 +#endif
15 19 return 0;
16 20 }
arch/arm/mach-uniphier/board_early_init_f.c
Diff comments   View file @ 9d0c2ce
... ... @@ -62,6 +62,14 @@
62 62 uniphier_pxs2_clk_init();
63 63 break;
64 64 #endif
  65 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  66 + case SOC_UNIPHIER_LD20:
  67 + uniphier_ld20_pin_init();
  68 + led_puts("U1");
  69 + uniphier_ld20_clk_init();
  70 + cci500_init(2);
  71 + break;
  72 +#endif
65 73 default:
66 74 break;
67 75 }
arch/arm/mach-uniphier/boards.c
Diff comments   View file @ 9d0c2ce
... ... @@ -165,6 +165,28 @@
165 165 };
166 166 #endif
167 167  
  168 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  169 +static const struct uniphier_board_data uniphier_ld20_data = {
  170 + .dram_freq = 1866,
  171 + .dram_nr_ch = 3,
  172 + .dram_ch[0] = {
  173 + .base = 0x80000000,
  174 + .size = 0x40000000,
  175 + .width = 32,
  176 + },
  177 + .dram_ch[1] = {
  178 + .base = 0xc0000000,
  179 + .size = 0x40000000,
  180 + .width = 32,
  181 + },
  182 + .dram_ch[2] = {
  183 + .base = 0x100000000UL,
  184 + .size = 0x40000000,
  185 + .width = 32,
  186 + },
  187 +};
  188 +#endif
  189 +
168 190 struct uniphier_board_id {
169 191 const char *compatible;
170 192 const struct uniphier_board_data *param;
... ... @@ -193,6 +215,9 @@
193 215 #endif
194 216 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
195 217 { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
  218 +#endif
  219 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  220 + { "socionext,ph1-ld20", &uniphier_ld20_data, },
196 221 #endif
197 222 };
198 223  
arch/arm/mach-uniphier/boot-mode/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -11,6 +11,7 @@
11 11 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
12 12 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
13 13 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
  14 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
14 15  
15 16 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
arch/arm/mach-uniphier/boot-mode/boot-device.h
Diff comments   View file @ 9d0c2ce
... ... @@ -16,11 +16,13 @@
16 16 u32 uniphier_ld4_boot_device(void);
17 17 u32 uniphier_pro5_boot_device(void);
18 18 u32 uniphier_pxs2_boot_device(void);
  19 +u32 uniphier_ld20_boot_device(void);
19 20  
20 21 void uniphier_sld3_boot_mode_show(void);
21 22 void uniphier_ld4_boot_mode_show(void);
22 23 void uniphier_pro5_boot_mode_show(void);
23 24 void uniphier_pxs2_boot_mode_show(void);
  25 +void uniphier_ld20_boot_mode_show(void);
24 26  
25 27 u32 spl_boot_device_raw(void);
26 28  
arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <linux/io.h>
  10 +
  11 +#include "../sg-regs.h"
  12 +#include "boot-device.h"
  13 +
  14 +static struct boot_device_info boot_device_table[] = {
  15 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
  16 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
  17 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
  18 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
  19 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
  20 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
  21 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
  22 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
  23 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
  24 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
  25 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
  26 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
  27 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
  28 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
  29 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
  30 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
  31 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
  32 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
  33 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
  34 + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
  35 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"},
  36 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"},
  37 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"},
  38 + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"},
  39 + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
  40 + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
  41 + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
  42 + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
  43 + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
  44 + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
  45 + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
  46 + {BOOT_DEVICE_NONE, "Reserved"},
  47 +};
  48 +
  49 +static int get_boot_mode_sel(void)
  50 +{
  51 + return (readl(SG_PINMON0) >> 1) & 0x1f;
  52 +}
  53 +
  54 +u32 uniphier_ld20_boot_device(void)
  55 +{
  56 + int boot_mode;
  57 +
  58 + if (~readl(SG_PINMON0) & 0x00000780)
  59 + return BOOT_DEVICE_USB;
  60 +
  61 + boot_mode = get_boot_mode_sel();
  62 +
  63 + return boot_device_table[boot_mode].type;
  64 +}
  65 +
  66 +void uniphier_ld20_boot_mode_show(void)
  67 +{
  68 + int mode_sel, i;
  69 +
  70 + mode_sel = get_boot_mode_sel();
  71 +
  72 + puts("Boot Mode Pin:\n");
  73 +
  74 + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
  75 + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
  76 + boot_device_table[i].info);
  77 +}
arch/arm/mach-uniphier/boot-mode/boot-mode.c
Diff comments   View file @ 9d0c2ce
... ... @@ -39,6 +39,10 @@
39 39 case SOC_UNIPHIER_LD6B:
40 40 return uniphier_pxs2_boot_device();
41 41 #endif
  42 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  43 + case SOC_UNIPHIER_LD20:
  44 + return uniphier_ld20_boot_device();
  45 +#endif
42 46 default:
43 47 return BOOT_DEVICE_NONE;
44 48 }
arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
Diff comments   View file @ 9d0c2ce
... ... @@ -39,6 +39,11 @@
39 39 uniphier_pxs2_boot_mode_show();
40 40 break;
41 41 #endif
  42 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  43 + case SOC_UNIPHIER_LD20:
  44 + uniphier_ld20_boot_mode_show();
  45 + break;
  46 +#endif
42 47 default:
43 48 break;
44 49 }
arch/arm/mach-uniphier/clk/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -9,4 +9,5 @@
9 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
10 10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
11 11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
  12 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
arch/arm/mach-uniphier/clk/clk-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <linux/io.h>
  8 +
  9 +#include "../init.h"
  10 +#include "../sc64-regs.h"
  11 +
  12 +void uniphier_ld20_clk_init(void)
  13 +{
  14 +}
arch/arm/mach-uniphier/cpu_info.c
Diff comments   View file @ 9d0c2ce
... ... @@ -48,7 +48,7 @@
48 48 puts("PH1-LD11 ()");
49 49 break;
50 50 case 0x32:
51   - puts("PH1-LD20 ()");
  51 + puts("PH1-LD20 (SC1401AJ1)");
52 52 break;
53 53 default:
54 54 printf("Unknown Processor ID (0x%x)\n", revision);
arch/arm/mach-uniphier/dram/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -12,6 +12,7 @@
12 12 ddrphy-training.o ddrphy-ld4.o
13 13 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
14 14 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
  15 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
15 16  
16 17 else
17 18  
arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Socionext Inc.
  3 + */
  4 +
  5 +#ifndef _DDRPHY_LD20_REGS_H
  6 +#define _DDRPHY_LD20_REGS_H
  7 +
  8 +#define PHY_SCL_DATA_0 0x00000104
  9 +#define PHY_SCL_DATA_1 0x00000108
  10 +#define PHY_SCL_LATENCY 0x0000010C
  11 +#define PHY_SCL_START 0x00000100
  12 +#define PHY_SCL_CONFIG_1 0x00000118
  13 +#define PHY_SCL_CONFIG_2 0x0000011C
  14 +#define PHY_PAD_CTRL 0x00000120
  15 +#define PHY_DLL_RECALIB 0x00000124
  16 +#define PHY_DLL_ADRCTRL 0x00000128
  17 +#define PHY_LANE_SEL 0x0000012C
  18 +#define PHY_DLL_TRIM_1 0x00000130
  19 +#define PHY_DLL_TRIM_2 0x00000134
  20 +#define PHY_DLL_TRIM_3 0x00000138
  21 +#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
  22 +#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
  23 +#define PHY_WRLVL_DYN_ODT 0x00000150
  24 +#define PHY_WRLVL_ON_OFF 0x00000154
  25 +#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
  26 +#define PHY_DLL_INCR_TRIM_1 0x00000164
  27 +#define PHY_DLL_INCR_TRIM_3 0x00000168
  28 +#define PHY_SCL_CONFIG_3 0x0000016C
  29 +#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
  30 +#define PHY_SCL_START_ADDR 0x00000188
  31 +#define PHY_DSCL_CNT 0x0000019C
  32 +#define PHY_DLL_TRIM_CLK 0x000001A4
  33 +#define PHY_DYNAMIC_BIT_LVL 0x000001AC
  34 +#define PHY_SCL_WINDOW_TRIM 0x000001B4
  35 +#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
  36 +#define PHY_SCL_CONFIG_4 0x000001BC
  37 +#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
  38 +#define PHY_VREF_TRAINING 0x000001C8
  39 +#define PHY_SCL_GATE_TIMING 0x000001E0
  40 +
  41 +#endif /* _DDRPHY_LD20_REGS_H */
arch/arm/mach-uniphier/dram/umc-ld20-regs.h
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Socionext Inc.
  3 + */
  4 +
  5 +#ifndef UMC_LD20_REGS_H
  6 +#define UMC_LD20_REGS_H
  7 +
  8 +#define UMC_CMDCTLA 0x00000000
  9 +#define UMC_CMDCTLB 0x00000004
  10 +#define UMC_CMDCTLC 0x00000008
  11 +#define UMC_INITCTLA 0x00000020
  12 +#define UMC_INITCTLB 0x00000024
  13 +#define UMC_INITCTLC 0x00000028
  14 +#define UMC_DRMMR0 0x00000030
  15 +#define UMC_DRMMR1 0x00000034
  16 +#define UMC_DRMMR2 0x00000038
  17 +#define UMC_DRMMR3 0x0000003C
  18 +#define UMC_INITSET 0x00000040
  19 +#define UMC_INITSTAT 0x00000044
  20 +#define UMC_CMDCTLE 0x00000050
  21 +#define UMC_SPCSETB 0x00000084
  22 +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
  23 +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
  24 +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
  25 +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
  26 +#define UMC_ACSCTLA 0x000000C0
  27 +#define UMC_ACSSETA 0x000000C4
  28 +#define UMC_MEMCONF0A 0x00000200
  29 +#define UMC_MEMCONF0B 0x00000204
  30 +#define UMC_MEMCONFCH 0x00000240
  31 +#define UMC_MEMMAPSET 0x00000250
  32 +#define UMC_FLOWCTLA 0x00000400
  33 +#define UMC_FLOWCTLB 0x00000404
  34 +#define UMC_FLOWCTLC 0x00000408
  35 +#define UMC_FLOWCTLG 0x00000508
  36 +#define UMC_RDATACTL_D0 0x00000600
  37 +#define UMC_WDATACTL_D0 0x00000604
  38 +#define UMC_RDATACTL_D1 0x00000608
  39 +#define UMC_WDATACTL_D1 0x0000060C
  40 +#define UMC_DATASET 0x00000610
  41 +#define UMC_ODTCTL_D0 0x00000618
  42 +#define UMC_ODTCTL_D1 0x0000061C
  43 +#define UMC_RESPCTL 0x00000624
  44 +#define UMC_DIRECTBUSCTRLA 0x00000680
  45 +#define UMC_DCCGCTL 0x00000720
  46 +#define UMC_DICGCTLA 0x00000724
  47 +#define UMC_DICGCTLB 0x00000728
  48 +#define UMC_ERRMASKA 0x00000958
  49 +#define UMC_ERRMASKB 0x0000095C
  50 +#define UMC_BSICMAPSET 0x00000988
  51 +#define UMC_DIOCTLA 0x00000C00
  52 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
  53 +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
  54 +#define UMC_DFISTCTLC 0x00000C18
  55 +#define UMC_DFICUPDCTLA 0x00000C20
  56 +#define UMC_DFIPUPDCTLA 0x00000C30
  57 +#define UMC_DFICSOVRRD 0x00000C84
  58 +#define UMC_DFITURNOFF 0x00000C88
  59 +
  60 +/* UM registers */
  61 +#define UMC_MBUS0 0x00080004
  62 +#define UMC_MBUS1 0x00081004
  63 +#define UMC_MBUS2 0x00082004
  64 +#define UMC_MBUS3 0x00000C78
  65 +#define UMC_MBUS4 0x00000CF8
  66 +#define UMC_MBUS5 0x00000E78
  67 +#define UMC_MBUS6 0x00000EF8
  68 +#define UMC_MBUS7 0x00001278
  69 +#define UMC_MBUS8 0x000012F8
  70 +#define UMC_MBUS9 0x00002478
  71 +#define UMC_MBUS10 0x000024F8
  72 +
  73 +#endif /* UMC_LD20_REGS_H */
arch/arm/mach-uniphier/dram/umc-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Socionext Inc.
  3 + *
  4 + * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <linux/bitops.h>
  11 +#include <linux/err.h>
  12 +#include <linux/io.h>
  13 +#include <linux/sizes.h>
  14 +#include <asm/processor.h>
  15 +
  16 +#include "../init.h"
  17 +#include "ddrphy-ld20-regs.h"
  18 +#include "umc-ld20-regs.h"
  19 +
  20 +#define DRAM_CH_NR 3
  21 +
  22 +enum dram_freq {
  23 + DRAM_FREQ_1866M,
  24 + DRAM_FREQ_NR,
  25 +};
  26 +
  27 +enum dram_size {
  28 + DRAM_SZ_256M,
  29 + DRAM_SZ_512M,
  30 + DRAM_SZ_NR,
  31 +};
  32 +
  33 +/* umc */
  34 +static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
  35 +static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
  36 +static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
  37 +static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
  38 +static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
  39 +
  40 +static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
  41 +static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
  42 +static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
  43 +
  44 +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
  45 +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
  46 +static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
  47 +static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  48 + {0x0049071D, 0x0078071D},
  49 +};
  50 +
  51 +static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
  52 +static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
  53 +static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
  54 +static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
  55 +static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
  56 +static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
  57 +static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
  58 +
  59 +static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
  60 +static u32 umc_directbusctrla[DRAM_CH_NR] = {
  61 + 0x00000000, 0x00000001, 0x00000001
  62 +};
  63 +
  64 +/* DDR PHY */
  65 +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
  66 +{
  67 + writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
  68 + while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
  69 + cpu_relax();
  70 +
  71 + writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
  72 + writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
  73 + writel(0x00000000, phy_base + PHY_LANE_SEL);
  74 + writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
  75 + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
  76 + writel(0x00000006, phy_base + PHY_LANE_SEL);
  77 + writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
  78 + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
  79 + writel(0x0000000c, phy_base + PHY_LANE_SEL);
  80 + writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
  81 + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
  82 + writel(0x00000012, phy_base + PHY_LANE_SEL);
  83 + writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
  84 + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
  85 + writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
  86 + writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
  87 + writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
  88 + writel(0x00000070, phy_base + PHY_VREF_TRAINING);
  89 + writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
  90 + writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
  91 + writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
  92 + writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
  93 + writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
  94 + writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
  95 + writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
  96 + writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
  97 + writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
  98 + writel(0x00000000, phy_base + PHY_LANE_SEL);
  99 + writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
  100 + writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
  101 + writel(0x00005076, phy_base + PHY_SCL_LATENCY);
  102 +}
  103 +
  104 +static int ddrphy_training(void __iomem *phy_base)
  105 +{
  106 + writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
  107 + writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
  108 + writel(0x50000000, phy_base + PHY_SCL_START);
  109 +
  110 + while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
  111 + cpu_relax();
  112 +
  113 + writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
  114 + writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
  115 + writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
  116 + writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
  117 + writel(0x11000000, phy_base + PHY_SCL_START);
  118 +
  119 + while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
  120 + cpu_relax();
  121 +
  122 + writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
  123 + writel(0x30500000, phy_base + PHY_SCL_START);
  124 +
  125 + while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
  126 + cpu_relax();
  127 +
  128 + writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
  129 + writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
  130 + writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
  131 + writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
  132 + writel(0x11000000, phy_base + PHY_SCL_START);
  133 +
  134 + while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
  135 + cpu_relax();
  136 +
  137 + writel(0x34000000, phy_base + PHY_SCL_START);
  138 +
  139 + while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
  140 + cpu_relax();
  141 +
  142 + writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
  143 +
  144 + return 0;
  145 +}
  146 +
  147 +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
  148 + unsigned long size, int ch)
  149 +{
  150 + enum dram_size size_e;
  151 +
  152 + switch (size) {
  153 + case 0:
  154 + return 0;
  155 + case SZ_256M:
  156 + size_e = DRAM_SZ_256M;
  157 + break;
  158 + case SZ_512M:
  159 + size_e = DRAM_SZ_512M;
  160 + break;
  161 + default:
  162 + pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
  163 + size, ch);
  164 + return -EINVAL;
  165 + }
  166 +
  167 + /* Wait for PHY Init Complete */
  168 + while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
  169 + cpu_relax();
  170 +
  171 + writel(0x00000001, dc_base + UMC_DFICSOVRRD);
  172 + writel(0x00000000, dc_base + UMC_DFITURNOFF);
  173 +
  174 + writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
  175 + writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
  176 + writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
  177 +
  178 + writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
  179 + writel(0x00000004, dc_base + UMC_DRMMR1);
  180 + writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
  181 + writel(0x00000000, dc_base + UMC_DRMMR3);
  182 +
  183 + writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
  184 + writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
  185 + writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
  186 + writel(0x00000008, dc_base + UMC_MEMMAPSET);
  187 +
  188 + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
  189 + writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
  190 + writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
  191 + writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
  192 +
  193 + writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
  194 + writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
  195 +
  196 + writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
  197 + writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
  198 + writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
  199 + writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
  200 + writel(umc_dataset[freq], dc_base + UMC_DATASET);
  201 +
  202 + writel(0x00400020, dc_base + UMC_DCCGCTL);
  203 + writel(0x00000003, dc_base + UMC_ACSCTLA);
  204 + writel(0x00000103, dc_base + UMC_FLOWCTLG);
  205 + writel(0x00010200, dc_base + UMC_ACSSETA);
  206 +
  207 + writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
  208 + writel(0x00004444, dc_base + UMC_FLOWCTLC);
  209 + writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
  210 +
  211 + writel(0x00202000, dc_base + UMC_FLOWCTLB);
  212 + writel(0x00000000, dc_base + UMC_BSICMAPSET);
  213 + writel(0x00000000, dc_base + UMC_ERRMASKA);
  214 + writel(0x00000000, dc_base + UMC_ERRMASKB);
  215 +
  216 + writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
  217 +
  218 + writel(0x00000001, dc_base + UMC_INITSET);
  219 + /* Wait for PHY Init Complete */
  220 + while (readl(dc_base + UMC_INITSTAT) & BIT(0))
  221 + cpu_relax();
  222 +
  223 + writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
  224 + writel(0x00000000, dc_base + UMC_DFICSOVRRD);
  225 +
  226 + return 0;
  227 +}
  228 +
  229 +static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
  230 + enum dram_freq freq, unsigned long size, int ch)
  231 +{
  232 + void __iomem *dc_base = umc_ch_base + 0x00011000;
  233 + void __iomem *phy_base = phy_ch_base;
  234 + int ret;
  235 +
  236 + /* PHY Update Mode (ON) */
  237 + writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
  238 +
  239 + /* deassert PHY reset signals */
  240 + writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
  241 + dc_base + UMC_DIOCTLA);
  242 +
  243 + ddrphy_init(phy_base, freq);
  244 +
  245 + ret = umc_dc_init(dc_base, freq, size, ch);
  246 + if (ret)
  247 + return ret;
  248 +
  249 + ret = ddrphy_training(phy_base);
  250 + if (ret)
  251 + return ret;
  252 +
  253 + return 0;
  254 +}
  255 +
  256 +static void um_init(void __iomem *um_base)
  257 +{
  258 + writel(0x000000ff, um_base + UMC_MBUS0);
  259 + writel(0x000000ff, um_base + UMC_MBUS1);
  260 + writel(0x000000ff, um_base + UMC_MBUS2);
  261 + writel(0x00000001, um_base + UMC_MBUS3);
  262 + writel(0x00000001, um_base + UMC_MBUS4);
  263 + writel(0x00000001, um_base + UMC_MBUS5);
  264 + writel(0x00000001, um_base + UMC_MBUS6);
  265 + writel(0x00000001, um_base + UMC_MBUS7);
  266 + writel(0x00000001, um_base + UMC_MBUS8);
  267 + writel(0x00000001, um_base + UMC_MBUS9);
  268 + writel(0x00000001, um_base + UMC_MBUS10);
  269 +}
  270 +
  271 +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
  272 +{
  273 + void __iomem *um_base = (void __iomem *)0x5b600000;
  274 + void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
  275 + void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
  276 + enum dram_freq freq;
  277 + int ch, ret;
  278 +
  279 + switch (bd->dram_freq) {
  280 + case 1866:
  281 + freq = DRAM_FREQ_1866M;
  282 + break;
  283 + default:
  284 + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
  285 + return -EINVAL;
  286 + }
  287 +
  288 + for (ch = 0; ch < bd->dram_nr_ch; ch++) {
  289 + unsigned long size = bd->dram_ch[ch].size;
  290 + unsigned int width = bd->dram_ch[ch].width;
  291 +
  292 + ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
  293 + size / (width / 16), ch);
  294 + if (ret) {
  295 + pr_err("failed to initialize UMC ch%d\n", ch);
  296 + return ret;
  297 + }
  298 +
  299 + umc_ch_base += 0x00200000;
  300 + phy_ch_base += 0x00004000;
  301 + }
  302 +
  303 + um_init(um_base);
  304 +
  305 + return 0;
  306 +}
arch/arm/mach-uniphier/early-clk/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -9,4 +9,5 @@
9 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
10 10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
11 11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
  12 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <linux/io.h>
  8 +
  9 +#include "../init.h"
  10 +#include "../sc64-regs.h"
  11 +
  12 +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
  13 +{
  14 + u32 tmp;
  15 +
  16 + /* deassert reset */
  17 + tmp = readl(SC_RSTCTRL7);
  18 + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
  19 + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
  20 + SC_RSTCTRL7_UMC30;
  21 + writel(tmp, SC_RSTCTRL7);
  22 +
  23 + /* provide clocks */
  24 + tmp = readl(SC_CLKCTRL7);
  25 + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
  26 + SC_CLKCTRL7_UMC30;
  27 + writel(tmp, SC_CLKCTRL7);
  28 +
  29 + return 0;
  30 +}
arch/arm/mach-uniphier/init.h
Diff comments   View file @ 9d0c2ce
... ... @@ -32,6 +32,7 @@
32 32 int uniphier_sld8_init(const struct uniphier_board_data *bd);
33 33 int uniphier_pro5_init(const struct uniphier_board_data *bd);
34 34 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
  35 +int uniphier_ld20_init(const struct uniphier_board_data *bd);
35 36  
36 37 #if defined(CONFIG_MICRO_SUPPORT_CARD)
37 38 int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
... ... @@ -86,6 +87,7 @@
86 87 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
87 88 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
88 89 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
  90 +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
89 91  
90 92 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
91 93  
... ... @@ -93,6 +95,7 @@
93 95 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
94 96 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
95 97 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
  98 +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
96 99  
97 100 void uniphier_sld3_pin_init(void);
98 101 void uniphier_ld4_pin_init(void);
99 102  
... ... @@ -101,11 +104,15 @@
101 104 void uniphier_pro5_pin_init(void);
102 105 void uniphier_pxs2_pin_init(void);
103 106 void uniphier_ld6b_pin_init(void);
  107 +void uniphier_ld20_pin_init(void);
104 108  
105 109 void uniphier_ld4_clk_init(void);
106 110 void uniphier_pro4_clk_init(void);
107 111 void uniphier_pro5_clk_init(void);
108 112 void uniphier_pxs2_clk_init(void);
  113 +void uniphier_ld20_clk_init(void);
  114 +
  115 +void cci500_init(int nr_slaves);
109 116  
110 117 #define pr_err(fmt, args...) printf(fmt, ##args)
111 118  
arch/arm/mach-uniphier/init/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -11,4 +11,5 @@
11 11 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
12 12 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
13 13 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
  14 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o
arch/arm/mach-uniphier/init/init-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +
  10 +#include "../init.h"
  11 +#include "../micro-support-card.h"
  12 +
  13 +int uniphier_ld20_init(const struct uniphier_board_data *bd)
  14 +{
  15 + uniphier_sbc_init_savepin(bd);
  16 +
  17 + support_card_reset();
  18 +
  19 + support_card_init();
  20 +
  21 + led_puts("L0");
  22 +
  23 + memconf_init(bd);
  24 + uniphier_pxs2_memconf_init(bd);
  25 +
  26 + led_puts("L1");
  27 +
  28 + uniphier_ld20_early_clk_init(bd);
  29 +
  30 + led_puts("L2");
  31 +
  32 + led_puts("L3");
  33 +
  34 +#ifdef CONFIG_SPL_SERIAL_SUPPORT
  35 + preloader_console_init();
  36 +#endif
  37 +
  38 + led_puts("L4");
  39 +
  40 + {
  41 + int res;
  42 +
  43 + res = uniphier_ld20_umc_init(bd);
  44 + if (res < 0) {
  45 + while (1)
  46 + ;
  47 + }
  48 + }
  49 +
  50 + led_puts("L5");
  51 +
  52 + return 0;
  53 +}
arch/arm/mach-uniphier/init/init.c
Diff comments   View file @ 9d0c2ce
... ... @@ -55,6 +55,11 @@
55 55 uniphier_pxs2_init(param);
56 56 break;
57 57 #endif
  58 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  59 + case SOC_UNIPHIER_LD20:
  60 + uniphier_ld20_init(param);
  61 + break;
  62 +#endif
58 63 default:
59 64 break;
60 65 }
arch/arm/mach-uniphier/memconf/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -6,4 +6,5 @@
6 6 obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o
7 7 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o
8 8 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o
  9 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o
arch/arm/mach-uniphier/memconf/memconf-pxs2.c
Diff comments   View file @ 9d0c2ce
... ... @@ -49,6 +49,9 @@
49 49 case SZ_512M:
50 50 tmp |= SG_MEMCONF_CH2_SZ_512M;
51 51 break;
  52 + case SZ_1G:
  53 + tmp |= SG_MEMCONF_CH2_SZ_1G;
  54 + break;
52 55 default:
53 56 pr_err("error: unsupported DRAM Ch2 size\n");
54 57 return -EINVAL;
arch/arm/mach-uniphier/pinctrl/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -9,4 +9,5 @@
9 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
10 10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
11 11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
  12 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
Diff comments   View file @ 9d0c2ce
  1 +/*
  2 + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <linux/io.h>
  8 +
  9 +#include "../init.h"
  10 +#include "../sg-regs.h"
  11 +
  12 +void uniphier_ld20_pin_init(void)
  13 +{
  14 + /* Comment format: PAD Name -> Function Name */
  15 +
  16 +#ifdef CONFIG_NAND_DENALI
  17 + sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */
  18 + sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
  19 + sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */
  20 + sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */
  21 + sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */
  22 + sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */
  23 + sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */
  24 + sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */
  25 + sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */
  26 + sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */
  27 + sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */
  28 + sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */
  29 + sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */
  30 + sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */
  31 + sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */
  32 + sg_set_iectrl_range(3, 17);
  33 +#endif
  34 +
  35 +#ifdef CONFIG_USB_XHCI_UNIPHIER
  36 + sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
  37 + sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */
  38 + sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
  39 + sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */
  40 + sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
  41 + sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */
  42 + sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
  43 + sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */
  44 + sg_set_iectrl_range(46, 53);
  45 +#endif
  46 +}
arch/arm/mach-uniphier/sbc/Makefile
Diff comments   View file @ 9d0c2ce
... ... @@ -9,4 +9,5 @@
9 9 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
10 10 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
11 11 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
  12 +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o
arch/arm/mach-uniphier/sg-regs.h
Diff comments   View file @ 9d0c2ce
... ... @@ -50,10 +50,11 @@
50 50 #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
51 51 #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
52 52 #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
  53 +#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
53 54 #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
54 55 #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
55 56 #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
56   -/* PH1-LD6b, ProXstream2 only */
  57 +/* PH1-LD6b, ProXstream2, PH1-LD20 only */
57 58 #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
58 59  
59 60 #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
configs/uniphier_ld20_defconfig
Diff comments   View file @ 9d0c2ce
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_UNIPHIER=y
  3 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  4 +CONFIG_ARCH_UNIPHIER_LD20=y
  5 +CONFIG_MICRO_SUPPORT_CARD=y
  6 +CONFIG_SYS_TEXT_BASE=0x84000000
  7 +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
  8 +CONFIG_HUSH_PARSER=y
  9 +# CONFIG_CMD_XIMG is not set
  10 +# CONFIG_CMD_ENV_EXISTS is not set
  11 +CONFIG_CMD_I2C=y
  12 +CONFIG_CMD_USB=y
  13 +# CONFIG_CMD_FPGA is not set
  14 +CONFIG_CMD_GPIO=y
  15 +CONFIG_CMD_TFTPPUT=y
  16 +CONFIG_CMD_PING=y
  17 +CONFIG_CMD_TIME=y
  18 +# CONFIG_CMD_MISC is not set
  19 +CONFIG_NET_RANDOM_ETHADDR=y
  20 +CONFIG_SPL_OF_TRANSLATE=y
  21 +CONFIG_GPIO_UNIPHIER=y
  22 +CONFIG_MMC_UNIPHIER=y
  23 +CONFIG_PINCTRL=y
  24 +CONFIG_SPL_PINCTRL=y
  25 +CONFIG_UNIPHIER_SERIAL=y
  26 +CONFIG_USB=y
  27 +CONFIG_USB_XHCI_HCD=y
  28 +CONFIG_USB_STORAGE=y
include/configs/uniphier.h
Diff comments   View file @ 9d0c2ce
... ... @@ -71,8 +71,7 @@
71 71 /* serial console configuration */
72 72 #define CONFIG_BAUDRATE 115200
73 73  
74   -
75   -#if !defined(CONFIG_SPL_BUILD)
  74 +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
76 75 #define CONFIG_USE_ARCH_MEMSET
77 76 #define CONFIG_USE_ARCH_MEMCPY
78 77 #endif
79 78  
80 79  
... ... @@ -99,9 +98,19 @@
99 98 #define CONFIG_SYS_MMC_ENV_DEV 0
100 99 #define CONFIG_SYS_MMC_ENV_PART 1
101 100  
  101 +#ifdef CONFIG_ARM64
  102 +#define CONFIG_ARMV8_MULTIENTRY
  103 +#define CPU_RELEASE_ADDR 0x80000100
  104 +#define COUNTER_FREQUENCY 50000000
  105 +#define CONFIG_GICV3
  106 +#define GICD_BASE 0x5fe00000
  107 +#define GICR_BASE 0x5fe80000
  108 +#else
102 109 /* Time clock 1MHz */
103 110 #define CONFIG_SYS_TIMER_RATE 1000000
  111 +#endif
104 112  
  113 +
105 114 #define CONFIG_SYS_MAX_NAND_DEVICE 1
106 115 #define CONFIG_SYS_NAND_MAX_CHIPS 2
107 116 #define CONFIG_SYS_NAND_ONFI_DETECTION
108 117  
109 118  
110 119  
... ... @@ -176,21 +185,34 @@
176 185 "bootm $fit_addr_r\0" \
177 186 "__nfsboot=run tftpboot\0"
178 187 #else
  188 +#ifdef CONFIG_ARM64
  189 +#define CONFIG_CMD_BOOTI
  190 +#define CONFIG_BOOTFILE "Image"
  191 +#define LINUXBOOT_CMD "booti"
  192 +#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
  193 +#define KERNEL_SIZE "kernel_size=0x00c00000\0"
  194 +#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
  195 +#else
179 196 #define CONFIG_CMD_BOOTZ
180 197 #define CONFIG_BOOTFILE "zImage"
  198 +#define LINUXBOOT_CMD "bootz"
  199 +#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
  200 +#define KERNEL_SIZE "kernel_size=0x00800000\0"
  201 +#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
  202 +#endif
181 203 #define LINUXBOOT_ENV_SETTINGS \
182 204 "fdt_addr=0x00100000\0" \
183 205 "fdt_addr_r=0x84100000\0" \
184 206 "fdt_size=0x00008000\0" \
185 207 "kernel_addr=0x00200000\0" \
186   - "kernel_addr_r=0x80208000\0" \
187   - "kernel_size=0x00800000\0" \
188   - "ramdisk_addr=0x00a00000\0" \
  208 + KERNEL_ADDR_R \
  209 + KERNEL_SIZE \
  210 + RAMDISK_ADDR \
189 211 "ramdisk_addr_r=0x84a00000\0" \
190 212 "ramdisk_size=0x00600000\0" \
191 213 "ramdisk_file=rootfs.cpio.uboot\0" \
192 214 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
193   - "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \" \
  215 + LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \" \
194 216 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
195 217 "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
196 218 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
197 219  
198 220  
... ... @@ -238,14 +260,21 @@
238 260 #define CONFIG_SYS_SDRAM_BASE 0x80000000
239 261 #define CONFIG_NR_DRAM_BANKS 2
240 262  
241   -#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \
  263 +#if defined(CONFIG_ARM64)
  264 +#define CONFIG_SPL_TEXT_BASE 0x30000000
  265 +#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
  266 + defined(CONFIG_ARCH_UNIPHIER_LD4) || \
242 267 defined(CONFIG_ARCH_UNIPHIER_SLD8)
243 268 #define CONFIG_SPL_TEXT_BASE 0x00040000
244 269 #else
245 270 #define CONFIG_SPL_TEXT_BASE 0x00100000
246 271 #endif
247 272  
  273 +#if defined(CONFIG_ARCH_UNIPHIER_LD20)
  274 +#define CONFIG_SPL_STACK (0x3001c000)
  275 +#else
248 276 #define CONFIG_SPL_STACK (0x00100000)
  277 +#endif
249 278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
250 279  
251 280 #define CONFIG_PANIC_HANG
252 281  
... ... @@ -253,8 +282,10 @@
253 282 #define CONFIG_SPL_FRAMEWORK
254 283 #define CONFIG_SPL_SERIAL_SUPPORT
255 284 #define CONFIG_SPL_NOR_SUPPORT
  285 +#ifndef CONFIG_ARM64
256 286 #define CONFIG_SPL_NAND_SUPPORT
257 287 #define CONFIG_SPL_MMC_SUPPORT
  288 +#endif
258 289  
259 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
260 291 #define CONFIG_SPL_LIBGENERIC_SUPPORT
... ... @@ -270,6 +301,8 @@
270 301 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
271 302 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
272 303 #define CONFIG_SPL_MAX_SIZE 0x10000
  304 +#define CONFIG_SPL_BSS_START_ADDR 0x30016000
  305 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
273 306  
274 307 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */