microblaze: Add SPL support

Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>

microblaze: Add SPL support
Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek
1 parent 22ff7f4d19
Showing 9 changed files with 219 additions and 2 deletions Side-by-side Diff
arch/microblaze/cpu/Makefile
arch/microblaze/cpu/spl.c
arch/microblaze/cpu/start.S
arch/microblaze/cpu/timer.c
arch/microblaze/cpu/u-boot-spl.lds
arch/microblaze/include/asm/spl.h
arch/microblaze/include/asm/u-boot.h
arch/microblaze/lib/board.c
include/configs/microblaze-generic.h
@@ -8,4 +8,5 @@
 extra-y	= start.o
 obj-y	= irq.o
 obj-y	+= cpu.o interrupts.o cache.o exception.o timer.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+bool boot_linux;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+/* Board initialization after bss clearance */
+void spl_board_init(void)
+{
+	gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(char *, ulong, ulong)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t)spl_image.entry_point;
+
+	image_entry(NULL, 0, (ulong)arg);
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int spl_start_uboot(void)
+{
+#ifdef CONFIG_SPL_OS_BOOT
+	if (boot_linux)
+		return 0;
+#endif
+
+	return 1;
+}
@@ -22,6 +22,11 @@
 	 */
  
 	mts	rmsr, r0	/* disable cache */
+
+#if defined(CONFIG_SPL_BUILD)
+	addi	r1, r0, CONFIG_SPL_STACK_ADDR
+	addi	r1, r1, -4	/* Decrement SP to top of memory */
+#else
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
  
@@ -115,6 +120,7 @@
 	sh	r7, r0, r8
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
+#endif /* BUILD_SPL */
  
 	/* Flush cache before enable cache */
 	addik	r5, r0, 0
  
  
@@ -139,9 +145,14 @@
 	cmp     r6, r5, r4 /* check if we have reach the end */
 	bnei    r6, 2b
 3:	/* jumping to board_init */
+#ifndef CONFIG_SPL_BUILD
 	brai	board_init_f
+#else
+	brai	board_init_r
+#endif
 1:	bri	1b
  
+#ifndef CONFIG_SPL_BUILD
 /*
  * Read 16bit little endian
  */
@@ -174,4 +185,5 @@
 	rtsd	r15, 8
 	or	r0, r0, r0
 	.end	out16
+#endif
@@ -34,6 +34,7 @@
 	}
 }
  
+#ifndef CONFIG_SPL_BUILD
 static void timer_isr(void *arg)
 {
 	timestamp++;
  
@@ -62,10 +63,15 @@
 		if (ret)
 			tmr = NULL;
 	}
-
 	/* No problem if timer is not found/initialized */
 	return 0;
 }
+#else
+int timer_init(void)
+{
+	return 0;
+}
+#endif
  
 /*
  * This function is derived from PowerPC code (read timebase as long long).
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		arch/microblaze/cpu/start.o (.text)
+		*(.text)
+		*(.text.*)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+		__data_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.sbss)
+		*(.scommon)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__end = . ;
+}
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+        "SPL image plus BSS too big");
+#endif
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_MICROBLAZE_SPL_H_
+#define _ASM_MICROBLAZE_SPL_H_
+
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_NOR		2
+#define BOOT_DEVICE_SPI		3
+
+#endif
@@ -25,6 +25,7 @@
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 	unsigned int	bi_baudrate;	/* Console Baudrate */
+	ulong		bi_boot_params; /* where this board expects params */
 } bd_t;
  
 /* For image.h:image_check_target_arch() */
@@ -50,10 +50,14 @@
 	fdtdec_check_fdt,
 #endif
 	serial_init,
+#ifndef CONFIG_SPL_BUILD
 	console_init_f,
+#endif
 	display_banner,
+#ifndef CONFIG_SPL_BUILD
 	interrupts_init,
 	timer_init,
+#endif
 	NULL,
 };
  
@@ -66,7 +70,7 @@
 	gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
 	bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
 						- GENERATED_BD_INFO_SIZE);
-#if defined(CONFIG_CMD_FLASH)
+#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
 	ulong flash_size = 0;
 #endif
 	asm ("nop");	/* FIXME gd is not initialize - wait */
  
@@ -88,9 +92,12 @@
 	/* FDT is at end of image */
 	gd->fdt_blob = (void *)__end;
 #endif
+
+#ifndef CONFIG_SPL_BUILD
 	/* Allow the early environment to override the fdt address */
 	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
 						(uintptr_t)gd->fdt_blob);
+#endif
  
 	/*
 	 * The Malloc area is immediately below the monitor copy in DRAM
@@ -110,6 +117,7 @@
 			hang();
 	}
  
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_OF_CONTROL
 	/* For now, put this check after the console is ready */
 	if (fdtdec_prepare_fdt())
@@ -190,5 +198,6 @@
 		WATCHDOG_RESET();
 		main_loop();
 	}
+#endif /* CONFIG_SPL_BUILD */
 }
@@ -447,5 +447,65 @@
 # undef CONFIG_PHYLIB
 #endif
  
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_NOR_SUPPORT
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x60000)
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x40000)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
+					 0x1000000)
+
+/* SP location before relocation, must use scratch RAM */
+/* BRAM start */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+/* BRAM size - will be generated */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100
+
+/*
+ * The main reason to do it in this way is that MALLOC_START
+ * can't be defined - common/spl/spl.c
+ */
+#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
+# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE)
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
+#else
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
+#endif
+
+/* Just for sure that there is a space for stack */
+#define CONFIG_SPL_STACK_SIZE		0x100
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_INIT_RAM_ADDR - \
+					 GENERATED_GBL_DATA_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE - \
+					 CONFIG_SPL_STACK_SIZE)
+
 #endif	/* __CONFIG_H */
...	...	@@ -8,4 +8,5 @@
8	8	extra-y = start.o
9	9	obj-y = irq.o
10	10	obj-y += cpu.o interrupts.o cache.o exception.o timer.o
	11	+obj-$(CONFIG_SPL_BUILD) += spl.o
	1	+/*
	2	+ * (C) Copyright 2013 - 2014 Xilinx, Inc
	3	+ *
	4	+ * Michal Simek <michal.simek@xilinx.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <image.h>
	11	+#include <spl.h>
	12	+#include <version.h>
	13	+#include <asm/io.h>
	14	+#include <asm/u-boot.h>
	15	+
	16	+DECLARE_GLOBAL_DATA_PTR;
	17	+
	18	+bool boot_linux;
	19	+
	20	+u32 spl_boot_device(void)
	21	+{
	22	+ return BOOT_DEVICE_NOR;
	23	+}
	24	+
	25	+/* Board initialization after bss clearance */
	26	+void spl_board_init(void)
	27	+{
	28	+ gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
	29	+
	30	+ /* enable console uart printing */
	31	+ preloader_console_init();
	32	+}
	33	+
	34	+#ifdef CONFIG_SPL_OS_BOOT
	35	+void __noreturn jump_to_image_linux(void *arg)
	36	+{
	37	+ debug("Entering kernel arg pointer: 0x%p\n", arg);
	38	+ typedef void (image_entry_arg_t)(char , ulong, ulong)
	39	+ __attribute__ ((noreturn));
	40	+ image_entry_arg_t image_entry =
	41	+ (image_entry_arg_t)spl_image.entry_point;
	42	+
	43	+ image_entry(NULL, 0, (ulong)arg);
	44	+}
	45	+#endif /* CONFIG_SPL_OS_BOOT */
	46	+
	47	+int spl_start_uboot(void)
	48	+{
	49	+#ifdef CONFIG_SPL_OS_BOOT
	50	+ if (boot_linux)
	51	+ return 0;
	52	+#endif
	53	+
	54	+ return 1;
	55	+}
...	...	@@ -22,6 +22,11 @@
22	22	*/
23	23
24	24	mts rmsr, r0 /* disable cache */
	25	+
	26	+#if defined(CONFIG_SPL_BUILD)
	27	+ addi r1, r0, CONFIG_SPL_STACK_ADDR
	28	+ addi r1, r1, -4 /* Decrement SP to top of memory */
	29	+#else
25	30	addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
26	31	addi r1, r1, -4 /* Decrement SP to top of memory */
27	32
...	...	@@ -115,6 +120,7 @@
115	120	sh r7, r0, r8
116	121	rsubi r8, r10, 0x26
117	122	sh r6, r0, r8
	123	+#endif /* BUILD_SPL */
118	124
119	125	/* Flush cache before enable cache */
120	126	addik r5, r0, 0
121	127
122	128
...	...	@@ -139,9 +145,14 @@
139	145	cmp r6, r5, r4 /* check if we have reach the end */
140	146	bnei r6, 2b
141	147	3: /* jumping to board_init */
	148	+#ifndef CONFIG_SPL_BUILD
142	149	brai board_init_f
	150	+#else
	151	+ brai board_init_r
	152	+#endif
143	153	1: bri 1b
144	154
	155	+#ifndef CONFIG_SPL_BUILD
145	156	/*
146	157	* Read 16bit little endian
147	158	*/
...	...	@@ -174,4 +185,5 @@
174	185	rtsd r15, 8
175	186	or r0, r0, r0
176	187	.end out16
	188	+#endif
...	...	@@ -34,6 +34,7 @@
34	34	}
35	35	}
36	36
	37	+#ifndef CONFIG_SPL_BUILD
37	38	static void timer_isr(void *arg)
38	39	{
39	40	timestamp++;
40	41
...	...	@@ -62,10 +63,15 @@
62	63	if (ret)
63	64	tmr = NULL;
64	65	}
65		-
66	66	/* No problem if timer is not found/initialized */
67	67	return 0;
68	68	}
	69	+#else
	70	+int timer_init(void)
	71	+{
	72	+ return 0;
	73	+}
	74	+#endif
69	75
70	76	/*
71	77	* This function is derived from PowerPC code (read timebase as long long).
...	...	@@ -25,6 +25,7 @@
25	25	unsigned long bi_sramstart; /* start of SRAM memory */
26	26	unsigned long bi_sramsize; /* size of SRAM memory */
27	27	unsigned int bi_baudrate; /* Console Baudrate */
	28	+ ulong bi_boot_params; /* where this board expects params */
28	29	} bd_t;
29	30
30	31	/* For image.h:image_check_target_arch() */
...	...	@@ -50,10 +50,14 @@
50	50	fdtdec_check_fdt,
51	51	#endif
52	52	serial_init,
	53	+#ifndef CONFIG_SPL_BUILD
53	54	console_init_f,
	55	+#endif
54	56	display_banner,
	57	+#ifndef CONFIG_SPL_BUILD
55	58	interrupts_init,
56	59	timer_init,
	60	+#endif
57	61	NULL,
58	62	};
59	63
...	...	@@ -66,7 +70,7 @@
66	70	gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
67	71	bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
68	72	- GENERATED_BD_INFO_SIZE);
69		-#if defined(CONFIG_CMD_FLASH)
	73	+#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
70	74	ulong flash_size = 0;
71	75	#endif
72	76	asm ("nop"); /* FIXME gd is not initialize - wait */
73	77
...	...	@@ -88,9 +92,12 @@
88	92	/* FDT is at end of image */
89	93	gd->fdt_blob = (void *)__end;
90	94	#endif
	95	+
	96	+#ifndef CONFIG_SPL_BUILD
91	97	/* Allow the early environment to override the fdt address */
92	98	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
93	99	(uintptr_t)gd->fdt_blob);
	100	+#endif
94	101
95	102	/*
96	103	* The Malloc area is immediately below the monitor copy in DRAM
...	...	@@ -110,6 +117,7 @@
110	117	hang();
111	118	}
112	119
	120	+#ifndef CONFIG_SPL_BUILD
113	121	#ifdef CONFIG_OF_CONTROL
114	122	/* For now, put this check after the console is ready */
115	123	if (fdtdec_prepare_fdt())
...	...	@@ -190,5 +198,6 @@
190	198	WATCHDOG_RESET();
191	199	main_loop();
192	200	}
	201	+#endif /* CONFIG_SPL_BUILD */
193	202	}
...	...	@@ -447,5 +447,65 @@
447	447	# undef CONFIG_PHYLIB
448	448	#endif
449	449
	450	+/* SPL part */
	451	+#define CONFIG_SPL
	452	+#define CONFIG_CMD_SPL
	453	+#define CONFIG_SPL_FRAMEWORK
	454	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	455	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	456	+#define CONFIG_SPL_SERIAL_SUPPORT
	457	+#define CONFIG_SPL_BOARD_INIT
	458	+
	459	+#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	460	+
	461	+#define CONFIG_SPL_RAM_DEVICE
	462	+#define CONFIG_SPL_NOR_SUPPORT
	463	+
	464	+/* for booting directly linux */
	465	+#define CONFIG_SPL_OS_BOOT
	466	+
	467	+#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	468	+ 0x60000)
	469	+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	470	+ 0x40000)
	471	+#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	472	+ 0x1000000)
	473	+
	474	+/* SP location before relocation, must use scratch RAM */
	475	+/* BRAM start */
	476	+#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	477	+/* BRAM size - will be generated */
	478	+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	479	+/* Stack pointer prior relocation, must situated at on-chip RAM */
	480	+#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
	481	+ CONFIG_SYS_INIT_RAM_SIZE - \
	482	+ GENERATED_GBL_DATA_SIZE)
	483	+
	484	+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
	485	+
	486	+/*
	487	+ * The main reason to do it in this way is that MALLOC_START
	488	+ * can't be defined - common/spl/spl.c
	489	+ */
	490	+#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
	491	+# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
	492	+ CONFIG_SYS_SPL_MALLOC_SIZE)
	493	+# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
	494	+#else
	495	+# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
	496	+#endif
	497	+
	498	+/* Just for sure that there is a space for stack */
	499	+#define CONFIG_SPL_STACK_SIZE 0x100
	500	+
	501	+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	502	+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	503	+
	504	+#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	505	+ CONFIG_SYS_INIT_RAM_ADDR - \
	506	+ GENERATED_GBL_DATA_SIZE - \
	507	+ CONFIG_SYS_SPL_MALLOC_SIZE - \
	508	+ CONFIG_SPL_STACK_SIZE)
	509	+
450	510	#endif /* __CONFIG_H */