Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).

Removed CFG_CMD_DISPLAY from default commands. Fixed compiler warning in net.c. Patch by Stefan Roese, 31 Aug 2005

Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
Removed CFG_CMD_DISPLAY from default commands. Fixed compiler warning in net.c. Patch by Stefan Roese, 31 Aug 2005
Stefan Roese
1 parent 77f6580cc0
Showing 8 changed files with 109 additions and 20 deletions Side-by-side Diff
CHANGELOG
MAKEALL
board/tqm8540/tqm8540.c
board/tqm8560/tqm8560.c
include/cmd_confdefs.h
include/configs/TQM8540.h
include/configs/TQM8560.h
net/net.c
@@ -2,6 +2,11 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
  
+* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
+  Removed CFG_CMD_DISPLAY from default commands.
+  Fixed compiler warning in net.c.
+  Patch by Stefan Roese, 31 Aug 2005
+
 * Fix problems with ld version 2.16 (dot outside sections problem)
   Pointed out by Gerhard Jaeger, 31 Aug 2005;
   cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
@@ -126,6 +126,7 @@
 	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8548CDS	\
 	MPC8555CDS	MPC8560ADS	PM854		PM856		\
 	sbc8540		sbc8560		stxgp3		TQM8540		\
+	TQM8560								\
 "
  
 #########################################################################
@@ -74,15 +74,26 @@
  
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur = &immap->im_gur;
-		uint temp_ddrdll = 0;
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+		int i,x;
  
+		x = 10;
+
 		/*
 		 * Work around to stabilize DDR DLL
 		 */
-		temp_ddrdll = gur->ddrdllcr;
-		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-		asm ("sync;isync;msync");
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay (200);
+		while (gur->ddrdllcr != 0x81000100) {
+			gur->devdisr = gur->devdisr | 0x00010000;
+			asm("sync;isync;msync");
+			for (i=0; i<x; i++)
+				;
+			gur->devdisr = gur->devdisr & 0xfff7ffff;
+			asm("sync;isync;msync");
+			x++;
+		}
 	}
 #endif
  
@@ -229,15 +229,26 @@
  
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur = &immap->im_gur;
-		uint temp_ddrdll = 0;
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+		int i,x;
  
+		x = 10;
+
 		/*
 		 * Work around to stabilize DDR DLL
 		 */
-		temp_ddrdll = gur->ddrdllcr;
-		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-		asm ("sync;isync;msync");
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay (200);
+		while (gur->ddrdllcr != 0x81000100) {
+			gur->devdisr = gur->devdisr | 0x00010000;
+			asm("sync;isync;msync");
+			for (i=0; i<x; i++)
+				;
+			gur->devdisr = gur->devdisr & 0xfff7ffff;
+			asm("sync;isync;msync");
+			x++;
+		}
 	}
 #endif
  
@@ -109,6 +109,7 @@
 			CFG_CMD_DATE	| \
 			CFG_CMD_DHCP	| \
 			CFG_CMD_DIAG	| \
+			CFG_CMD_DISPLAY	| \
 			CFG_CMD_DOC	| \
 			CFG_CMD_DTT	| \
 			CFG_CMD_ECHO	| \
@@ -230,12 +230,34 @@
 #endif
  
 /* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
  
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C EEPROM */
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
 #define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
@@ -301,7 +323,6 @@
  
 #endif	/* CONFIG_TSEC_ENET */
  
-
 /*
  * Environment
  */
@@ -342,6 +363,9 @@
 #define CONFIG_COMMANDS        (CONFIG_CMD_PRIV	| \
 				ADD_PCI_CMD	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DTT	| \
 				CFG_CMD_PING	)
 #include <cmd_confdefs.h>
  
@@ -426,6 +450,11 @@
 	"bootfile=/tftpboot/tqm8540/uImage\0"				\
 	"kernel_addr=FE000000\0"					\
 	"ramdisk_addr=FE100000\0"					\
+	"load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
  
@@ -38,6 +38,7 @@
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
+#define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8560		1	/* MPC8560 specific */
 #define CONFIG_TQM8560		1	/* TQM8560 board specific */
  
  
  
@@ -226,12 +227,34 @@
 #endif
  
 /* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
  
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C EEPROM */
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
 #define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
@@ -331,6 +354,9 @@
 #define CONFIG_COMMANDS        (CONFIG_CMD_PRIV	| \
 				ADD_PCI_CMD	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DTT	| \
 				CFG_CMD_PING	)
 #include <cmd_confdefs.h>
  
@@ -415,6 +441,11 @@
 	"bootfile=/tftpboot/tqm8560/uImage\0"				\
 	"kernel_addr=FE000000\0"					\
 	"ramdisk_addr=FE100000\0"					\
+	"load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
  
@@ -1574,7 +1574,7 @@
 NetCksum(uchar * ptr, int len)
 {
 	ulong	xsum;
-	ushort *p = ptr;
+	ushort *p = (ushort *)ptr;
  
 	xsum = 0;
 	while (len-- > 0)
...	...	@@ -2,6 +2,11 @@
2	2	Changes for U-Boot 1.1.4:
3	3	======================================================================
4	4
	5	+* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
	6	+ Removed CFG_CMD_DISPLAY from default commands.
	7	+ Fixed compiler warning in net.c.
	8	+ Patch by Stefan Roese, 31 Aug 2005
	9	+
5	10	* Fix problems with ld version 2.16 (dot outside sections problem)
6	11	Pointed out by Gerhard Jaeger, 31 Aug 2005;
7	12	cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
...	...	@@ -126,6 +126,7 @@
126	126	MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
127	127	MPC8555CDS MPC8560ADS PM854 PM856 \
128	128	sbc8540 sbc8560 stxgp3 TQM8540 \
	129	+ TQM8560 \
129	130	"
130	131
131	132	#########################################################################
...	...	@@ -74,15 +74,26 @@
74	74
75	75	#if defined(CONFIG_DDR_DLL)
76	76	{
77		- volatile ccsr_gur_t *gur = &immap->im_gur;
78		- uint temp_ddrdll = 0;
	77	+ volatile ccsr_gur_t *gur= &immap->im_gur;
	78	+ int i,x;
79	79
	80	+ x = 10;
	81	+
80	82	/*
81	83	* Work around to stabilize DDR DLL
82	84	*/
83		- temp_ddrdll = gur->ddrdllcr;
84		- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
85		- asm ("sync;isync;msync");
	85	+ gur->ddrdllcr = 0x81000000;
	86	+ asm("sync;isync;msync");
	87	+ udelay (200);
	88	+ while (gur->ddrdllcr != 0x81000100) {
	89	+ gur->devdisr = gur->devdisr \| 0x00010000;
	90	+ asm("sync;isync;msync");
	91	+ for (i=0; i<x; i++)
	92	+ ;
	93	+ gur->devdisr = gur->devdisr & 0xfff7ffff;
	94	+ asm("sync;isync;msync");
	95	+ x++;
	96	+ }
86	97	}
87	98	#endif
88	99
...	...	@@ -229,15 +229,26 @@
229	229
230	230	#if defined(CONFIG_DDR_DLL)
231	231	{
232		- volatile ccsr_gur_t *gur = &immap->im_gur;
233		- uint temp_ddrdll = 0;
	232	+ volatile ccsr_gur_t *gur= &immap->im_gur;
	233	+ int i,x;
234	234
	235	+ x = 10;
	236	+
235	237	/*
236	238	* Work around to stabilize DDR DLL
237	239	*/
238		- temp_ddrdll = gur->ddrdllcr;
239		- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
240		- asm ("sync;isync;msync");
	240	+ gur->ddrdllcr = 0x81000000;
	241	+ asm("sync;isync;msync");
	242	+ udelay (200);
	243	+ while (gur->ddrdllcr != 0x81000100) {
	244	+ gur->devdisr = gur->devdisr \| 0x00010000;
	245	+ asm("sync;isync;msync");
	246	+ for (i=0; i<x; i++)
	247	+ ;
	248	+ gur->devdisr = gur->devdisr & 0xfff7ffff;
	249	+ asm("sync;isync;msync");
	250	+ x++;
	251	+ }
241	252	}
242	253	#endif
243	254
...	...	@@ -109,6 +109,7 @@
109	109	CFG_CMD_DATE \| \
110	110	CFG_CMD_DHCP \| \
111	111	CFG_CMD_DIAG \| \
	112	+ CFG_CMD_DISPLAY \| \
112	113	CFG_CMD_DOC \| \
113	114	CFG_CMD_DTT \| \
114	115	CFG_CMD_ECHO \| \
...	...	@@ -230,12 +230,34 @@
230	230	#endif
231	231
232	232	/* I2C */
233		-#define CONFIG_HARD_I2C /* I2C with hardware support*/
234		-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
235		-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	233	+#define CONFIG_HARD_I2C /* I2C with hardware support */
	234	+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	235	+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
236	236	#define CFG_I2C_SLAVE 0x7F
237		-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	237	+#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
238	238
	239	+/* I2C RTC */
	240	+#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
	241	+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	242	+
	243	+/* I2C EEPROM */
	244	+/*
	245	+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
	246	+ */
	247	+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	248	+#define CFG_I2C_EEPROM_ADDR_LEN 2
	249	+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	250	+#define CFG_EEPROM_PAGE_WRITE_ENABLE
	251	+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	252	+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
	253	+
	254	+/* I2C SYSMON (LM75) */
	255	+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	256	+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	257	+#define CFG_DTT_MAX_TEMP 70
	258	+#define CFG_DTT_LOW_TEMP -30
	259	+#define CFG_DTT_HYSTERESIS 3
	260	+
239	261	/* RapidIO MMU */
240	262	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
241	263	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
...	...	@@ -301,7 +323,6 @@
301	323
302	324	#endif /* CONFIG_TSEC_ENET */
303	325
304		-
305	326	/*
306	327	* Environment
307	328	*/
...	...	@@ -342,6 +363,9 @@
342	363	#define CONFIG_COMMANDS (CONFIG_CMD_PRIV \| \
343	364	ADD_PCI_CMD \| \
344	365	CFG_CMD_I2C \| \
	366	+ CFG_CMD_DATE \| \
	367	+ CFG_CMD_EEPROM \| \
	368	+ CFG_CMD_DTT \| \
345	369	CFG_CMD_PING )
346	370	#include <cmd_confdefs.h>
347	371
...	...	@@ -426,6 +450,11 @@
426	450	"bootfile=/tftpboot/tqm8540/uImage\0" \
427	451	"kernel_addr=FE000000\0" \
428	452	"ramdisk_addr=FE100000\0" \
	453	+ "load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0" \
	454	+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	455	+ "cp.b 100000 fffc0000 40000;" \
	456	+ "setenv filesize;saveenv\0" \
	457	+ "upd=run load;run update\0" \
429	458	""
430	459	#define CONFIG_BOOTCOMMAND "run flash_self"
431	460
...	...	@@ -38,6 +38,7 @@
38	38	#define CONFIG_BOOKE 1 /* BOOKE */
39	39	#define CONFIG_E500 1 /* BOOKE e500 family */
40	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	41	+#define CONFIG_CPM2 1 /* has CPM2 */
41	42	#define CONFIG_MPC8560 1 /* MPC8560 specific */
42	43	#define CONFIG_TQM8560 1 /* TQM8560 board specific */
43	44
44	45
45	46
...	...	@@ -226,12 +227,34 @@
226	227	#endif
227	228
228	229	/* I2C */
229		-#define CONFIG_HARD_I2C /* I2C with hardware support*/
230		-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
231		-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	230	+#define CONFIG_HARD_I2C /* I2C with hardware support */
	231	+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	232	+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
232	233	#define CFG_I2C_SLAVE 0x7F
233		-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	234	+#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
234	235
	236	+/* I2C RTC */
	237	+#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
	238	+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	239	+
	240	+/* I2C EEPROM */
	241	+/*
	242	+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
	243	+ */
	244	+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	245	+#define CFG_I2C_EEPROM_ADDR_LEN 2
	246	+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	247	+#define CFG_EEPROM_PAGE_WRITE_ENABLE
	248	+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	249	+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
	250	+
	251	+/* I2C SYSMON (LM75) */
	252	+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	253	+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	254	+#define CFG_DTT_MAX_TEMP 70
	255	+#define CFG_DTT_LOW_TEMP -30
	256	+#define CFG_DTT_HYSTERESIS 3
	257	+
235	258	/* RapidIO MMU */
236	259	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
237	260	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
...	...	@@ -331,6 +354,9 @@
331	354	#define CONFIG_COMMANDS (CONFIG_CMD_PRIV \| \
332	355	ADD_PCI_CMD \| \
333	356	CFG_CMD_I2C \| \
	357	+ CFG_CMD_DATE \| \
	358	+ CFG_CMD_EEPROM \| \
	359	+ CFG_CMD_DTT \| \
334	360	CFG_CMD_PING )
335	361	#include <cmd_confdefs.h>
336	362
...	...	@@ -415,6 +441,11 @@
415	441	"bootfile=/tftpboot/tqm8560/uImage\0" \
416	442	"kernel_addr=FE000000\0" \
417	443	"ramdisk_addr=FE100000\0" \
	444	+ "load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0" \
	445	+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	446	+ "cp.b 100000 fffc0000 40000;" \
	447	+ "setenv filesize;saveenv\0" \
	448	+ "upd=run load;run update\0" \
418	449	""
419	450	#define CONFIG_BOOTCOMMAND "run flash_self"
420	451
...	...	@@ -1574,7 +1574,7 @@
1574	1574	NetCksum(uchar * ptr, int len)
1575	1575	{
1576	1576	ulong xsum;
1577		- ushort *p = ptr;
	1577	+ ushort p = (ushort )ptr;
1578	1578
1579	1579	xsum = 0;
1580	1580	while (len-- > 0)