ARM: MX51: PLL errata workaround

This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>

ARM: MX51: PLL errata workaround
This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>
David Jander · Albert ARIBAUD
1 parent 96c9745fa1
Showing 3 changed files with 60 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/include/asm/arch-mx5/imx-regs.h
doc/README.imx5
@@ -121,6 +121,35 @@
 	beq 1b
 .endm
  
+.macro setup_pll_errata pll, freq
+	ldr r2, =\pll
+	mov r1, #0x0
+	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+	ldr r1, =0x00001236
+	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
+1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
+	ands r1, r1, #0x1
+	beq 1b
+
+	ldr r5, \freq
+	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
+	str r5, [r2, #PLL_DP_HFS_MFN]
+
+	mov r1, #0x1
+	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
+
+2:	ldr r1, [r2, #PLL_DP_CONFIG]
+	tst r1, #1
+	bne 2b
+
+	ldr r1, =100		     /* Wait at least 4 us */
+3:	subs r1, r1, #1
+	bge 3b
+
+	mov r1, #0x2
+	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+.endm
+
 .macro init_clock
 	ldr r0, =CCM_BASE_ADDR
  
  
@@ -157,7 +186,12 @@
 	mov r1, #0x4
 	str r1, [r0, #CLKCTL_CCSR]
  
+#if defined(CONFIG_MX51_PLL_ERRATA)
+	setup_pll PLL1_BASE_ADDR, 864
+	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
+#else
 	setup_pll PLL1_BASE_ADDR, 800
+#endif
  
 #if defined(CONFIG_MX51)
 	setup_pll PLL3_BASE_ADDR, 665
@@ -287,6 +321,10 @@
 	mov pc,lr
  
 /* Board level setting value */
+W_DP_OP_864:              .word DP_OP_864
+W_DP_MFD_864:             .word DP_MFD_864
+W_DP_MFN_864:             .word DP_MFN_864
+W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
 W_DP_OP_800:              .word DP_OP_800
 W_DP_MFD_800:             .word DP_MFD_800
 W_DP_MFN_800:             .word DP_MFN_800
@@ -235,6 +235,11 @@
  
 /* Assuming 24MHz input clock with doubler ON */
 /*                            MFI         PDF */
+#define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_864	(180 - 1) /* PL Dither mode */
+#define DP_MFN_864	180
+#define DP_MFN_800_DIT	60 /* PL Dither mode */
+
 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_850	(48 - 1)
 #define DP_MFN_850	41
+U-Boot for Freescale i.MX5x
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX5x SoCs.
+
+1. CONFIGURATION OPTIONS/SETTINGS
+---------------------------------
+
+1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
+    This option should be enabled by all boards using the i.MX51 silicon
+    version up until (including) 3.0 running at 800MHz.
+    The PLL's in the i.MX51 processor can go out of lock due to a metastable
+    condition in an analog flip-flop when used at high frequencies.
+    This workaround implements an undocumented feature in the PLL (dither
+    mode), which causes the effect of this failure to be much lower (in terms
+    of frequency deviation), avoiding system failure, or at least decreasing
+    the likelihood of system failure.
...	...	@@ -121,6 +121,35 @@
121	121	beq 1b
122	122	.endm
123	123
	124	+.macro setup_pll_errata pll, freq
	125	+ ldr r2, =\pll
	126	+ mov r1, #0x0
	127	+ str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	128	+ ldr r1, =0x00001236
	129	+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
	130	+1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
	131	+ ands r1, r1, #0x1
	132	+ beq 1b
	133	+
	134	+ ldr r5, \freq
	135	+ str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
	136	+ str r5, [r2, #PLL_DP_HFS_MFN]
	137	+
	138	+ mov r1, #0x1
	139	+ str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
	140	+
	141	+2: ldr r1, [r2, #PLL_DP_CONFIG]
	142	+ tst r1, #1
	143	+ bne 2b
	144	+
	145	+ ldr r1, =100 /* Wait at least 4 us */
	146	+3: subs r1, r1, #1
	147	+ bge 3b
	148	+
	149	+ mov r1, #0x2
	150	+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
	151	+.endm
	152	+
124	153	.macro init_clock
125	154	ldr r0, =CCM_BASE_ADDR
126	155
127	156
...	...	@@ -157,7 +186,12 @@
157	186	mov r1, #0x4
158	187	str r1, [r0, #CLKCTL_CCSR]
159	188
	189	+#if defined(CONFIG_MX51_PLL_ERRATA)
	190	+ setup_pll PLL1_BASE_ADDR, 864
	191	+ setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
	192	+#else
160	193	setup_pll PLL1_BASE_ADDR, 800
	194	+#endif
161	195
162	196	#if defined(CONFIG_MX51)
163	197	setup_pll PLL3_BASE_ADDR, 665
...	...	@@ -287,6 +321,10 @@
287	321	mov pc,lr
288	322
289	323	/* Board level setting value */
	324	+W_DP_OP_864: .word DP_OP_864
	325	+W_DP_MFD_864: .word DP_MFD_864
	326	+W_DP_MFN_864: .word DP_MFN_864
	327	+W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
290	328	W_DP_OP_800: .word DP_OP_800
291	329	W_DP_MFD_800: .word DP_MFD_800
292	330	W_DP_MFN_800: .word DP_MFN_800
...	...	@@ -235,6 +235,11 @@
235	235
236	236	/* Assuming 24MHz input clock with doubler ON */
237	237	/* MFI PDF */
	238	+#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
	239	+#define DP_MFD_864 (180 - 1) /* PL Dither mode */
	240	+#define DP_MFN_864 180
	241	+#define DP_MFN_800_DIT 60 /* PL Dither mode */
	242	+
238	243	#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
239	244	#define DP_MFD_850 (48 - 1)
240	245	#define DP_MFN_850 41
	1	+U-Boot for Freescale i.MX5x
	2	+
	3	+This file contains information for the port of U-Boot to the Freescale
	4	+i.MX5x SoCs.
	5	+
	6	+1. CONFIGURATION OPTIONS/SETTINGS
	7	+---------------------------------
	8	+
	9	+1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
	10	+ This option should be enabled by all boards using the i.MX51 silicon
	11	+ version up until (including) 3.0 running at 800MHz.
	12	+ The PLL's in the i.MX51 processor can go out of lock due to a metastable
	13	+ condition in an analog flip-flop when used at high frequencies.
	14	+ This workaround implements an undocumented feature in the PLL (dither
	15	+ mode), which causes the effect of this failure to be much lower (in terms
	16	+ of frequency deviation), avoiding system failure, or at least decreasing
	17	+ the likelihood of system failure.