Eric Lee / smarc-uboot

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Commit 9dee205d78402c6c48076735859f4e1a293cf693

Authored by ramneek mehresh
Committed by York Sun
1 parent a4c955bc3b
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

fsl/usb: Move USB internal phy definitions to fsl_usb.h 

fsl_usb.h file created to share data bewteen usb platform code
and usb ip driver. Internal phy structure definitions moved to
this file

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

Showing 3 changed files with 84 additions and 51 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 9dee205
... ... @@ -22,6 +22,7 @@
22 22 #include <asm/fsl_law.h>
23 23 #include <asm/fsl_serdes.h>
24 24 #include <asm/fsl_srio.h>
  25 +#include <fsl_usb.h>
25 26 #include <hwconfig.h>
26 27 #include <linux/compiler.h>
27 28 #include "mp.h"
... ... @@ -605,7 +606,7 @@
605 606  
606 607 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
607 608 {
608   - ccsr_usb_phy_t *usb_phy1 =
  609 + struct ccsr_usb_phy __iomem *usb_phy1 =
609 610 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
610 611 out_be32(&usb_phy1->usb_enable_override,
611 612 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
... ... @@ -613,7 +614,7 @@
613 614 #endif
614 615 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
615 616 {
616   - ccsr_usb_phy_t *usb_phy2 =
  617 + struct ccsr_usb_phy __iomem *usb_phy2 =
617 618 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
618 619 out_be32(&usb_phy2->usb_enable_override,
619 620 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
... ... @@ -635,7 +636,7 @@
635 636 #endif
636 637  
637 638 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
638   - ccsr_usb_phy_t *usb_phy =
  639 + struct ccsr_usb_phy __iomem *usb_phy =
639 640 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
640 641 setbits_be32(&usb_phy->pllprg[1],
641 642 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 9dee205
... ... @@ -2846,54 +2846,6 @@
2846 2846 u8 res4[0x400];
2847 2847 } ccsr_pme_t;
2848 2848  
2849   -#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
2850   -struct ccsr_usb_port_ctrl {
2851   - u32 ctrl;
2852   - u32 drvvbuscfg;
2853   - u32 pwrfltcfg;
2854   - u32 sts;
2855   - u8 res_14[0xc];
2856   - u32 bistcfg;
2857   - u32 biststs;
2858   - u32 abistcfg;
2859   - u32 abiststs;
2860   - u8 res_30[0x10];
2861   - u32 xcvrprg;
2862   - u32 anaprg;
2863   - u32 anadrv;
2864   - u32 anasts;
2865   -};
2866   -
2867   -typedef struct ccsr_usb_phy {
2868   - u32 id;
2869   - struct ccsr_usb_port_ctrl port1;
2870   - u8 res_50[0xc];
2871   - u32 tvr;
2872   - u32 pllprg[4];
2873   - u8 res_70[0x4];
2874   - u32 anaccfg;
2875   - u32 dbg;
2876   - u8 res_7c[0x4];
2877   - struct ccsr_usb_port_ctrl port2;
2878   - u8 res_dc[0x334];
2879   -} ccsr_usb_phy_t;
2880   -
2881   -#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
2882   -#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
2883   -#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
2884   -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
2885   -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
2886   -#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
2887   -#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
2888   -#else
2889   -typedef struct ccsr_usb_phy {
2890   - u8 res0[0x18];
2891   - u32 usb_enable_override;
2892   - u8 res[0xe4];
2893   -} ccsr_usb_phy_t;
2894   -#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
2895   -#endif
2896   -
2897 2849 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2898 2850 struct ccsr_raide {
2899 2851 u8 res0[0x543];
  1 +/*
  2 + * Freescale USB Controller
  3 + *
  4 + * Copyright 2013 Freescale Semiconductor, Inc.
  5 + *
  6 + * This software may be used and distributed according to the
  7 + * terms of the GNU Public License, Version 2, incorporated
  8 + * herein by reference.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License
  12 + * Version 2 as published by the Free Software Foundation.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#ifndef _ASM_FSL_USB_H_
  26 +#define _ASM_FSL_USB_H_
  27 +
  28 +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  29 +struct ccsr_usb_port_ctrl {
  30 + u32 ctrl;
  31 + u32 drvvbuscfg;
  32 + u32 pwrfltcfg;
  33 + u32 sts;
  34 + u8 res_14[0xc];
  35 + u32 bistcfg;
  36 + u32 biststs;
  37 + u32 abistcfg;
  38 + u32 abiststs;
  39 + u8 res_30[0x10];
  40 + u32 xcvrprg;
  41 + u32 anaprg;
  42 + u32 anadrv;
  43 + u32 anasts;
  44 +};
  45 +
  46 +struct ccsr_usb_phy {
  47 + u32 id;
  48 + struct ccsr_usb_port_ctrl port1;
  49 + u8 res_50[0xc];
  50 + u32 tvr;
  51 + u32 pllprg[4];
  52 + u8 res_70[0x4];
  53 + u32 anaccfg;
  54 + u32 dbg;
  55 + u8 res_7c[0x4];
  56 + struct ccsr_usb_port_ctrl port2;
  57 + u8 res_dc[0x334];
  58 +};
  59 +
  60 +#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
  61 +#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
  62 +#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
  63 +#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
  64 +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
  65 +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
  66 +#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
  67 +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
  68 +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
  69 +#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
  70 +#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
  71 +#else
  72 +struct ccsr_usb_phy {
  73 + u8 res0[0x18];
  74 + u32 usb_enable_override;
  75 + u8 res[0xe4];
  76 +};
  77 +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  78 +#endif
  79 +
  80 +#endif /*_ASM_FSL_USB_H_ */