Commit 9ed781a6ffba48d75b3ae0a0058ca439b8e178c2
Committed by
Bin Meng
Bin Meng
1 parent
ac643e0363
Exists in
v2017.01-smarct4x
and in
30 other branches
x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Showing 4 changed files with 12 additions and 55 deletions Side-by-side Diff
arch/x86/cpu/ivybridge/bd82x6x.c
| ... | ... | @@ -18,45 +18,6 @@ |
| 18 | 18 | |
| 19 | 19 | #define BIOS_CTRL 0xdc |
| 20 | 20 | |
| 21 | -void bd82x6x_pci_init(pci_dev_t dev) | |
| 22 | -{ | |
| 23 | - u16 reg16; | |
| 24 | - u8 reg8; | |
| 25 | - | |
| 26 | - debug("bd82x6x PCI init.\n"); | |
| 27 | - /* Enable Bus Master */ | |
| 28 | - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); | |
| 29 | - reg16 |= PCI_COMMAND_MASTER; | |
| 30 | - x86_pci_write_config16(dev, PCI_COMMAND, reg16); | |
| 31 | - | |
| 32 | - /* This device has no interrupt */ | |
| 33 | - x86_pci_write_config8(dev, INTR, 0xff); | |
| 34 | - | |
| 35 | - /* disable parity error response and SERR */ | |
| 36 | - reg16 = x86_pci_read_config16(dev, BCTRL); | |
| 37 | - reg16 &= ~(1 << 0); | |
| 38 | - reg16 &= ~(1 << 1); | |
| 39 | - x86_pci_write_config16(dev, BCTRL, reg16); | |
| 40 | - | |
| 41 | - /* Master Latency Count must be set to 0x04! */ | |
| 42 | - reg8 = x86_pci_read_config8(dev, SMLT); | |
| 43 | - reg8 &= 0x07; | |
| 44 | - reg8 |= (0x04 << 3); | |
| 45 | - x86_pci_write_config8(dev, SMLT, reg8); | |
| 46 | - | |
| 47 | - /* Will this improve throughput of bus masters? */ | |
| 48 | - x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); | |
| 49 | - | |
| 50 | - /* Clear errors in status registers */ | |
| 51 | - reg16 = x86_pci_read_config16(dev, PSTS); | |
| 52 | - /* reg16 |= 0xf900; */ | |
| 53 | - x86_pci_write_config16(dev, PSTS, reg16); | |
| 54 | - | |
| 55 | - reg16 = x86_pci_read_config16(dev, SECSTS); | |
| 56 | - /* reg16 |= 0xf900; */ | |
| 57 | - x86_pci_write_config16(dev, SECSTS, reg16); | |
| 58 | -} | |
| 59 | - | |
| 60 | 21 | static int bd82x6x_probe(struct udevice *dev) |
| 61 | 22 | { |
| 62 | 23 | const void *blob = gd->fdt_blob; |
| 63 | 24 | |
| ... | ... | @@ -108,10 +69,7 @@ |
| 108 | 69 | return -EINVAL; |
| 109 | 70 | } |
| 110 | 71 | |
| 111 | - bd82x6x_pci_init(PCH_DEV); | |
| 112 | 72 | bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); |
| 113 | - northbridge_enable(PCH_DEV); | |
| 114 | - northbridge_init(PCH_DEV); | |
| 115 | 73 | |
| 116 | 74 | return 0; |
| 117 | 75 | } |
arch/x86/cpu/ivybridge/northbridge.c
| ... | ... | @@ -197,15 +197,12 @@ |
| 197 | 197 | dm_pci_write_config8(dev, PAM6, 0x33); |
| 198 | 198 | } |
| 199 | 199 | |
| 200 | -static int bd82x6x_northbridge_probe(struct udevice *dev) | |
| 200 | +static int bd82x6x_northbridge_early_init(struct udevice *dev) | |
| 201 | 201 | { |
| 202 | 202 | const int chipset_type = SANDYBRIDGE_MOBILE; |
| 203 | 203 | u32 capid0_a; |
| 204 | 204 | u8 reg8; |
| 205 | 205 | |
| 206 | - if (gd->flags & GD_FLG_RELOC) | |
| 207 | - return 0; | |
| 208 | - | |
| 209 | 206 | /* Device ID Override Enable should be done very early */ |
| 210 | 207 | dm_pci_read_config32(dev, 0xe4, &capid0_a); |
| 211 | 208 | if (capid0_a & (1 << 10)) { |
| ... | ... | @@ -222,6 +219,17 @@ |
| 222 | 219 | |
| 223 | 220 | /* Device Enable */ |
| 224 | 221 | dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); |
| 222 | + | |
| 223 | + return 0; | |
| 224 | +} | |
| 225 | + | |
| 226 | +static int bd82x6x_northbridge_probe(struct udevice *dev) | |
| 227 | +{ | |
| 228 | + if (!(gd->flags & GD_FLG_RELOC)) | |
| 229 | + return bd82x6x_northbridge_early_init(dev); | |
| 230 | + | |
| 231 | + northbridge_enable(PCH_DEV); | |
| 232 | + northbridge_init(PCH_DEV); | |
| 225 | 233 | |
| 226 | 234 | return 0; |
| 227 | 235 | } |
arch/x86/include/asm/arch-ivybridge/bd82x6x.h
| ... | ... | @@ -9,7 +9,6 @@ |
| 9 | 9 | |
| 10 | 10 | void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); |
| 11 | 11 | void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); |
| 12 | -void bd82x6x_pci_init(pci_dev_t dev); | |
| 13 | 12 | void bd82x6x_usb_ehci_init(pci_dev_t dev); |
| 14 | 13 | void bd82x6x_usb_xhci_init(pci_dev_t dev); |
| 15 | 14 | int gma_func0_init(struct udevice *dev, const void *blob, int node); |
board/google/chromebook_link/link.c
| ... | ... | @@ -14,14 +14,6 @@ |
| 14 | 14 | |
| 15 | 15 | int arch_early_init_r(void) |
| 16 | 16 | { |
| 17 | - struct udevice *dev; | |
| 18 | - int ret; | |
| 19 | - | |
| 20 | - /* Make sure the platform controller hub is up and running */ | |
| 21 | - ret = uclass_get_device(UCLASS_PCH, 0, &dev); | |
| 22 | - if (ret) | |
| 23 | - return ret; | |
| 24 | - | |
| 25 | 17 | return 0; |
| 26 | 18 | } |
| 27 | 19 |