Eric Lee / smarc-uboot

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Commit 9efaca3e847696ed40fca1dbbc621fcc35b8d94c

Authored by Scott Wood
Committed by Tom Rini
1 parent 3907305fb9
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ahci: mmio_base is a virtual address 

Don't store it in a u32.

Don't dereference the bus address as if it were a virtual address
(fixes 284231e49a2b4 ("ahci: Support splitting of read transactions
into multiple chunks")).

Fixes crash on boot in MPC8641HPCN_36BIT target.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>

Showing 7 changed files with 16 additions and 15 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap-common/boot-common.c
Diff comments   View file @ 9efaca3
... ... @@ -159,7 +159,7 @@
159 159 #ifdef CONFIG_SCSI_AHCI_PLAT
160 160 void arch_preboot_os(void)
161 161 {
162   - ahci_reset(DWC_AHSATA_BASE);
  162 + ahci_reset((void __iomem *)DWC_AHSATA_BASE);
163 163 }
164 164 #endif
arch/arm/cpu/armv7/omap-common/sata.c
Diff comments   View file @ 9efaca3
... ... @@ -69,7 +69,7 @@
69 69 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
70 70 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
71 71  
72   - ret = ahci_init(DWC_AHSATA_BASE);
  72 + ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
73 73  
74 74 return ret;
75 75 }
... ... @@ -88,7 +88,7 @@
88 88  
89 89 void scsi_bus_reset(void)
90 90 {
91   - ahci_reset(DWC_AHSATA_BASE);
92   - ahci_init(DWC_AHSATA_BASE);
  91 + ahci_reset((void __iomem *)DWC_AHSATA_BASE);
  92 + ahci_init((void __iomem *)DWC_AHSATA_BASE);
93 93 }
board/highbank/highbank.c
Diff comments   View file @ 9efaca3
... ... @@ -57,7 +57,7 @@
57 57 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
58 58  
59 59 if (reg & PWRDOM_STAT_SATA) {
60   - ahci_init(HB_AHCI_BASE);
  60 + ahci_init((void __iomem *)HB_AHCI_BASE);
61 61 scsi_scan(1);
62 62 }
63 63 }
... ... @@ -83,6 +83,6 @@
83 83 if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
84 84 return;
85 85  
86   - ahci_init(SUNXI_SATA_BASE);
  86 + ahci_init((void __iomem *)SUNXI_SATA_BASE);
87 87 }
drivers/block/ahci.c
Diff comments   View file @ 9efaca3
... ... @@ -137,10 +137,10 @@
137 137 }
138 138 #endif
139 139  
140   -int ahci_reset(u32 base)
  140 +int ahci_reset(void __iomem *base)
141 141 {
142 142 int i = 1000;
143   - u32 host_ctl_reg = base + HOST_CTL;
  143 + u32 __iomem *host_ctl_reg = base + HOST_CTL;
144 144 u32 tmp = readl(host_ctl_reg); /* global controller reset */
145 145  
146 146 if ((tmp & HOST_RESET) == 0)
... ... @@ -419,8 +419,9 @@
419 419 probe_ent->pio_mask = 0x1f;
420 420 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
421 421  
422   - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
423   - debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
  422 + probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
  423 + PCI_REGION_MEM);
  424 + debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
424 425  
425 426 /* Take from kernel:
426 427 * JMicron-specific fixup:
... ... @@ -939,7 +940,7 @@
939 940 }
940 941  
941 942 #ifdef CONFIG_SCSI_AHCI_PLAT
942   -int ahci_init(u32 base)
  943 +int ahci_init(void __iomem *base)
943 944 {
944 945 int i, rc = 0;
945 946 u32 linkmap;
drivers/block/dwc_ahsata.c
Diff comments   View file @ 9efaca3
... ... @@ -343,7 +343,7 @@
343 343 | ATA_FLAG_PIO_DMA
344 344 | ATA_FLAG_NO_ATAPI;
345 345  
346   - probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
  346 + probe_ent->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
347 347  
348 348 /* initialize adapter */
349 349 rc = ahci_host_init(probe_ent);
... ... @@ -151,7 +151,7 @@
151 151 u32 hard_port_no;
152 152 u32 host_flags;
153 153 u32 host_set_flags;
154   - u32 mmio_base;
  154 + void __iomem *mmio_base;
155 155 u32 pio_mask;
156 156 u32 udma_mask;
157 157 u32 flags;
... ... @@ -160,8 +160,8 @@
160 160 u32 link_port_map; /*linkup port map*/
161 161 };
162 162  
163   -int ahci_init(u32 base);
164   -int ahci_reset(u32 base);
  163 +int ahci_init(void __iomem *base);
  164 +int ahci_reset(void __iomem *base);
165 165  
166 166 #endif