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Commit 9f4322fd2281d9736b9fd208a5e2ecaec49e21e0

Authored by Jagannadha Sutradharudu Teki
1 parent 5bb30f1a40
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sf: Divide flash register ops from QEB code 

QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Showing 3 changed files with 77 additions and 53 deletions Side-by-side Diff

drivers/mtd/spi/sf_internal.h
Diff comments   View file @ 9f4322f
... ... @@ -101,14 +101,17 @@
101 101 /* Flash erase(sectors) operation, support all possible erase commands */
102 102 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
103 103  
  104 +/* Read the status register */
  105 +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
  106 +
104 107 /* Program the status register */
105 108 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
106 109  
107   -/* Set quad enbale bit for macronix flashes */
108   -int spi_flash_set_qeb_mxic(struct spi_flash *flash);
  110 +/* Read the config register */
  111 +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
109 112  
110   -/* Set quad enbale bit for winbond and spansion flashes */
111   -int spi_flash_set_qeb_winspan(struct spi_flash *flash);
  113 +/* Program the config register */
  114 +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
112 115  
113 116 /* Enable writing on the SPI flash */
114 117 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
drivers/mtd/spi/sf_ops.c
Diff comments   View file @ 9f4322f
... ... @@ -24,94 +24,71 @@
24 24 cmd[3] = addr >> 0;
25 25 }
26 26  
27   -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  27 +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
28 28 {
29   - u8 cmd;
30 29 int ret;
  30 + u8 cmd;
31 31  
32   - cmd = CMD_WRITE_STATUS;
33   - ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
  32 + cmd = CMD_READ_STATUS;
  33 + ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
34 34 if (ret < 0) {
35   - debug("SF: fail to write status register\n");
  35 + debug("SF: fail to read status register\n");
36 36 return ret;
37 37 }
38 38  
39 39 return 0;
40 40 }
41 41  
42   -#ifdef CONFIG_SPI_FLASH_MACRONIX
43   -int spi_flash_set_qeb_mxic(struct spi_flash *flash)
  42 +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
44 43 {
45   - u8 qeb_status;
46 44 u8 cmd;
47 45 int ret;
48 46  
49   - cmd = CMD_READ_STATUS;
50   - ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
  47 + cmd = CMD_WRITE_STATUS;
  48 + ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
51 49 if (ret < 0) {
52   - debug("SF: fail to read status register\n");
  50 + debug("SF: fail to write status register\n");
53 51 return ret;
54 52 }
55 53  
56   - if (qeb_status & STATUS_QEB_MXIC) {
57   - debug("SF: Quad enable bit is already set\n");
58   - } else {
59   - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
60   - if (ret < 0)
61   - return ret;
62   - }
63   -
64   - return ret;
  54 + return 0;
65 55 }
66   -#endif
67 56  
68 57 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
69   -static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
  58 +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
70 59 {
71   - u8 data[2];
72   - u8 cmd;
73 60 int ret;
  61 + u8 cmd;
74 62  
75   - cmd = CMD_READ_STATUS;
76   - ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
  63 + cmd = CMD_READ_CONFIG;
  64 + ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
77 65 if (ret < 0) {
78   - debug("SF: fail to read status register\n");
  66 + debug("SF: fail to read config register\n");
79 67 return ret;
80 68 }
81 69  
82   - cmd = CMD_WRITE_STATUS;
83   - data[1] = cr;
84   - ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
85   - if (ret) {
86   - debug("SF: fail to write config register\n");
87   - return ret;
88   - }
89   -
90 70 return 0;
91 71 }
92 72  
93   -int spi_flash_set_qeb_winspan(struct spi_flash *flash)
  73 +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
94 74 {
95   - u8 qeb_status;
  75 + u8 data[2];
96 76 u8 cmd;
97 77 int ret;
98 78  
99   - cmd = CMD_READ_CONFIG;
100   - ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
101   - if (ret < 0) {
102   - debug("SF: fail to read config register\n");
  79 + ret = spi_flash_cmd_read_status(flash, &data[0]);
  80 + if (ret < 0)
103 81 return ret;
104   - }
105 82  
106   - if (qeb_status & STATUS_QEB_WINSPAN) {
107   - debug("SF: Quad enable bit is already set\n");
108   - } else {
109   - ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
110   - if (ret < 0)
111   - return ret;
  83 + cmd = CMD_WRITE_STATUS;
  84 + data[1] = wc;
  85 + ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
  86 + if (ret) {
  87 + debug("SF: fail to write config register\n");
  88 + return ret;
112 89 }
113 90  
114   - return ret;
  91 + return 0;
115 92 }
116 93 #endif
117 94  
drivers/mtd/spi/sf_probe.c
Diff comments   View file @ 9f4322f
... ... @@ -28,6 +28,50 @@
28 28 CMD_READ_QUAD_IO_FAST,
29 29 };
30 30  
  31 +#ifdef CONFIG_SPI_FLASH_MACRONIX
  32 +static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
  33 +{
  34 + u8 qeb_status;
  35 + int ret;
  36 +
  37 + ret = spi_flash_cmd_read_status(flash, &qeb_status);
  38 + if (ret < 0)
  39 + return ret;
  40 +
  41 + if (qeb_status & STATUS_QEB_MXIC) {
  42 + debug("SF: mxic: QEB is already set\n");
  43 + } else {
  44 + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
  45 + if (ret < 0)
  46 + return ret;
  47 + }
  48 +
  49 + return ret;
  50 +}
  51 +#endif
  52 +
  53 +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  54 +static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
  55 +{
  56 + u8 qeb_status;
  57 + int ret;
  58 +
  59 + ret = spi_flash_cmd_read_config(flash, &qeb_status);
  60 + if (ret < 0)
  61 + return ret;
  62 +
  63 + if (qeb_status & STATUS_QEB_WINSPAN) {
  64 + debug("SF: winspan: QEB is already set\n");
  65 + } else {
  66 + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
  67 + if (ret < 0)
  68 + return ret;
  69 + }
  70 +
  71 + return ret;
  72 +}
  73 +#endif
  74 +
31 75 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
32 76 {
33 77 switch (idcode0) {