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Commit 9fa32b12370236a39090d4e42b013910d123db61

Authored by Vikas Manocha
Committed by Tom Rini
1 parent 32fdf0e4d8
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

stv0991: Add basic stv0991 architecture support 

stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add arch/arm/cpu/armv7/Makefile hunk]
Signed-off-by: Tom Rini <trini@ti.com>

Showing 22 changed files with 764 additions and 0 deletions Side-by-side Diff

... ... @@ -128,6 +128,12 @@
128 128 F: arch/arm/cpu/arm926ejs/spear/
129 129 F: arch/arm/include/asm/arch-spear/
130 130  
  131 +ARM STM STV0991
  132 +M: Vikas Manocha <vikas.manocha@st.com>
  133 +S: Maintained
  134 +F: arch/arm/cpu/armv7/stv0991/
  135 +F: arch/arm/include/asm/arch-stv0991/
  136 +
131 137 ARM SUNXI
132 138 M: Ian Campbell <ijc@hellion.org.uk>
133 139 M: Hans De Goede <hdegoede@redhat.com>
... ... @@ -341,6 +341,10 @@
341 341 bool "Support spear600"
342 342 select CPU_ARM926EJS
343 343  
  344 +config TARGET_STV0991
  345 + bool "Support stv0991"
  346 + select CPU_V7
  347 +
344 348 config TARGET_X600
345 349 bool "Support x600"
346 350 select CPU_ARM926EJS
... ... @@ -953,6 +957,7 @@
953 957 source "board/spear/x600/Kconfig"
954 958 source "board/st-ericsson/snowball/Kconfig"
955 959 source "board/st-ericsson/u8500/Kconfig"
  960 +source "board/st/stv0991/Kconfig"
956 961 source "board/sunxi/Kconfig"
957 962 source "board/syteco/jadecpu/Kconfig"
958 963 source "board/syteco/zmx25/Kconfig"
arch/arm/cpu/armv7/Makefile
Diff comments   View file @ 9fa32b1
... ... @@ -56,6 +56,7 @@
56 56 obj-$(CONFIG_RMOBILE) += rmobile/
57 57 obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
58 58 obj-$(CONFIG_SOCFPGA) += socfpga/
  59 +obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
59 60 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
60 61 obj-$(CONFIG_TEGRA20) += tegra20/
61 62 obj-$(CONFIG_U8500) += u8500/
arch/arm/cpu/armv7/stv0991/Makefile
Diff comments   View file @ 9fa32b1
  1 +#
  2 +# (C) Copyright 2014
  3 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := timer.o clock.o pinmux.o reset.o
  9 +obj-y += lowlevel.o
arch/arm/cpu/armv7/stv0991/clock.c
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <asm/io.h>
  9 +#include <asm/arch/hardware.h>
  10 +#include <asm/arch/stv0991_cgu.h>
  11 +#include<asm/arch/stv0991_periph.h>
  12 +
  13 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
  14 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
  15 +
  16 +void clock_setup(int peripheral)
  17 +{
  18 + switch (peripheral) {
  19 + case UART_CLOCK_CFG:
  20 + writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
  21 + break;
  22 + case ETH_CLOCK_CFG:
  23 + break;
  24 + default:
  25 + break;
  26 + }
  27 +}
arch/arm/cpu/armv7/stv0991/lowlevel.S
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014 stmicroelectronics
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +#include <linux/linkage.h>
  9 +
  10 +ENTRY(lowlevel_init)
  11 + mov pc, lr
  12 +ENDPROC(lowlevel_init)
arch/arm/cpu/armv7/stv0991/pinmux.c
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <asm/io.h>
  9 +#include <asm/arch/stv0991_creg.h>
  10 +#include <asm/arch/stv0991_periph.h>
  11 +#include <asm/arch/hardware.h>
  12 +
  13 +static struct stv0991_creg *const stv0991_creg = \
  14 + (struct stv0991_creg *)CREG_BASE_ADDR;
  15 +
  16 +int stv0991_pinmux_config(int peripheral)
  17 +{
  18 + switch (peripheral) {
  19 + case UART_GPIOC_30_31:
  20 + /* SSDA/SSCL pad muxing to UART Rx/Dx */
  21 + writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
  22 + CFG_GPIOC_31_UART_RX,
  23 + &stv0991_creg->mux12);
  24 + writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
  25 + CFG_GPIOC_30_UART_TX,
  26 + &stv0991_creg->mux12);
  27 + /* SSDA/SSCL pad config to push pull*/
  28 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
  29 + CFG_GPIOC_31_MODE_PP,
  30 + &stv0991_creg->cfg_pad6);
  31 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
  32 + CFG_GPIOC_30_MODE_HIGH,
  33 + &stv0991_creg->cfg_pad6);
  34 + break;
  35 + case UART_GPIOB_16_17:
  36 + /* ethernet rx_6/7 to UART Rx/Dx */
  37 + writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
  38 + CFG_GPIOB_17_UART_RX,
  39 + &stv0991_creg->mux7);
  40 + writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
  41 + CFG_GPIOB_16_UART_TX,
  42 + &stv0991_creg->mux7);
  43 + break;
  44 + default:
  45 + break;
  46 + }
  47 + return 0;
  48 +}
arch/arm/cpu/armv7/stv0991/reset.c
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/stv0991_wdru.h>
  11 +void reset_cpu(ulong ignored)
  12 +{
  13 + puts("System is going to reboot ...\n");
  14 + /*
  15 + * This 1 second delay will allow the above message
  16 + * to be printed before reset
  17 + */
  18 + udelay((1000 * 1000));
  19 +
  20 + /* Setting bit 1 of the WDRU unit will reset the SoC */
  21 + writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
  22 +
  23 + /* system will restart */
  24 + while (1)
  25 + ;
  26 +}
arch/arm/cpu/armv7/stv0991/timer.c
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch-stv0991/hardware.h>
  11 +#include <asm/arch-stv0991/stv0991_cgu.h>
  12 +#include <asm/arch-stv0991/stv0991_gpt.h>
  13 +
  14 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
  15 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
  16 +
  17 +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
  18 +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +#define timestamp gd->arch.tbl
  23 +#define lastdec gd->arch.lastinc
  24 +
  25 +int timer_init(void)
  26 +{
  27 + /* Timer1 clock configuration */
  28 + writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
  29 + writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
  30 + TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
  31 +
  32 + /* Stop the timer */
  33 + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
  34 + writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
  35 + /* Configure timer for auto-reload */
  36 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
  37 + &gpt1_regs_ptr->cr1);
  38 +
  39 + /* load value for free running */
  40 + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
  41 +
  42 + /* start timer */
  43 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
  44 + &gpt1_regs_ptr->cr1);
  45 +
  46 + /* Reset the timer */
  47 + lastdec = READ_TIMER();
  48 + timestamp = 0;
  49 +
  50 + return 0;
  51 +}
  52 +
  53 +/*
  54 + * timer without interrupts
  55 + */
  56 +ulong get_timer(ulong base)
  57 +{
  58 + return (get_timer_masked() / GPT_RESOLUTION) - base;
  59 +}
  60 +
  61 +void __udelay(unsigned long usec)
  62 +{
  63 + ulong tmo;
  64 + ulong start = get_timer_masked();
  65 + ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
  66 + ulong rndoff;
  67 +
  68 + rndoff = (usec % 10) ? 1 : 0;
  69 +
  70 + /* tenudelcnt timer tick gives 10 microsecconds delay */
  71 + tmo = ((usec / 10) + rndoff) * tenudelcnt;
  72 +
  73 + while ((ulong) (get_timer_masked() - start) < tmo)
  74 + ;
  75 +}
  76 +
  77 +ulong get_timer_masked(void)
  78 +{
  79 + ulong now = READ_TIMER();
  80 +
  81 + if (now >= lastdec) {
  82 + /* normal mode */
  83 + timestamp += now - lastdec;
  84 + } else {
  85 + /* we have an overflow ... */
  86 + timestamp += now + GPT_FREE_RUNNING - lastdec;
  87 + }
  88 + lastdec = now;
  89 +
  90 + return timestamp;
  91 +}
  92 +
  93 +void udelay_masked(unsigned long usec)
  94 +{
  95 + return udelay(usec);
  96 +}
  97 +
  98 +/*
  99 + * This function is derived from PowerPC code (read timebase as long long).
  100 + * On ARM it just returns the timer value.
  101 + */
  102 +unsigned long long get_ticks(void)
  103 +{
  104 + return get_timer(0);
  105 +}
  106 +
  107 +/*
  108 + * This function is derived from PowerPC code (timebase clock frequency).
  109 + * On ARM it returns the number of timer ticks per second.
  110 + */
  111 +ulong get_tbclk(void)
  112 +{
  113 + return CONFIG_STV0991_HZ;
  114 +}
arch/arm/include/asm/arch-stv0991/hardware.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _ASM_ARCH_HARDWARE_H
  9 +#define _ASM_ARCH_HARDWARE_H
  10 +
  11 +/* STV0991 */
  12 +#define SRAM0_BASE_ADDR 0x00000000UL
  13 +#define SRAM1_BASE_ADDR 0x00068000UL
  14 +#define SRAM2_BASE_ADDR 0x000D0000UL
  15 +#define SRAM3_BASE_ADDR 0x00138000UL
  16 +#define CFS_SRAM0_BASE_ADDR 0x00198000UL
  17 +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
  18 +#define FAST_SRAM_BASE_ADDR 0x001D8000UL
  19 +#define FLASH_BASE_ADDR 0x40000000UL
  20 +#define PL310_BASE_ADDR 0x70000000UL
  21 +#define HSAXIM_BASE_ADDR 0x70100000UL
  22 +#define IMGSS_BASE_ADDR 0x70200000UL
  23 +#define ADC_BASE_ADDR 0x80000000UL
  24 +#define GPIOA_BASE_ADDR 0x80001000UL
  25 +#define GPIOB_BASE_ADDR 0x80002000UL
  26 +#define GPIOC_BASE_ADDR 0x80003000UL
  27 +#define HDM_BASE_ADDR 0x80004000UL
  28 +#define THSENS_BASE_ADDR 0x80200000UL
  29 +#define GPTIMER2_BASE_ADDR 0x80201000UL
  30 +#define GPTIMER1_BASE_ADDR 0x80202000UL
  31 +#define QSPI_BASE_ADDR 0x80203000UL
  32 +#define CGU_BASE_ADDR 0x80204000UL
  33 +#define CREG_BASE_ADDR 0x80205000UL
  34 +#define PEC_BASE_ADDR 0x80206000UL
  35 +#define WDRU_BASE_ADDR 0x80207000UL
  36 +#define BSEC_BASE_ADDR 0x80208000UL
  37 +#define DAP_ROM_BASE_ADDR 0x80210000UL
  38 +#define SOC_CTI_BASE_ADDR 0x80211000UL
  39 +#define TPIU_BASE_ADDR 0x80212000UL
  40 +#define TMC_ETF_BASE_ADDR 0x80213000UL
  41 +#define R4_ETM_BASE_ADDR 0x80214000UL
  42 +#define R4_CTI_BASE_ADDR 0x80215000UL
  43 +#define R4_DBG_BASE_ADDR 0x80216000UL
  44 +#define GMAC_BASE_ADDR 0x80300000UL
  45 +#define RNSS_BASE_ADDR 0x80302000UL
  46 +#define CRYP_BASE_ADDR 0x80303000UL
  47 +#define HASH_BASE_ADDR 0x80304000UL
  48 +#define GPDMA_BASE_ADDR 0x80305000UL
  49 +#define ISA_BASE_ADDR 0x8032A000UL
  50 +#define HCI_BASE_ADDR 0x80400000UL
  51 +#define I2C1_BASE_ADDR 0x80401000UL
  52 +#define I2C2_BASE_ADDR 0x80402000UL
  53 +#define SAI_BASE_ADDR 0x80403000UL
  54 +#define USI_BASE_ADDR 0x80404000UL
  55 +#define SPI1_BASE_ADDR 0x80405000UL
  56 +#define UART_BASE_ADDR 0x80406000UL
  57 +#define SPI2_BASE_ADDR 0x80500000UL
  58 +#define CAN_BASE_ADDR 0x80501000UL
  59 +#define USART1_BASE_ADDR 0x80502000UL
  60 +#define USART2_BASE_ADDR 0x80503000UL
  61 +#define USART3_BASE_ADDR 0x80504000UL
  62 +#define USART4_BASE_ADDR 0x80505000UL
  63 +#define USART5_BASE_ADDR 0x80506000UL
  64 +#define USART6_BASE_ADDR 0x80507000UL
  65 +#define SDI2_BASE_ADDR 0x80600000UL
  66 +#define SDI1_BASE_ADDR 0x80601000UL
  67 +#define VICA_BASE_ADDR 0x81000000UL
  68 +#define VICB_BASE_ADDR 0x81001000UL
  69 +#define STM_CHANNELS_BASE_ADDR 0x81100000UL
  70 +#define STM_BASE_ADDR 0x81110000UL
  71 +#define SROM_BASE_ADDR 0xFFFF0000UL
  72 +
  73 +#endif /* _ASM_ARCH_HARDWARE_H */
arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _STV0991_CGU_H
  9 +#define _STV0991_CGU_H
  10 +
  11 +struct stv0991_cgu_regs {
  12 + u32 cpu_freq; /* offset 0x0 */
  13 + u32 icn2_freq; /* offset 0x4 */
  14 + u32 dma_freq; /* offset 0x8 */
  15 + u32 isp_freq; /* offset 0xc */
  16 + u32 h264_freq; /* offset 0x10 */
  17 + u32 osif_freq; /* offset 0x14 */
  18 + u32 ren_freq; /* offset 0x18 */
  19 + u32 tim_freq; /* offset 0x1c */
  20 + u32 sai_freq; /* offset 0x20 */
  21 + u32 eth_freq; /* offset 0x24 */
  22 + u32 i2c_freq; /* offset 0x28 */
  23 + u32 spi_freq; /* offset 0x2c */
  24 + u32 uart_freq; /* offset 0x30 */
  25 + u32 qspi_freq; /* offset 0x34 */
  26 + u32 sdio_freq; /* offset 0x38 */
  27 + u32 usi_freq; /* offset 0x3c */
  28 + u32 can_line_freq; /* offset 0x40 */
  29 + u32 debug_freq; /* offset 0x44 */
  30 + u32 trace_freq; /* offset 0x48 */
  31 + u32 stm_freq; /* offset 0x4c */
  32 + u32 eth_ctrl; /* offset 0x50 */
  33 + u32 reserved[3]; /* offset 0x54 */
  34 + u32 osc_ctrl; /* offset 0x60 */
  35 + u32 pll1_ctrl; /* offset 0x64 */
  36 + u32 pll1_freq; /* offset 0x68 */
  37 + u32 pll1_fract; /* offset 0x6c */
  38 + u32 pll1_spread; /* offset 0x70 */
  39 + u32 pll1_status; /* offset 0x74 */
  40 + u32 pll2_ctrl; /* offset 0x78 */
  41 + u32 pll2_freq; /* offset 0x7c */
  42 + u32 pll2_fract; /* offset 0x80 */
  43 + u32 pll2_spread; /* offset 0x84 */
  44 + u32 pll2_status; /* offset 0x88 */
  45 + u32 cgu_enable_1; /* offset 0x8c */
  46 + u32 cgu_enable_2; /* offset 0x90 */
  47 + u32 cgu_isp_pulse; /* offset 0x94 */
  48 + u32 cgu_h264_pulse; /* offset 0x98 */
  49 + u32 cgu_osif_pulse; /* offset 0x9c */
  50 + u32 cgu_ren_pulse; /* offset 0xa0 */
  51 +
  52 +};
  53 +
  54 +/* CGU Timer */
  55 +#define CLK_TMR_OSC 0
  56 +#define CLK_TMR_MCLK 1
  57 +#define CLK_TMR_PLL1 2
  58 +#define CLK_TMR_PLL2 3
  59 +#define MDIV_SHIFT_TMR 3
  60 +#define DIV_SHIFT_TMR 6
  61 +
  62 +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
  63 + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
  64 +
  65 +/* Clock Enable/Disable */
  66 +
  67 +#define TIMER1_CLK_EN (1 << 15)
  68 +
  69 +/* CGU Uart config */
  70 +#define CLK_UART_MCLK 0
  71 +#define CLK_UART_PLL1 1
  72 +#define CLK_UART_PLL2 2
  73 +
  74 +#define MDIV_SHIFT_UART 3
  75 +#define DIV_SHIFT_UART 6
  76 +
  77 +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
  78 + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
  79 +
  80 +#endif
arch/arm/include/asm/arch-stv0991/stv0991_creg.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _STV0991_CREG_H
  9 +#define _STV0991_CREG_H
  10 +
  11 +struct stv0991_creg {
  12 + u32 version; /* offset 0x0 */
  13 + u32 hdpctl; /* offset 0x4 */
  14 + u32 hdpval; /* offset 0x8 */
  15 + u32 hdpgposet; /* offset 0xc */
  16 + u32 hdpgpoclr; /* offset 0x10 */
  17 + u32 hdpgpoval; /* offset 0x14 */
  18 + u32 stm_mux; /* offset 0x18 */
  19 + u32 sysctrl_1; /* offset 0x1c */
  20 + u32 sysctrl_2; /* offset 0x20 */
  21 + u32 sysctrl_3; /* offset 0x24 */
  22 + u32 sysctrl_4; /* offset 0x28 */
  23 + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
  24 + u32 mux1; /* offset 0x100 */
  25 + u32 mux2; /* offset 0x104 */
  26 + u32 mux3; /* offset 0x108 */
  27 + u32 mux4; /* offset 0x10c */
  28 + u32 mux5; /* offset 0x110 */
  29 + u32 mux6; /* offset 0x114 */
  30 + u32 mux7; /* offset 0x118 */
  31 + u32 mux8; /* offset 0x11c */
  32 + u32 mux9; /* offset 0x120 */
  33 + u32 mux10; /* offset 0x124 */
  34 + u32 mux11; /* offset 0x128 */
  35 + u32 mux12; /* offset 0x12c */
  36 + u32 mux13; /* offset 0x130 */
  37 + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
  38 + u32 cfg_pad1; /* offset 0x200 */
  39 + u32 cfg_pad2; /* offset 0x204 */
  40 + u32 cfg_pad3; /* offset 0x208 */
  41 + u32 cfg_pad4; /* offset 0x20c */
  42 + u32 cfg_pad5; /* offset 0x210 */
  43 + u32 cfg_pad6; /* offset 0x214 */
  44 + u32 cfg_pad7; /* offset 0x218 */
  45 + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
  46 + u32 vdd_pad1; /* offset 0x300 */
  47 + u32 vdd_pad2; /* offset 0x304 */
  48 + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
  49 + u32 vdd_comp1; /* offset 0x400 */
  50 +};
  51 +
  52 +/* CREG MUX 12 register */
  53 +#define GPIOC_30_MUX_SHIFT 24
  54 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
  55 +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
  56 +
  57 +#define GPIOC_31_MUX_SHIFT 28
  58 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
  59 +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
  60 +
  61 +/* CREG MUX 7 register */
  62 +#define GPIOB_16_MUX_SHIFT 0
  63 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
  64 +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
  65 +
  66 +#define GPIOB_17_MUX_SHIFT 4
  67 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
  68 +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
  69 +
  70 +/* CREG CFG_PAD6 register */
  71 +
  72 +#define GPIOC_31_MODE_SHIFT 30
  73 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
  74 +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
  75 +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
  76 +
  77 +#define GPIOC_30_MODE_SHIFT 28
  78 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
  79 +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
  80 +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
  81 +
  82 +#endif
arch/arm/include/asm/arch-stv0991/stv0991_defs.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __STV0991_DEFS_H__
  9 +#define __STV0991_DEFS_H__
  10 +#include <asm/arch/stv0991_periph.h>
  11 +
  12 +extern int stv0991_pinmux_config(enum periph_id);
  13 +extern int clock_setup(enum periph_clock);
  14 +
  15 +#endif
arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _STV0991_GPT_H
  9 +#define _STV0991_GPT_H
  10 +
  11 +#include <asm/arch-stv0991/hardware.h>
  12 +
  13 +struct gpt_regs {
  14 + u32 cr1;
  15 + u32 cr2;
  16 + u32 reserved_1;
  17 + u32 dier; /* dma_int_en */
  18 + u32 sr; /* status reg */
  19 + u32 egr; /* event gen */
  20 + u32 reserved_2[3]; /* offset 0x18--0x20*/
  21 + u32 cnt;
  22 + u32 psc;
  23 + u32 arr;
  24 +};
  25 +
  26 +struct gpt_regs *const gpt1_regs_ptr =
  27 + (struct gpt_regs *) GPTIMER1_BASE_ADDR;
  28 +
  29 +/* Timer control1 register */
  30 +#define GPT_CR1_CEN 0x0001
  31 +#define GPT_MODE_AUTO_RELOAD (1 << 7)
  32 +
  33 +/* Timer prescalar reg */
  34 +#define GPT_PRESCALER_128 0x128
  35 +
  36 +/* Auto reload register for free running config */
  37 +#define GPT_FREE_RUNNING 0xFFFF
  38 +
  39 +/* Timer, HZ specific defines */
  40 +#define CONFIG_STV0991_HZ 1000
  41 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
  42 +
  43 +#endif
arch/arm/include/asm/arch-stv0991/stv0991_periph.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARM_ARCH_PERIPH_H
  9 +#define __ASM_ARM_ARCH_PERIPH_H
  10 +
  11 +/*
  12 + * Peripherals required for pinmux configuration. List will
  13 + * grow with support for more devices getting added.
  14 + * Numbering based on interrupt table.
  15 + *
  16 + */
  17 +enum periph_id {
  18 + UART_GPIOC_30_31 = 0,
  19 + UART_GPIOB_16_17,
  20 + PERIPH_ID_I2C0,
  21 + PERIPH_ID_I2C1,
  22 + PERIPH_ID_I2C2,
  23 + PERIPH_ID_I2C3,
  24 + PERIPH_ID_I2C4,
  25 + PERIPH_ID_I2C5,
  26 + PERIPH_ID_I2C6,
  27 + PERIPH_ID_I2C7,
  28 + PERIPH_ID_SPI0,
  29 + PERIPH_ID_SPI1,
  30 + PERIPH_ID_SPI2,
  31 + PERIPH_ID_SDMMC0,
  32 + PERIPH_ID_SDMMC1,
  33 + PERIPH_ID_SDMMC2,
  34 + PERIPH_ID_SDMMC3,
  35 + PERIPH_ID_I2S1,
  36 +};
  37 +
  38 +enum periph_clock {
  39 + UART_CLOCK_CFG = 0,
  40 + ETH_CLOCK_CFG,
  41 +};
  42 +
  43 +#endif /* __ASM_ARM_ARCH_PERIPH_H */
arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _STV0991_WD_RST_H
  9 +#define _STV0991_WD_RST_H
  10 +#include <asm/arch-stv0991/hardware.h>
  11 +
  12 +struct stv0991_wd_ru {
  13 + u32 wdru_config;
  14 + u32 wdru_ctrl1;
  15 + u32 wdru_ctrl2;
  16 + u32 wdru_tim;
  17 + u32 wdru_count;
  18 + u32 wdru_stat;
  19 + u32 wdru_wrlock;
  20 +};
  21 +
  22 +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
  23 + (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
  24 +
  25 +/* Watchdog control register */
  26 +#define WDRU_RST_SYS 0x1
  27 +
  28 +#endif
board/st/stv0991/Kconfig
Diff comments   View file @ 9fa32b1
  1 +if TARGET_STV0991
  2 +
  3 +config SYS_CPU
  4 + string
  5 + default "armv7"
  6 +
  7 +config SYS_BOARD
  8 + string
  9 + default "stv0991"
  10 +
  11 +config SYS_VENDOR
  12 + string
  13 + default "st"
  14 +
  15 +config SYS_SOC
  16 + string
  17 + default "stv0991"
  18 +
  19 +config SYS_CONFIG_NAME
  20 + string
  21 + default "stv0991"
  22 +
  23 +endif
board/st/stv0991/MAINTAINERS
Diff comments   View file @ 9fa32b1
  1 +STV0991 APPLICATION BOARD
  2 +M: Vikas Manocha <vikas.manocha@st.com>
  3 +S: Maintained
  4 +F: board/st/stv0991/
  5 +F: include/configs/stv0991.h
board/st/stv0991/Makefile
Diff comments   View file @ 9fa32b1
  1 +#
  2 +# (C) Copyright 2014
  3 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := stv0991.o
board/st/stv0991/stv0991.c
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <miiphy.h>
  10 +#include <asm/arch/stv0991_periph.h>
  11 +#include <asm/arch/stv0991_defs.h>
  12 +
  13 +DECLARE_GLOBAL_DATA_PTR;
  14 +
  15 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
  16 +void show_boot_progress(int progress)
  17 +{
  18 + printf("%i\n", progress);
  19 +}
  20 +#endif
  21 +
  22 +/*
  23 + * Miscellaneous platform dependent initialisations
  24 + */
  25 +int board_init(void)
  26 +{
  27 + return 0;
  28 +}
  29 +
  30 +int board_uart_init(void)
  31 +{
  32 + stv0991_pinmux_config(UART_GPIOC_30_31);
  33 + clock_setup(UART_CLOCK_CFG);
  34 + return 0;
  35 +}
  36 +#ifdef CONFIG_BOARD_EARLY_INIT_F
  37 +int board_early_init_f(void)
  38 +{
  39 + board_uart_init();
  40 + return 0;
  41 +}
  42 +#endif
  43 +
  44 +int dram_init(void)
  45 +{
  46 + gd->ram_size = PHYS_SDRAM_1_SIZE;
  47 + return 0;
  48 +}
  49 +
  50 +void dram_init_banksize(void)
  51 +{
  52 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  53 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  54 +}
configs/stv0991_defconfig
Diff comments   View file @ 9fa32b1
  1 +CONFIG_SYS_EXTRA_OPTIONS="stv0991"
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_STV0991=y
include/configs/stv0991.h
Diff comments   View file @ 9fa32b1
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __CONFIG_STV0991_H
  9 +#define __CONFIG_STV0991_H
  10 +
  11 +#define CONFIG_SYS_DCACHE_OFF
  12 +#define CONFIG_SYS_ICACHE_OFF
  13 +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  14 +#define CONFIG_BOARD_EARLY_INIT_F
  15 +#define CONFIG_SYS_CORTEX_R4
  16 +
  17 +#define CONFIG_SYS_GENERIC_BOARD
  18 +#define CONFIG_SYS_NO_FLASH
  19 +
  20 +/* ram memory-related information */
  21 +#define CONFIG_NR_DRAM_BANKS 1
  22 +#define PHYS_SDRAM_1 0x00000000
  23 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  24 +#define PHYS_SDRAM_1_SIZE 0x00198000
  25 +
  26 +#define CONFIG_ENV_SIZE 0x10000
  27 +#define CONFIG_ENV_IS_IN_FLASH
  28 +#define CONFIG_ENV_ADDR \
  29 + (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
  30 +#define CONFIG_SYS_MAXARGS 16
  31 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
  32 +
  33 +/* serial port (PL011) configuration */
  34 +#define CONFIG_SYS_SERIAL0 0x80406000
  35 +#define CONFIG_PL011_SERIAL
  36 +#define CONFIG_CONS_INDEX 0
  37 +#define CONFIG_BAUDRATE 115200
  38 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
  39 +#define CONFIG_PL011_CLOCK (2700 * 1000)
  40 +
  41 +/* user interface */
  42 +#define CONFIG_SYS_PROMPT "STV0991> "
  43 +#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */
  44 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
  45 + +sizeof(CONFIG_SYS_PROMPT) + 16)
  46 +
  47 +/* MISC */
  48 +#define CONFIG_SYS_LOAD_ADDR 0x00000000
  49 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
  50 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
  51 +#define CONFIG_SYS_INIT_SP_OFFSET \
  52 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  53 +/* U-boot Load Address */
  54 +#define CONFIG_SYS_TEXT_BASE 0x00010000
  55 +#define CONFIG_SYS_INIT_SP_ADDR \
  56 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  57 +
  58 +#endif /* __CONFIG_H */