Commit 9fa3d093d626b25c64c695e29d381dd2ae7bf8cc
Committed by
Stefano Babic
Stefano Babic
1 parent
31ac2d0c6a
Exists in
master
and in
54 other branches
ehci-mxc: Make i.MX25 EHCI configurable
Use EHCI MXC configuration options for i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Matthias Weisser <weisserm@arcor.de>
Showing 2 changed files with 67 additions and 11 deletions Side-by-side Diff
drivers/usb/host/ehci-mxc.c
| ... | ... | @@ -28,11 +28,22 @@ |
| 28 | 28 | |
| 29 | 29 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
| 30 | 30 | |
| 31 | -#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) | |
| 32 | -#define MX25_USB_CTRL_HSTD_BIT (1<<5) | |
| 33 | -#define MX25_USB_CTRL_USBTE_BIT (1<<4) | |
| 34 | -#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) | |
| 31 | +#define MX25_OTG_SIC_SHIFT 29 | |
| 32 | +#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) | |
| 33 | +#define MX25_OTG_PM_BIT (1 << 24) | |
| 34 | +#define MX25_OTG_PP_BIT (1 << 11) | |
| 35 | +#define MX25_OTG_OCPOL_BIT (1 << 3) | |
| 35 | 36 | |
| 37 | +#define MX25_H1_SIC_SHIFT 21 | |
| 38 | +#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) | |
| 39 | +#define MX25_H1_PP_BIT (1 << 18) | |
| 40 | +#define MX25_H1_PM_BIT (1 << 8) | |
| 41 | +#define MX25_H1_IPPUE_UP_BIT (1 << 7) | |
| 42 | +#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) | |
| 43 | +#define MX25_H1_TLL_BIT (1 << 5) | |
| 44 | +#define MX25_H1_USBTE_BIT (1 << 4) | |
| 45 | +#define MX25_H1_OCPOL_BIT (1 << 2) | |
| 46 | + | |
| 36 | 47 | #define MX31_OTG_SIC_SHIFT 29 |
| 37 | 48 | #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) |
| 38 | 49 | #define MX31_OTG_PM_BIT (1 << 24) |
| 39 | 50 | |
| 40 | 51 | |
| ... | ... | @@ -51,12 +62,57 @@ |
| 51 | 62 | { |
| 52 | 63 | unsigned int v; |
| 53 | 64 | |
| 54 | -#if defined(CONFIG_MX25) | |
| 55 | - v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | | |
| 56 | - MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; | |
| 57 | -#elif defined(CONFIG_MX31) | |
| 58 | 65 | v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); |
| 66 | +#if defined(CONFIG_MX25) | |
| 67 | + switch (port) { | |
| 68 | + case 0: /* OTG port */ | |
| 69 | + v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | | |
| 70 | + MX25_OTG_OCPOL_BIT); | |
| 71 | + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; | |
| 59 | 72 | |
| 73 | + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | |
| 74 | + v |= MX25_OTG_PM_BIT; | |
| 75 | + | |
| 76 | + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | |
| 77 | + v |= MX25_OTG_PP_BIT; | |
| 78 | + | |
| 79 | + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | |
| 80 | + v |= MX25_OTG_OCPOL_BIT; | |
| 81 | + | |
| 82 | + break; | |
| 83 | + case 1: /* H1 port */ | |
| 84 | + v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | | |
| 85 | + MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | | |
| 86 | + MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | | |
| 87 | + MX25_H1_IPPUE_UP_BIT); | |
| 88 | + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; | |
| 89 | + | |
| 90 | + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | |
| 91 | + v |= MX25_H1_PM_BIT; | |
| 92 | + | |
| 93 | + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | |
| 94 | + v |= MX25_H1_PP_BIT; | |
| 95 | + | |
| 96 | + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | |
| 97 | + v |= MX25_H1_OCPOL_BIT; | |
| 98 | + | |
| 99 | + if (!(flags & MXC_EHCI_TTL_ENABLED)) | |
| 100 | + v |= MX25_H1_TLL_BIT; | |
| 101 | + | |
| 102 | + if (flags & MXC_EHCI_INTERNAL_PHY) | |
| 103 | + v |= MX25_H1_USBTE_BIT; | |
| 104 | + | |
| 105 | + if (flags & MXC_EHCI_IPPUE_DOWN) | |
| 106 | + v |= MX25_H1_IPPUE_DOWN_BIT; | |
| 107 | + | |
| 108 | + if (flags & MXC_EHCI_IPPUE_UP) | |
| 109 | + v |= MX25_H1_IPPUE_UP_BIT; | |
| 110 | + | |
| 111 | + break; | |
| 112 | + default: | |
| 113 | + return -EINVAL; | |
| 114 | + } | |
| 115 | +#elif defined(CONFIG_MX31) | |
| 60 | 116 | switch (port) { |
| 61 | 117 | case 0: /* OTG port */ |
| 62 | 118 | v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); |
include/configs/zmx25.h
| ... | ... | @@ -109,9 +109,9 @@ |
| 109 | 109 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ |
| 110 | 110 | #define CONFIG_USB_EHCI_MXC |
| 111 | 111 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 112 | -#define CONFIG_MXC_USB_PORT 2 | |
| 113 | -#define CONFIG_MXC_USB_PORTSC 0xC0000000 | |
| 114 | -#define CONFIG_MXC_USB_FLAGS 0 | |
| 112 | +#define CONFIG_MXC_USB_PORT 1 | |
| 113 | +#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL | |
| 114 | +#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) | |
| 115 | 115 | #define CONFIG_EHCI_IS_TDI |
| 116 | 116 | #define CONFIG_USB_STORAGE |
| 117 | 117 | #define CONFIG_DOS_PARTITION |