Eric Lee / smarc-uboot

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Commit 9fa89220efab2cf36b95b440eeb34fbe1479dcc6

Authored by Ye Li
1 parent a3602fbc7b
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18458-2 mx6ull_arm2: Add 14x14 DDR3 ARM2 support 

Porting the iMX6ULL 14x14 DDR3 ARM2 board codes from v2017.03.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 7 changed files with 1569 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ 9fa8922
... ... @@ -424,6 +424,13 @@
424 424 select SPL_SEPARATE_BSS if SPL
425 425 select SPL_PINCTRL if SPL
426 426  
  427 +config TARGET_MX6ULL_DDR3_ARM2
  428 + bool "Support mx6ull_ddr3_arm2"
  429 + select BOARD_LATE_INIT
  430 + select MX6ULL
  431 + select DM
  432 + select DM_THERMAL
  433 +
427 434 config TARGET_MX6ULL_9X9_EVK
428 435 bool "Support mx6ull_9x9_evk"
429 436 select BOARD_LATE_INIT
... ... @@ -588,6 +595,7 @@
588 595 source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
589 596 source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
590 597 source "board/freescale/mx6ullevk/Kconfig"
  598 +source "board/freescale/mx6ull_ddr3_arm2/Kconfig"
591 599 source "board/grinn/liteboard/Kconfig"
592 600 source "board/phytec/pcm058/Kconfig"
593 601 source "board/phytec/pfla02/Kconfig"
board/freescale/mx6ull_ddr3_arm2/Kconfig
Diff comments   View file @ 9fa8922
  1 +if TARGET_MX6ULL_DDR3_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx6ull_ddr3_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx6ull_ddr3_arm2"
  11 +
  12 +config MX6ULL_DDR3_ARM2_EMMC_REWORK
  13 + bool "Select this for the board with eMMC rework"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0x87800000
  17 +
  18 +config MX6ULL_DDR3_ARM2_TSC_REWORK
  19 + bool "Select this for the board with screen touch rework"
  20 +
  21 +config MX6ULL_DDR3_ARM2_QSPIB_REWORK
  22 + bool "Select this for the board with flash on QSPI-B port rework"
  23 +
  24 +endif
board/freescale/mx6ull_ddr3_arm2/Makefile
Diff comments   View file @ 9fa8922
  1 +# (C) Copyright 2016 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx6ull_ddr3_arm2.o
board/freescale/mx6ull_ddr3_arm2/imximage.cfg
Diff comments   View file @ 9fa8922
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_QSPI_BOOT
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_NOR_BOOT)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6ull_ddr3_arm2/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x020c4068 0xffffffff
  54 +DATA 4 0x020c406c 0xffffffff
  55 +DATA 4 0x020c4070 0xffffffff
  56 +DATA 4 0x020c4074 0xffffffff
  57 +DATA 4 0x020c4078 0xffffffff
  58 +DATA 4 0x020c407c 0xffffffff
  59 +DATA 4 0x020c4080 0xffffffff
  60 +
  61 +DATA 4 0x020E04B4 0x000C0000
  62 +DATA 4 0x020E04AC 0x00000000
  63 +DATA 4 0x020E027C 0x00000030
  64 +DATA 4 0x020E0250 0x00000030
  65 +DATA 4 0x020E024C 0x00000030
  66 +DATA 4 0x020E0490 0x00000030
  67 +DATA 4 0x020E0288 0x000C0030
  68 +DATA 4 0x020E0270 0x00000000
  69 +DATA 4 0x020E0260 0x00000030
  70 +DATA 4 0x020E0264 0x00000030
  71 +DATA 4 0x020E04A0 0x00000030
  72 +DATA 4 0x020E0494 0x00020000
  73 +DATA 4 0x020E0280 0x00000030
  74 +DATA 4 0x020E0284 0x00000030
  75 +DATA 4 0x020E04B0 0x00020000
  76 +DATA 4 0x020E0498 0x00000030
  77 +DATA 4 0x020E04A4 0x00000030
  78 +DATA 4 0x020E0244 0x00000030
  79 +DATA 4 0x020E0248 0x00000030
  80 +DATA 4 0x021B001C 0x00008000
  81 +DATA 4 0x021B0800 0xA1390003
  82 +DATA 4 0x021B080C 0x00150019
  83 +DATA 4 0x021B083C 0x41550153
  84 +DATA 4 0x021B0848 0x40403A3E
  85 +DATA 4 0x021B0850 0x40402F2A
  86 +DATA 4 0x021B081C 0x33333333
  87 +DATA 4 0x021B0820 0x33333333
  88 +DATA 4 0x021B082C 0xf3333333
  89 +DATA 4 0x021B0830 0xf3333333
  90 +DATA 4 0x021B08C0 0x00944009
  91 +DATA 4 0x021B08b8 0x00000800
  92 +DATA 4 0x021B0004 0x0002002D
  93 +DATA 4 0x021B0008 0x1B333030
  94 +DATA 4 0x021B000C 0x676B52F3
  95 +DATA 4 0x021B0010 0xB66D0B63
  96 +DATA 4 0x021B0014 0x01FF00DB
  97 +DATA 4 0x021B0018 0x00211740
  98 +DATA 4 0x021B001C 0x00008000
  99 +DATA 4 0x021B002C 0x000026D2
  100 +DATA 4 0x021B0030 0x006B1023
  101 +DATA 4 0x021B0040 0x0000005F
  102 +DATA 4 0x021B0000 0x85180000
  103 +DATA 4 0x021B0890 0x00400000
  104 +DATA 4 0x021B001C 0x02008032
  105 +DATA 4 0x021B001C 0x00008033
  106 +DATA 4 0x021B001C 0x00048031
  107 +DATA 4 0x021B001C 0x15208030
  108 +DATA 4 0x021B001C 0x04008040
  109 +DATA 4 0x021B0020 0x00000800
  110 +DATA 4 0x021B0818 0x00000227
  111 +DATA 4 0x021B0004 0x0002552D
  112 +DATA 4 0x021B0404 0x00011006
  113 +DATA 4 0x021B001C 0x00000000
  114 +#endif
board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
Diff comments   View file @ 9fa8922
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/crm_regs.h>
  9 +#include <asm/arch/iomux.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +#include <asm/arch/mx6-pins.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/gpio.h>
  14 +#include <asm/mach-imx/iomux-v3.h>
  15 +#include <asm/mach-imx/boot_mode.h>
  16 +#include <asm/mach-imx/mxc_i2c.h>
  17 +#include <asm/io.h>
  18 +#include <common.h>
  19 +#include <fsl_esdhc.h>
  20 +#include <i2c.h>
  21 +#include <linux/sizes.h>
  22 +#include <linux/fb.h>
  23 +#include <miiphy.h>
  24 +#include <mmc.h>
  25 +#include <mxsfb.h>
  26 +#include <netdev.h>
  27 +#include <power/pmic.h>
  28 +#include <power/pfuze100_pmic.h>
  29 +#include "../common/pfuze.h"
  30 +#include <usb.h>
  31 +#include <usb/ehci-ci.h>
  32 +#if defined(CONFIG_MXC_EPDC)
  33 +#include <lcd.h>
  34 +#include <mxc_epdc_fb.h>
  35 +#endif
  36 +#include <asm/mach-imx/video.h>
  37 +
  38 +DECLARE_GLOBAL_DATA_PTR;
  39 +
  40 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43 +
  44 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  45 + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  46 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47 +
  48 +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
  49 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  50 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  51 +
  52 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  53 + PAD_CTL_SPEED_HIGH | \
  54 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  55 +
  56 +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  57 + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  58 +
  59 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  60 + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  61 +
  62 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  63 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  64 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  65 + PAD_CTL_ODE)
  66 +
  67 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  68 + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  69 +
  70 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  71 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  72 + PAD_CTL_SRE_FAST)
  73 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  74 +
  75 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  76 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  77 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  78 +
  79 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  80 + PAD_CTL_SPEED_MED | \
  81 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  82 +
  83 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  84 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  85 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  86 +
  87 +#define EPDC_PAD_CTRL 0x010b1
  88 +
  89 +#ifdef CONFIG_SYS_I2C
  90 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  91 +/* I2C1 for PMIC and EEPROM */
  92 +struct i2c_pads_info i2c_pad_info1 = {
  93 + .scl = {
  94 + /* conflict with usb_otg2_pwr */
  95 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  96 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  97 + .gp = IMX_GPIO_NR(1, 2),
  98 + },
  99 + .sda = {
  100 + /* conflict with usb_otg2_oc */
  101 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  102 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  103 + .gp = IMX_GPIO_NR(1, 3),
  104 + },
  105 +};
  106 +#endif
  107 +
  108 +int dram_init(void)
  109 +{
  110 + gd->ram_size = PHYS_SDRAM_SIZE;
  111 +
  112 + return 0;
  113 +}
  114 +
  115 +static iomux_v3_cfg_t const uart1_pads[] = {
  116 + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  117 + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  118 +};
  119 +
  120 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
  121 +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
  122 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128 + /*
  129 + * The following 4 pins conflicts with qspi and nand flash.
  130 + * You can comment out the following 4 pins and change
  131 + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4}
  132 + * to make emmc and qspi coexists.
  133 + */
  134 + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136 + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138 +
  139 + /* Default NO WP for emmc, since we use pull down */
  140 + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
  141 + /* RST_B */
  142 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  143 +};
  144 +#else
  145 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  146 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  148 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152 + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153 +
  154 + /* VSELECT */
  155 + MX6_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  156 + /* CD */
  157 + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  158 + /* RST_B */
  159 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  160 +};
  161 +#endif
  162 +
  163 +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK)
  164 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  165 + /* usdhc2_clk, nand_re_b, qspi1b_clk */
  166 + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167 + /* usdhc2_cmd, nand_we_b, qspi1b_cs0_b */
  168 + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  169 + /* usdhc2_data0, nand_data0, qspi1b_cs1_b */
  170 + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  171 + /* usdhc2_data1, nand_data1 */
  172 + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  173 + /* usdhc2_data2, nand_data2, qspi1b_dat0 */
  174 + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  175 + /* usdhc2_data3, nand_data3, qspi1b_dat1 */
  176 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  177 +
  178 + /*
  179 + * VSELECT
  180 + * Conflicts with WDOG1, so default disabled.
  181 + * MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  182 + */
  183 + /*
  184 + * CD
  185 + * Share with sdhc1
  186 + * MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  187 + */
  188 + /*
  189 + * RST_B
  190 + * Pin conflicts with NAND ALE, if want to test nand,
  191 + * Connect R169(B), disconnect R169(A).
  192 + */
  193 + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  194 +};
  195 +#endif
  196 +
  197 +#ifdef CONFIG_CMD_NAND
  198 +static iomux_v3_cfg_t const nand_pads[] = {
  199 + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  200 + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  201 + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  202 + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  203 + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  204 + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  205 + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  206 + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  207 + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  208 + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  209 + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  210 + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  211 + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  212 + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  213 + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  214 + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  215 + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  216 + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  217 + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  218 +};
  219 +
  220 +static void setup_gpmi_nand(void)
  221 +{
  222 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  223 +
  224 + /* config gpmi nand iomux */
  225 + SETUP_IOMUX_PADS(nand_pads);
  226 +
  227 + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  228 + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  229 +
  230 + /* enable apbh clock gating */
  231 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  232 +}
  233 +#endif
  234 +
  235 +#ifdef CONFIG_MXC_SPI
  236 +static iomux_v3_cfg_t const ecspi1_pads[] = {
  237 + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  238 + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  239 + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  240 +
  241 + /* CS Pin */
  242 + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
  243 +};
  244 +
  245 +static void setup_spinor(void)
  246 +{
  247 + SETUP_IOMUX_PADS(ecspi1_pads);
  248 + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs");
  249 + gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
  250 +}
  251 +
  252 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  253 +{
  254 + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1;
  255 +}
  256 +#endif
  257 +
  258 +#ifdef CONFIG_FEC_MXC
  259 +/*
  260 + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  261 + * be used for ENET1 or ENET2, cannot be used for both.
  262 + */
  263 +static iomux_v3_cfg_t const fec1_pads[] = {
  264 + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  265 + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  266 + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  267 + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  268 + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  269 + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  270 + /* Pin conflicts with LCD PWM1 */
  271 + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  272 + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  273 + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  274 + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  275 +};
  276 +
  277 +static iomux_v3_cfg_t const fec1_phy_rst[] = {
  278 + /*
  279 + * ALT5 mode is only valid when TAMPER pin is used for GPIO.
  280 + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
  281 + *
  282 + * ENET1_RST
  283 + */
  284 + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  285 +};
  286 +
  287 +static iomux_v3_cfg_t const fec2_pads[] = {
  288 + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  289 + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  290 +
  291 + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  292 + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  293 + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  294 + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  295 + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  296 + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  297 + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  298 +
  299 + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  300 + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  301 + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  302 + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  303 + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  304 + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  305 +
  306 + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  307 + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  308 +};
  309 +
  310 +static iomux_v3_cfg_t const fec2_phy_rst[] = {
  311 + /*
  312 + * ENET2_RST
  313 + *
  314 + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]
  315 + */
  316 + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  317 +};
  318 +
  319 +static void setup_iomux_fec(int fec_id)
  320 +{
  321 + if (fec_id == 0) {
  322 + SETUP_IOMUX_PADS(fec1_pads);
  323 + } else {
  324 + SETUP_IOMUX_PADS(fec2_pads);
  325 + }
  326 +}
  327 +#endif
  328 +
  329 +static void setup_iomux_uart(void)
  330 +{
  331 + SETUP_IOMUX_PADS(uart1_pads);
  332 +}
  333 +
  334 +#ifdef CONFIG_FSL_QSPI
  335 +
  336 +#ifndef CONFIG_DM_SPI
  337 +#define QSPI_PAD_CTRL1 \
  338 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
  339 + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
  340 +
  341 +static iomux_v3_cfg_t const quadspi_pads[] = {
  342 + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  343 + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  344 + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  345 + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  346 + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  347 + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  348 + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  349 +
  350 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK
  351 + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  352 + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  353 + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  354 + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  355 + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  356 + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  357 + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  358 +#endif
  359 +};
  360 +#endif
  361 +
  362 +int board_qspi_init(void)
  363 +{
  364 +#ifndef CONFIG_DM_SPI
  365 + /* Set the iomux */
  366 + SETUP_IOMUX_PADS(quadspi_pads);
  367 +#endif
  368 + /* Set the clock */
  369 + enable_qspi_clk(0);
  370 +
  371 + return 0;
  372 +}
  373 +#endif
  374 +
  375 +#ifdef CONFIG_FSL_ESDHC
  376 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  377 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
  378 + /* If want to use qspi, should change to 4 bit width */
  379 + {USDHC1_BASE_ADDR, 0, 8},
  380 +#else
  381 + {USDHC1_BASE_ADDR, 0, 4},
  382 +#endif
  383 +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK)
  384 + {USDHC2_BASE_ADDR, 0, 4},
  385 +#endif
  386 +};
  387 +
  388 +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
  389 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
  390 +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
  391 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  392 +
  393 +int board_mmc_get_env_dev(int devno)
  394 +{
  395 + if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
  396 + devno = 0;
  397 +
  398 + return devno;
  399 +}
  400 +
  401 +int mmc_map_to_kernel_blk(int devno)
  402 +{
  403 + if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
  404 + devno = 1;
  405 +
  406 + return devno;
  407 +}
  408 +
  409 +int board_mmc_getcd(struct mmc *mmc)
  410 +{
  411 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  412 + int ret = 0;
  413 +
  414 + switch (cfg->esdhc_base) {
  415 + case USDHC1_BASE_ADDR:
  416 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
  417 + ret = 1;
  418 +#else
  419 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  420 +#endif
  421 + break;
  422 +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK)
  423 + case USDHC2_BASE_ADDR:
  424 + ret = 1;
  425 + break;
  426 +#endif
  427 + }
  428 +
  429 + return ret;
  430 +}
  431 +
  432 +int board_mmc_init(bd_t *bis)
  433 +{
  434 + int i;
  435 +
  436 + /*
  437 + * According to the board_mmc_init() the following map is done:
  438 + * (U-boot device node) (Physical Port)
  439 + * mmc0 USDHC1
  440 + * mmc1 USDHC2
  441 + */
  442 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  443 + switch (i) {
  444 + case 0:
  445 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
  446 + SETUP_IOMUX_PADS(usdhc1_emmc_pads);
  447 +#else
  448 + SETUP_IOMUX_PADS(usdhc1_pads);
  449 + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
  450 + gpio_direction_input(USDHC1_CD_GPIO);
  451 +#endif
  452 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  453 + /* 3.3V */
  454 + gpio_request(USDHC1_VSELECT, "usdhc1 vsel");
  455 + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr");
  456 + gpio_direction_output(USDHC1_VSELECT, 0);
  457 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  458 + break;
  459 +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK)
  460 + case 1:
  461 + SETUP_IOMUX_PADS(usdhc2_pads);
  462 + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
  463 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  464 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  465 + break;
  466 +#endif
  467 + default:
  468 + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
  469 + return 0;
  470 + }
  471 +
  472 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  473 + printf("Warning: failed to initialize mmc dev %d\n", i);
  474 + }
  475 +
  476 + return 0;
  477 +}
  478 +#endif
  479 +
  480 +#ifdef CONFIG_VIDEO_MXS
  481 +static iomux_v3_cfg_t const lcd_pads[] = {
  482 + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  483 + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  484 + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  485 + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  486 + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  487 + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  488 + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  489 + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  490 + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  491 + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  492 + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  493 + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  494 + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  495 + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  496 + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  497 + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  498 + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  499 + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  500 + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  501 + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  502 + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  503 + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  504 + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  505 + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  506 + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  507 + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  508 + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  509 + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  510 + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  511 +
  512 + /*
  513 + * PWM1, pin conflicts with ENET1_RX_DATA0
  514 + * Use GPIO for Brightness adjustment, duty cycle = period.
  515 + */
  516 + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
  517 +};
  518 +
  519 +struct lcd_panel_info_t {
  520 + unsigned int lcdif_base_addr;
  521 + int depth;
  522 + void (*enable)(struct lcd_panel_info_t const *dev);
  523 + struct fb_videomode mode;
  524 +};
  525 +
  526 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  527 +{
  528 + enable_lcdif_clock(dev->bus, 1);
  529 +
  530 + SETUP_IOMUX_PADS(lcd_pads);
  531 +
  532 + /* Power up the LCD */
  533 + gpio_request(IMX_GPIO_NR(3, 4), "lcd power");
  534 + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  535 +
  536 + /* Set Brightness to high */
  537 + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */
  538 +}
  539 +
  540 +struct display_info_t const displays[] = {{
  541 + .bus = MX6ULL_LCDIF1_BASE_ADDR,
  542 + .addr = 0,
  543 + .pixfmt = 24,
  544 + .detect = NULL,
  545 + .enable = do_enable_parallel_lcd,
  546 + .mode = {
  547 + .name = "MCIMX28LCD",
  548 + .xres = 800,
  549 + .yres = 480,
  550 + .pixclock = 29850,
  551 + .left_margin = 89,
  552 + .right_margin = 164,
  553 + .upper_margin = 23,
  554 + .lower_margin = 10,
  555 + .hsync_len = 10,
  556 + .vsync_len = 10,
  557 + .sync = 0,
  558 + .vmode = FB_VMODE_NONINTERLACED
  559 +} } };
  560 +size_t display_count = ARRAY_SIZE(displays);
  561 +#endif
  562 +
  563 +#ifdef CONFIG_MXC_EPDC
  564 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  565 + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  566 + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  567 + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  568 + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  569 + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  570 + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  571 + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  572 + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  573 + MX6_PAD_LCD_CLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  574 + MX6_PAD_LCD_ENABLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  575 + MX6_PAD_LCD_HSYNC__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  576 + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  577 + MX6_PAD_LCD_DATA00__EPDC_SDDO00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  578 + MX6_PAD_LCD_DATA01__EPDC_SDDO01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  579 + MX6_PAD_LCD_DATA02__EPDC_SDDO02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  580 + MX6_PAD_LCD_DATA03__EPDC_SDDO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  581 + MX6_PAD_LCD_DATA04__EPDC_SDDO04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  582 + MX6_PAD_LCD_DATA05__EPDC_SDDO05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  583 + MX6_PAD_LCD_DATA06__EPDC_SDDO06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  584 + MX6_PAD_LCD_DATA07__EPDC_SDDO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  585 + MX6_PAD_LCD_DATA14__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  586 + MX6_PAD_LCD_DATA15__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  587 + MX6_PAD_LCD_DATA16__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  588 + MX6_PAD_LCD_DATA17__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  589 + MX6_PAD_LCD_RESET__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  590 +};
  591 +
  592 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  593 + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08,
  594 + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09,
  595 + MX6_PAD_ENET2_RX_EN__GPIO2_IO10,
  596 + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11,
  597 + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12,
  598 + MX6_PAD_ENET2_TX_EN__GPIO2_IO13,
  599 + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14,
  600 + MX6_PAD_ENET2_RX_ER__GPIO2_IO15,
  601 + MX6_PAD_LCD_CLK__GPIO3_IO00,
  602 + MX6_PAD_LCD_ENABLE__GPIO3_IO01,
  603 + MX6_PAD_LCD_HSYNC__GPIO3_IO02,
  604 + MX6_PAD_LCD_VSYNC__GPIO3_IO03,
  605 + MX6_PAD_LCD_DATA00__GPIO3_IO05,
  606 + MX6_PAD_LCD_DATA01__GPIO3_IO06,
  607 + MX6_PAD_LCD_DATA02__GPIO3_IO07,
  608 + MX6_PAD_LCD_DATA03__GPIO3_IO08,
  609 + MX6_PAD_LCD_DATA04__GPIO3_IO09,
  610 + MX6_PAD_LCD_DATA05__GPIO3_IO10,
  611 + MX6_PAD_LCD_DATA06__GPIO3_IO11,
  612 + MX6_PAD_LCD_DATA07__GPIO3_IO12,
  613 + MX6_PAD_LCD_DATA14__GPIO3_IO19,
  614 + MX6_PAD_LCD_DATA15__GPIO3_IO20,
  615 + MX6_PAD_LCD_DATA16__GPIO3_IO21,
  616 + MX6_PAD_LCD_DATA17__GPIO3_IO22,
  617 + MX6_PAD_LCD_RESET__GPIO3_IO04,
  618 +};
  619 +
  620 +vidinfo_t panel_info = {
  621 + .vl_refresh = 85,
  622 + .vl_col = 1024,
  623 + .vl_row = 758,
  624 + .vl_pixclock = 40000000,
  625 + .vl_left_margin = 12,
  626 + .vl_right_margin = 76,
  627 + .vl_upper_margin = 4,
  628 + .vl_lower_margin = 5,
  629 + .vl_hsync = 12,
  630 + .vl_vsync = 2,
  631 + .vl_sync = 0,
  632 + .vl_mode = 0,
  633 + .vl_flag = 0,
  634 + .vl_bpix = 3,
  635 + .cmap = 0,
  636 +};
  637 +
  638 +struct epdc_timing_params panel_timings = {
  639 + .vscan_holdoff = 4,
  640 + .sdoed_width = 10,
  641 + .sdoed_delay = 20,
  642 + .sdoez_width = 10,
  643 + .sdoez_delay = 20,
  644 + .gdclk_hp_offs = 524,
  645 + .gdsp_offs = 327,
  646 + .gdoe_offs = 0,
  647 + .gdclk_offs = 19,
  648 + .num_ce = 1,
  649 +};
  650 +
  651 +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
  652 + IOMUX_PADS(PAD_LCD_DATA11__GPIO3_IO16 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  653 + IOMUX_PADS(PAD_LCD_DATA19__GPIO3_IO24 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  654 + IOMUX_PADS(PAD_LCD_DATA09__GPIO3_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  655 + IOMUX_PADS(PAD_LCD_DATA12__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
  656 +};
  657 +
  658 +static void setup_epdc_power(void)
  659 +{
  660 + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
  661 +
  662 + /* Setup epdc voltage */
  663 +
  664 + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
  665 + gpio_request(IMX_GPIO_NR(3, 16), "EPDC_PWRSTAT");
  666 + gpio_direction_input(IMX_GPIO_NR(3, 16));
  667 +
  668 + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */
  669 + /* Set as output */
  670 + gpio_request(IMX_GPIO_NR(3, 24), "EPDC_VCOM0");
  671 + gpio_direction_output(IMX_GPIO_NR(3, 24), 1);
  672 +
  673 + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
  674 + /* Set as output */
  675 + gpio_request(IMX_GPIO_NR(3, 14), "EPDC_PWRWAKEUP");
  676 + gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
  677 +
  678 + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
  679 + /* Set as output */
  680 + gpio_request(IMX_GPIO_NR(3, 17), "EPDC_PWRCTRL0");
  681 + gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
  682 +}
  683 +
  684 +static void epdc_enable_pins(void)
  685 +{
  686 + /* epdc iomux settings */
  687 + SETUP_IOMUX_PADS(epdc_enable_pads);
  688 +}
  689 +
  690 +static void epdc_disable_pins(void)
  691 +{
  692 + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
  693 + SETUP_IOMUX_PADS(epdc_disable_pads);
  694 +}
  695 +
  696 +static void setup_epdc(void)
  697 +{
  698 + /* Set pixel clock rates for EPDC in clock.c */
  699 +
  700 + panel_info.epdc_data.wv_modes.mode_init = 0;
  701 + panel_info.epdc_data.wv_modes.mode_du = 1;
  702 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  703 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  704 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  705 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  706 +
  707 + panel_info.epdc_data.epdc_timings = panel_timings;
  708 +
  709 + setup_epdc_power();
  710 +}
  711 +
  712 +void epdc_power_on(void)
  713 +{
  714 + unsigned int reg;
  715 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR;
  716 +
  717 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  718 + gpio_set_value(IMX_GPIO_NR(3, 17), 1);
  719 + udelay(1000);
  720 +
  721 + /* Enable epdc signal pin */
  722 + epdc_enable_pins();
  723 +
  724 + /* Set PMIC Wakeup to high - enable Display power */
  725 + gpio_set_value(IMX_GPIO_NR(3, 14), 1);
  726 +
  727 + /* Wait for PWRGOOD == 1 */
  728 + while (1) {
  729 + reg = readl(&gpio_regs->gpio_psr);
  730 + if (!(reg & (1 << 16)))
  731 + break;
  732 +
  733 + udelay(100);
  734 + }
  735 +
  736 + /* Enable VCOM */
  737 + gpio_set_value(IMX_GPIO_NR(3, 24), 1);
  738 +
  739 + udelay(500);
  740 +}
  741 +
  742 +void epdc_power_off(void)
  743 +{
  744 + /* Set PMIC Wakeup to low - disable Display power */
  745 + gpio_set_value(IMX_GPIO_NR(3, 14), 0);
  746 +
  747 + /* Disable VCOM */
  748 + gpio_set_value(IMX_GPIO_NR(3, 24), 0);
  749 +
  750 + epdc_disable_pins();
  751 +
  752 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  753 + gpio_set_value(IMX_GPIO_NR(3, 17), 0);
  754 +}
  755 +#endif
  756 +
  757 +#ifdef CONFIG_FEC_MXC
  758 +int board_eth_init(bd_t *bis)
  759 +{
  760 + int ret;
  761 +
  762 + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  763 +
  764 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  765 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  766 + if (ret)
  767 + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
  768 +
  769 + return 0;
  770 +}
  771 +
  772 +static int setup_fec(int fec_id)
  773 +{
  774 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  775 + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  776 + int ret;
  777 +
  778 + if (0 == fec_id) {
  779 + if (check_module_fused(MX6_MODULE_ENET1))
  780 + return -1;
  781 + /*
  782 + * Use 50M anatop loopback REF_CLK1 for ENET1,
  783 + * clear gpr1[13], set gpr1[17]
  784 + */
  785 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  786 + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  787 + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  788 + if (ret)
  789 + return ret;
  790 +
  791 + SETUP_IOMUX_PADS(fec1_phy_rst);
  792 + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
  793 + gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
  794 + udelay(50);
  795 + gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
  796 +
  797 + } else {
  798 + if (check_module_fused(MX6_MODULE_ENET2))
  799 + return -1;
  800 +
  801 + /* clk from phy, set gpr1[14], clear gpr1[18]*/
  802 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  803 + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
  804 +
  805 + SETUP_IOMUX_PADS(fec2_phy_rst);
  806 + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
  807 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  808 + udelay(50);
  809 + gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  810 + }
  811 +
  812 + enable_enet_clk(1);
  813 +
  814 + return 0;
  815 +}
  816 +
  817 +int board_phy_config(struct phy_device *phydev)
  818 +{
  819 + if (CONFIG_FEC_ENET_DEV == 0) {
  820 + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
  821 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  822 + } else if (CONFIG_FEC_ENET_DEV == 1) {
  823 + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
  824 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
  825 + }
  826 +
  827 + if (phydev->drv->config)
  828 + phydev->drv->config(phydev);
  829 +
  830 + return 0;
  831 +}
  832 +#endif
  833 +
  834 +#ifdef CONFIG_POWER
  835 +#define I2C_PMIC 0
  836 +static struct pmic *pfuze;
  837 +int power_init_board(void)
  838 +{
  839 + int ret;
  840 + u32 rev_id, value;
  841 +
  842 + ret = power_pfuze100_init(I2C_PMIC);
  843 + if (ret)
  844 + return ret;
  845 +
  846 + pfuze = pmic_get("PFUZE100");
  847 + if (!pfuze)
  848 + return -ENODEV;
  849 +
  850 + ret = pmic_probe(pfuze);
  851 + if (ret)
  852 + return ret;
  853 +
  854 + ret = pfuze_mode_init(pfuze, APS_PFM);
  855 + if (ret < 0)
  856 + return ret;
  857 +
  858 + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
  859 + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
  860 + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
  861 +
  862 + /*
  863 + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
  864 + * Configuration is F0.
  865 + * Default VOLT:
  866 + * VSNVS_VOLT | 3.0V
  867 + * SW1AB | 1.375V
  868 + * SW2 | 3.3V
  869 + * SW3A | 1.5V
  870 + * SW3B | 1.5V
  871 + * VGEN1 | 1.5V
  872 + * VGEN2 | 1.5V
  873 + * VGEN3 | 2.5V
  874 + * VGEN4 | 1.8V
  875 + * VGEN5 | 2.8V
  876 + * VGEN6 | 3.3V
  877 + *
  878 + * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
  879 + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
  880 + * VGEN5 3.3V, VGEN6 3.0V.
  881 + *
  882 + * Here we just use the default VOLT, but not configure
  883 + * them, when needed, configure them to our requested voltage.
  884 + */
  885 +
  886 + /* set SW1AB standby volatage 0.975V */
  887 + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
  888 + value &= ~0x3f;
  889 + value |= PFUZE100_SW1ABC_SETP(9750);
  890 + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
  891 +
  892 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  893 + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
  894 + value &= ~0xc0;
  895 + value |= 0x40;
  896 + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
  897 +
  898 + /* Enable power of VGEN5 3V3 */
  899 + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
  900 + value &= ~0x1F;
  901 + value |= 0x1F;
  902 + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
  903 +
  904 + return 0;
  905 +}
  906 +
  907 +#ifdef CONFIG_LDO_BYPASS_CHECK
  908 +void ldo_mode_set(int ldo_bypass)
  909 +{
  910 + unsigned int value;
  911 + int is_400M;
  912 + u32 vddarm;
  913 +
  914 + struct pmic *p = pfuze;
  915 +
  916 + if (!p) {
  917 + printf("No PMIC found!\n");
  918 + return;
  919 + }
  920 +
  921 + /* switch to ldo_bypass mode */
  922 + if (ldo_bypass) {
  923 + prep_anatop_bypass();
  924 + /* decrease VDDARM to 1.275V */
  925 + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
  926 + value &= ~0x3f;
  927 + value |= PFUZE100_SW1ABC_SETP(12750);
  928 + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
  929 +
  930 + is_400M = set_anatop_bypass(1);
  931 + if (is_400M)
  932 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  933 + else
  934 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  935 +
  936 + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
  937 + value &= ~0x3f;
  938 + value |= vddarm;
  939 + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
  940 +
  941 + finish_anatop_bypass();
  942 +
  943 + printf("switch to ldo_bypass mode!\n");
  944 + }
  945 +}
  946 +#endif
  947 +
  948 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  949 +int power_init_board(void)
  950 +{
  951 + struct udevice *dev;
  952 + int ret;
  953 + unsigned int reg, dev_id, rev_id;
  954 +
  955 + ret = pmic_get("pfuze100", &dev);
  956 + if (ret == -ENODEV)
  957 + return ret;
  958 +
  959 + ret = pfuze_mode_init(dev, APS_PFM);
  960 + if (ret < 0)
  961 + return ret;
  962 +
  963 + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  964 + rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  965 + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  966 +
  967 + /*
  968 + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
  969 + * Configuration is F0.
  970 + * Default VOLT:
  971 + * VSNVS_VOLT | 3.0V
  972 + * SW1AB | 1.375V
  973 + * SW2 | 3.3V
  974 + * SW3A | 1.5V
  975 + * SW3B | 1.5V
  976 + * VGEN1 | 1.5V
  977 + * VGEN2 | 1.5V
  978 + * VGEN3 | 2.5V
  979 + * VGEN4 | 1.8V
  980 + * VGEN5 | 2.8V
  981 + * VGEN6 | 3.3V
  982 + *
  983 + * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
  984 + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
  985 + * VGEN5 3.3V, VGEN6 3.0V.
  986 + *
  987 + * Here we just use the default VOLT, but not configure
  988 + * them, when needed, configure them to our requested voltage.
  989 + */
  990 +
  991 + /* Set SW1AB stanby volage to 0.975V */
  992 + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  993 + reg &= ~SW1x_STBY_MASK;
  994 + reg |= SW1x_0_975V;
  995 + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  996 +
  997 + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  998 + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  999 + reg &= ~SW1xCONF_DVSSPEED_MASK;
  1000 + reg |= SW1xCONF_DVSSPEED_4US;
  1001 + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  1002 +
  1003 + /* Enable power of VGEN5 3V3 */
  1004 + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
  1005 + reg &= ~0x1F;
  1006 + reg |= 0x1F;
  1007 + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  1008 +
  1009 + return 0;
  1010 +}
  1011 +
  1012 +#ifdef CONFIG_LDO_BYPASS_CHECK
  1013 +void ldo_mode_set(int ldo_bypass)
  1014 +{
  1015 + struct udevice *dev;
  1016 + int ret;
  1017 + int is_400M;
  1018 + u32 vddarm;
  1019 +
  1020 + ret = pmic_get("pfuze100", &dev);
  1021 + if (ret == -ENODEV) {
  1022 + printf("No PMIC found!\n");
  1023 + return;
  1024 + }
  1025 +
  1026 + /* switch to ldo_bypass mode */
  1027 + if (ldo_bypass) {
  1028 + /* decrease VDDARM to 1.275V */
  1029 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
  1030 +
  1031 + is_400M = set_anatop_bypass(1);
  1032 + if (is_400M)
  1033 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  1034 + else
  1035 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  1036 +
  1037 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
  1038 +
  1039 + set_anatop_bypass(1);
  1040 +
  1041 + printf("switch to ldo_bypass mode!\n");
  1042 + }
  1043 +}
  1044 +#endif
  1045 +
  1046 +#endif
  1047 +
  1048 +int board_early_init_f(void)
  1049 +{
  1050 + setup_iomux_uart();
  1051 +
  1052 + return 0;
  1053 +}
  1054 +
  1055 +int board_init(void)
  1056 +{
  1057 + /* Address of boot parameters */
  1058 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  1059 +
  1060 +#ifdef CONFIG_SYS_I2C
  1061 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  1062 +#endif
  1063 +
  1064 +#ifdef CONFIG_FEC_MXC
  1065 + setup_fec(CONFIG_FEC_ENET_DEV);
  1066 +#endif
  1067 +
  1068 +#ifdef CONFIG_MXC_SPI
  1069 + setup_spinor();
  1070 +#endif
  1071 +
  1072 +#ifdef CONFIG_CMD_NAND
  1073 + setup_gpmi_nand();
  1074 +#endif
  1075 +
  1076 +#ifdef CONFIG_FSL_QSPI
  1077 + board_qspi_init();
  1078 +#endif
  1079 +
  1080 +#ifdef CONFIG_MXC_EPDC
  1081 + enable_epdc_clock();
  1082 + setup_epdc();
  1083 +#endif
  1084 +
  1085 + return 0;
  1086 +}
  1087 +
  1088 +#ifdef CONFIG_CMD_BMODE
  1089 +static const struct boot_mode board_boot_modes[] = {
  1090 + /* 4 bit bus width */
  1091 + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  1092 + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  1093 + {NULL, 0},
  1094 +};
  1095 +#endif
  1096 +
  1097 +int board_late_init(void)
  1098 +{
  1099 +#ifdef CONFIG_CMD_BMODE
  1100 + add_board_boot_modes(board_boot_modes);
  1101 +#endif
  1102 +
  1103 +#ifdef CONFIG_ENV_IS_IN_MMC
  1104 + board_late_mmc_env_init();
  1105 +#endif
  1106 +
  1107 + return 0;
  1108 +}
  1109 +
  1110 +u32 get_board_rev(void)
  1111 +{
  1112 + return get_cpu_rev();
  1113 +}
  1114 +
  1115 +int checkboard(void)
  1116 +{
  1117 + puts("Board: MX6ULL 14X14 DDR3 ARM2\n");
  1118 +
  1119 + return 0;
  1120 +}
  1121 +
  1122 +#ifdef CONFIG_USB_EHCI_MX6
  1123 +#ifndef CONFIG_DM_USB
  1124 +
  1125 +#define USB_OTHERREGS_OFFSET 0x800
  1126 +#define UCTRL_PWR_POL (1 << 9)
  1127 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  1128 + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  1129 + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  1130 +};
  1131 +
  1132 +/*
  1133 + * Leave it here, but default configuration only supports 1 port now,
  1134 + * because we need sd1 and i2c1
  1135 + */
  1136 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  1137 + /* conflict with i2c1_scl */
  1138 + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  1139 + /* conflict with sd1_vselect */
  1140 + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  1141 +};
  1142 +
  1143 +int board_usb_phy_mode(int port)
  1144 +{
  1145 + return usb_phy_mode(port);
  1146 +}
  1147 +
  1148 +int board_ehci_hcd_init(int port)
  1149 +{
  1150 + u32 *usbnc_usb_ctrl;
  1151 +
  1152 + if (port > 1)
  1153 + return -EINVAL;
  1154 +
  1155 + switch (port) {
  1156 + case 0:
  1157 + SETUP_IOMUX_PADS(usb_otg1_pads);
  1158 + break;
  1159 + case 1:
  1160 + SETUP_IOMUX_PADS(usb_otg2_pads);
  1161 + break;
  1162 + default:
  1163 + printf("MXC USB port %d not yet supported\n", port);
  1164 + return 1;
  1165 + }
  1166 +
  1167 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  1168 + port * 4);
  1169 +
  1170 + /* Set Power polarity */
  1171 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  1172 +
  1173 + return 0;
  1174 +}
  1175 +#endif
  1176 +#endif
board/freescale/mx6ull_ddr3_arm2/plugin.S
Diff comments   View file @ 9fa8922
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6ull_ddr3_arm2_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000C0000
  13 + str r1, [r0, #0x4B4]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x4AC]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x27C]
  18 + str r1, [r0, #0x250]
  19 + str r1, [r0, #0x24C]
  20 + str r1, [r0, #0x490]
  21 + ldr r1, =0x000C0030
  22 + str r1, [r0, #0x288]
  23 +
  24 + ldr r1, =0x00000000
  25 + str r1, [r0, #0x270]
  26 +
  27 + ldr r1, =0x00000030
  28 + str r1, [r0, #0x260]
  29 + str r1, [r0, #0x264]
  30 + str r1, [r0, #0x4A0]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x494]
  34 +
  35 + ldr r1, =0x00000030
  36 + str r1, [r0, #0x280]
  37 + str r1, [r0, #0x284]
  38 +
  39 + ldr r1, =0x00020000
  40 + str r1, [r0, #0x4B0]
  41 +
  42 + ldr r1, =0x00000030
  43 + str r1, [r0, #0x498]
  44 + str r1, [r0, #0x4A4]
  45 + str r1, [r0, #0x244]
  46 + str r1, [r0, #0x248]
  47 +
  48 + ldr r0, =MMDC_P0_BASE_ADDR
  49 + ldr r1, =0x00008000
  50 + str r1, [r0, #0x1C]
  51 + ldr r1, =0xA1390003
  52 + str r1, [r0, #0x800]
  53 + ldr r1, =0x00150019
  54 + str r1, [r0, #0x80C]
  55 + ldr r1, =0x41550153
  56 + str r1, [r0, #0x83C]
  57 + ldr r1, =0x40403A3E
  58 + str r1, [r0, #0x848]
  59 + ldr r1, =0x40402F2A
  60 + str r1, [r0, #0x850]
  61 + ldr r1, =0x33333333
  62 + str r1, [r0, #0x81C]
  63 + str r1, [r0, #0x820]
  64 + ldr r1, =0xF3333333
  65 + str r1, [r0, #0x82C]
  66 + str r1, [r0, #0x830]
  67 + ldr r1, =0x00944009
  68 + str r1, [r0, #0x8C0]
  69 + ldr r1, =0x00000800
  70 + str r1, [r0, #0x8B8]
  71 + ldr r1, =0x0002002D
  72 + str r1, [r0, #0x004]
  73 + ldr r1, =0x1B333030
  74 + str r1, [r0, #0x008]
  75 + ldr r1, =0x676B52F3
  76 + str r1, [r0, #0x00C]
  77 + ldr r1, =0xB66D0B63
  78 + str r1, [r0, #0x010]
  79 + ldr r1, =0x01FF00DB
  80 + str r1, [r0, #0x014]
  81 + ldr r1, =0x00211740
  82 + str r1, [r0, #0x018]
  83 + ldr r1, =0x00008000
  84 + str r1, [r0, #0x01C]
  85 + ldr r1, =0x000026D2
  86 + str r1, [r0, #0x02C]
  87 + ldr r1, =0x006B1023
  88 + str r1, [r0, #0x030]
  89 + ldr r1, =0x0000005F
  90 + str r1, [r0, #0x040]
  91 + ldr r1, =0x85180000
  92 + str r1, [r0, #0x000]
  93 + ldr r1, =0x00400000
  94 + str r1, [r0, #0x890]
  95 + ldr r1, =0x02008032
  96 + str r1, [r0, #0x01C]
  97 + ldr r1, =0x00008033
  98 + str r1, [r0, #0x01C]
  99 + ldr r1, =0x00048031
  100 + str r1, [r0, #0x01C]
  101 + ldr r1, =0x15208030
  102 + str r1, [r0, #0x01C]
  103 + ldr r1, =0x04008040
  104 + str r1, [r0, #0x01C]
  105 + ldr r1, =0x00000800
  106 + str r1, [r0, #0x020]
  107 + ldr r1, =0x00000227
  108 + str r1, [r0, #0x818]
  109 + ldr r1, =0x0002552D
  110 + str r1, [r0, #0x004]
  111 + ldr r1, =0x00011006
  112 + str r1, [r0, #0x404]
  113 + ldr r1, =0x00000000
  114 + str r1, [r0, #0x01C]
  115 +.endm
  116 +
  117 +.macro imx6_clock_gating
  118 + ldr r0, =CCM_BASE_ADDR
  119 + ldr r1, =0xFFFFFFFF
  120 + str r1, [r0, #0x68]
  121 + str r1, [r0, #0x6C]
  122 + str r1, [r0, #0x70]
  123 + str r1, [r0, #0x74]
  124 + str r1, [r0, #0x78]
  125 + str r1, [r0, #0x7C]
  126 + str r1, [r0, #0x80]
  127 +.endm
  128 +
  129 +.macro imx6_qos_setting
  130 +.endm
  131 +
  132 +.macro imx6_ddr_setting
  133 + imx6ull_ddr3_arm2_setting
  134 +.endm
  135 +
  136 +/* include the common plugin code here */
  137 +#include <asm/arch/mx6_plugin.S>
include/configs/mx6ull_ddr3_arm2.h
Diff comments   View file @ 9fa8922
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H
  9 +#define __MX6ULL_DDR3_ARM2_CONFIG_H
  10 +
  11 +#ifdef CONFIG_SPI_BOOT
  12 +
  13 +#define CONFIG_MXC_SPI
  14 +#elif defined CONFIG_NAND_BOOT
  15 +#define CONFIG_CMD_NAND
  16 +#endif
  17 +
  18 +#define BOOTARGS_CMA_SIZE ""
  19 +
  20 +#include "mx6ul_arm2.h"
  21 +
  22 +#define CONFIG_IOMUX_LPSR
  23 +
  24 +#define PHYS_SDRAM_SIZE SZ_1G
  25 +
  26 +/*
  27 + * TSC pins conflict with I2C1 bus, so after TSC
  28 + * hardware rework, need to disable i2c1 bus, also
  29 + * need to disable PMIC and ldo bypass check.
  30 + */
  31 +#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK
  32 +#undef CONFIG_LDO_BYPASS_CHECK
  33 +#undef CONFIG_SYS_I2C_MXC
  34 +#undef CONFIG_SYS_I2C
  35 +#undef CONFIG_CMD_I2C
  36 +#undef CONFIG_POWER_PFUZE100_I2C_ADDR
  37 +#undef CONFIG_POWER_PFUZE100
  38 +#undef CONFIG_POWER_I2C
  39 +#undef CONFIG_POWER
  40 +#endif
  41 +
  42 +#ifdef CONFIG_MXC_SPI
  43 +#define CONFIG_SF_DEFAULT_BUS 0
  44 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  45 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  46 +#define CONFIG_SF_DEFAULT_CS 0
  47 +#endif
  48 +
  49 +#ifdef CONFIG_DM_ETH
  50 +#define CONFIG_CMD_MII
  51 +#define CONFIG_FEC_MXC
  52 +#define CONFIG_MII
  53 +#define CONFIG_FEC_ENET_DEV 1
  54 +
  55 +#if (CONFIG_FEC_ENET_DEV == 0)
  56 +#define IMX_FEC_BASE ENET_BASE_ADDR
  57 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  58 +#define CONFIG_FEC_XCV_TYPE RMII
  59 +#ifdef CONFIG_DM_ETH
  60 +#define CONFIG_ETHPRIME "eth0"
  61 +#else
  62 +#define CONFIG_ETHPRIME "FEC0"
  63 +#endif
  64 +#elif (CONFIG_FEC_ENET_DEV == 1)
  65 +#define IMX_FEC_BASE ENET2_BASE_ADDR
  66 +#define CONFIG_FEC_MXC_PHYADDR 0x2
  67 +#define CONFIG_FEC_XCV_TYPE MII100
  68 +#ifdef CONFIG_DM_ETH
  69 +#define CONFIG_ETHPRIME "eth1"
  70 +#else
  71 +#define CONFIG_ETHPRIME "FEC1"
  72 +#endif
  73 +#endif
  74 +
  75 +#define CONFIG_PHYLIB
  76 +#define CONFIG_PHY_MICREL
  77 +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
  78 +#endif
  79 +
  80 +
  81 +/* #define CONFIG_SPLASH_SCREEN*/
  82 +/* #define CONFIG_MXC_EPDC*/
  83 +
  84 +/*
  85 + * SPLASH SCREEN Configs
  86 + */
  87 +#if defined(CONFIG_MXC_EPDC)
  88 +/*
  89 + * Framebuffer and LCD
  90 + */
  91 +#define CONFIG_SPLASH_SCREEN
  92 +
  93 +#undef LCD_TEST_PATTERN
  94 +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  95 +#define LCD_BPP LCD_MONOCHROME
  96 +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  97 +
  98 +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
  99 +#endif
  100 +
  101 +#define CONFIG_MODULE_FUSE
  102 +#define CONFIG_OF_SYSTEM_SETUP
  103 +
  104 +#endif