dm: implement a DMA uclass

Implement a DMA uclass so that the devices like ethernet, spi, mmc etc can offload the data transfers from/to the device and memory. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>

dm: implement a DMA uclass
Implement a DMA uclass so that the devices like ethernet, spi, mmc etc can offload the data transfers from/to the device and memory. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N · Jagan Teki
1 parent 18c61e9571
Showing 5 changed files with 176 additions and 0 deletions Side-by-side Diff
drivers/dma/Kconfig
drivers/dma/Makefile
drivers/dma/dma-uclass.c
include/dm/uclass-id.h
include/dma.h
+menu "DMA Support"
+
+config DMA
+	bool "Enable Driver Model for DMA drivers"
+	depends on DM
+	help
+	  Enable driver model for DMA. DMA engines can do
+	  asynchronous data transfers without involving the host
+	  CPU. Currently, this framework can be used to offload
+	  memory copies to and from devices like qspi, ethernet
+	  etc Drivers provide methods to access the DMA devices
+	  buses that is used to transfer data to and from memory.
+	  The uclass interface is defined in include/dma.h.
+
+endmenu # menu "DMA Support"
@@ -5,6 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
+obj-$(CONFIG_DMA) += dma-uclass.o
+
 obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 obj-$(CONFIG_APBH_DMA) += apbh_dma.o
 obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+/*
+ * Direct Memory Access U-Class driver
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Author: Mugunthan V N <mugunthanvnm@ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dma.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dma_get_device(u32 transfer_type, struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	for (ret = uclass_first_device(UCLASS_DMA, &dev); dev && !ret;
+	     ret = uclass_next_device(&dev)) {
+		struct dma_dev_priv *uc_priv;
+
+		uc_priv = dev_get_uclass_priv(dev);
+		if (uc_priv->supported & transfer_type)
+			break;
+	}
+
+	if (!dev) {
+		error("No DMA device found that supports %x type\n",
+		      transfer_type);
+		return -EPROTONOSUPPORT;
+	}
+
+	*devp = dev;
+
+	return ret;
+}
+
+int dma_memcpy(void *dst, void *src, size_t len)
+{
+	struct udevice *dev;
+	const struct dma_ops *ops;
+	int ret;
+
+	ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev);
+	if (ret < 0)
+		return ret;
+
+	ops = device_get_ops(dev);
+	if (!ops->transfer)
+		return -ENOSYS;
+
+	/* Invalidate the area, so no writeback into the RAM races with DMA */
+	invalidate_dcache_range((unsigned long)dst, (unsigned long)dst +
+				roundup(len, ARCH_DMA_MINALIGN));
+
+	return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len);
+}
+
+UCLASS_DRIVER(dma) = {
+	.id		= UCLASS_DMA,
+	.name		= "dma",
+	.flags		= DM_UC_FLAG_SEQ_ALIAS,
+	.per_device_auto_alloc_size = sizeof(struct dma_dev_priv),
+};
@@ -31,6 +31,7 @@
 	UCLASS_CROS_EC,		/* Chrome OS EC */
 	UCLASS_DISK,		/* Disk controller, e.g. SATA */
 	UCLASS_DISPLAY,		/* Display (e.g. DisplayPort, HDMI) */
+	UCLASS_DMA,		/* Direct Memory Access */
 	UCLASS_RAM,		/* RAM controller */
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
+/*
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+/*
+ * enum dma_direction - dma transfer direction indicator
+ * @DMA_MEM_TO_MEM: Memcpy mode
+ * @DMA_MEM_TO_DEV: From Memory to Device
+ * @DMA_DEV_TO_MEM: From Device to Memory
+ * @DMA_DEV_TO_DEV: From Device to Device
+ */
+enum dma_direction {
+	DMA_MEM_TO_MEM,
+	DMA_MEM_TO_DEV,
+	DMA_DEV_TO_MEM,
+	DMA_DEV_TO_DEV,
+};
+
+#define DMA_SUPPORTS_MEM_TO_MEM	BIT(0)
+#define DMA_SUPPORTS_MEM_TO_DEV	BIT(1)
+#define DMA_SUPPORTS_DEV_TO_MEM	BIT(2)
+#define DMA_SUPPORTS_DEV_TO_DEV	BIT(3)
+
+/*
+ * struct dma_ops - Driver model DMA operations
+ *
+ * The uclass interface is implemented by all DMA devices which use
+ * driver model.
+ */
+struct dma_ops {
+	/*
+	 * Get the current timer count
+	 *
+	 * @dev: The DMA device
+	 * @direction: direction of data transfer should be one from
+		       enum dma_direction
+	 * @dst: Destination pointer
+	 * @src: Source pointer
+	 * @len: Length of the data to be copied.
+	 * @return: 0 if OK, -ve on error
+	 */
+	int (*transfer)(struct udevice *dev, int direction, void *dst,
+			void *src, size_t len);
+};
+
+/*
+ * struct dma_dev_priv - information about a device used by the uclass
+ *
+ * @supported: mode of transfers that DMA can support, should be
+ *	       one/multiple of DMA_SUPPORTS_*
+ */
+struct dma_dev_priv {
+	u32 supported;
+};
+
+/*
+ * dma_get_device - get a DMA device which supports transfer
+ * type of transfer_type
+ *
+ * @transfer_type - transfer type should be one/multiple of
+ *		    DMA_SUPPORTS_*
+ * @devp - udevice pointer to return the found device
+ * @return - will return on success and devp will hold the
+ *	     pointer to the device
+ */
+int dma_get_device(u32 transfer_type, struct udevice **devp);
+
+/*
+ * dma_memcpy - try to use DMA to do a mem copy which will be
+ *		much faster than CPU mem copy
+ *
+ * @dst - destination pointer
+ * @src - souce pointer
+ * @len - data length to be copied
+ * @return - on successful transfer returns no of bytes
+	     transferred and on failure return error code.
+ */
+int dma_memcpy(void *dst, void *src, size_t len);
+
+#endif	/* _DMA_H_ */
	1	+menu "DMA Support"
	2	+
	3	+config DMA
	4	+ bool "Enable Driver Model for DMA drivers"
	5	+ depends on DM
	6	+ help
	7	+ Enable driver model for DMA. DMA engines can do
	8	+ asynchronous data transfers without involving the host
	9	+ CPU. Currently, this framework can be used to offload
	10	+ memory copies to and from devices like qspi, ethernet
	11	+ etc Drivers provide methods to access the DMA devices
	12	+ buses that is used to transfer data to and from memory.
	13	+ The uclass interface is defined in include/dma.h.
	14	+
	15	+endmenu # menu "DMA Support"
...	...	@@ -5,6 +5,8 @@
5	5	# SPDX-License-Identifier: GPL-2.0+
6	6	#
7	7
	8	+obj-$(CONFIG_DMA) += dma-uclass.o
	9	+
8	10	obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
9	11	obj-$(CONFIG_APBH_DMA) += apbh_dma.o
10	12	obj-$(CONFIG_FSL_DMA) += fsl_dma.o
	1	+/*
	2	+ * Direct Memory Access U-Class driver
	3	+ *
	4	+ * (C) Copyright 2015
	5	+ * Texas Instruments Incorporated, <www.ti.com>
	6	+ *
	7	+ * Author: Mugunthan V N <mugunthanvnm@ti.com>
	8	+ *
	9	+ * SPDX-License-Identifier: GPL-2.0+
	10	+ */
	11	+
	12	+#include <common.h>
	13	+#include <dma.h>
	14	+#include <dm.h>
	15	+#include <dm/uclass-internal.h>
	16	+#include <dm/device-internal.h>
	17	+#include <errno.h>
	18	+
	19	+DECLARE_GLOBAL_DATA_PTR;
	20	+
	21	+int dma_get_device(u32 transfer_type, struct udevice **devp)
	22	+{
	23	+ struct udevice *dev;
	24	+ int ret;
	25	+
	26	+ for (ret = uclass_first_device(UCLASS_DMA, &dev); dev && !ret;
	27	+ ret = uclass_next_device(&dev)) {
	28	+ struct dma_dev_priv *uc_priv;
	29	+
	30	+ uc_priv = dev_get_uclass_priv(dev);
	31	+ if (uc_priv->supported & transfer_type)
	32	+ break;
	33	+ }
	34	+
	35	+ if (!dev) {
	36	+ error("No DMA device found that supports %x type\n",
	37	+ transfer_type);
	38	+ return -EPROTONOSUPPORT;
	39	+ }
	40	+
	41	+ *devp = dev;
	42	+
	43	+ return ret;
	44	+}
	45	+
	46	+int dma_memcpy(void dst, void src, size_t len)
	47	+{
	48	+ struct udevice *dev;
	49	+ const struct dma_ops *ops;
	50	+ int ret;
	51	+
	52	+ ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev);
	53	+ if (ret < 0)
	54	+ return ret;
	55	+
	56	+ ops = device_get_ops(dev);
	57	+ if (!ops->transfer)
	58	+ return -ENOSYS;
	59	+
	60	+ /* Invalidate the area, so no writeback into the RAM races with DMA */
	61	+ invalidate_dcache_range((unsigned long)dst, (unsigned long)dst +
	62	+ roundup(len, ARCH_DMA_MINALIGN));
	63	+
	64	+ return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len);
	65	+}
	66	+
	67	+UCLASS_DRIVER(dma) = {
	68	+ .id = UCLASS_DMA,
	69	+ .name = "dma",
	70	+ .flags = DM_UC_FLAG_SEQ_ALIAS,
	71	+ .per_device_auto_alloc_size = sizeof(struct dma_dev_priv),
	72	+};
...	...	@@ -31,6 +31,7 @@
31	31	UCLASS_CROS_EC, /* Chrome OS EC */
32	32	UCLASS_DISK, /* Disk controller, e.g. SATA */
33	33	UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
	34	+ UCLASS_DMA, /* Direct Memory Access */
34	35	UCLASS_RAM, /* RAM controller */
35	36	UCLASS_ETH, /* Ethernet device */
36	37	UCLASS_GPIO, /* Bank of general-purpose I/O pins */