kmp204x: set CPU watchdog reset reason flag

Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>

kmp204x: set CPU watchdog reset reason flag
Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Boschung, Rainer · York Sun
1 parent 807d93d6de
Showing 1 changed file with 12 additions and 0 deletions Side-by-side Diff
board/keymile/kmp204x/kmp204x.c
@@ -80,13 +80,25 @@
  
 #define ZL30158_RST	8
 #define BFTIC4_RST	0
+#define RSTRQSR1_WDT_RR	0x00200000
+#define RSTRQSR1_SW_RR	0x00100000
  
 int board_early_init_f(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	bool cpuwd_flag = false;
  
 	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
 	setbits_be32(&gur->ddrclkdr, 0x001f000f);
+
+	/* set reset reason according CPU register */
+	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+	    RSTRQSR1_WDT_RR)
+		cpuwd_flag = true;
+
+	qrio_cpuwd_flag(cpuwd_flag);
+	/* clear CPU bits by writing 1 */
+	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  
 	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
 	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
...	...	@@ -80,13 +80,25 @@
80	80
81	81	#define ZL30158_RST 8
82	82	#define BFTIC4_RST 0
	83	+#define RSTRQSR1_WDT_RR 0x00200000
	84	+#define RSTRQSR1_SW_RR 0x00100000
83	85
84	86	int board_early_init_f(void)
85	87	{
86	88	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	89	+ bool cpuwd_flag = false;
87	90
88	91	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
89	92	setbits_be32(&gur->ddrclkdr, 0x001f000f);
	93	+
	94	+ /* set reset reason according CPU register */
	95	+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR)) ==
	96	+ RSTRQSR1_WDT_RR)
	97	+ cpuwd_flag = true;
	98	+
	99	+ qrio_cpuwd_flag(cpuwd_flag);
	100	+ /* clear CPU bits by writing 1 */
	101	+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR);
90	102
91	103	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
92	104	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);