dm: arm64: ls1012a: add i2c DM support

This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

dm: arm64: ls1012a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li · Priyanka Jain
1 parent 6089d8ab31
Showing 21 changed files with 230 additions and 28 deletions Side-by-side Diff
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/include/asm/gpio.h
board/freescale/ls1012aqds/ls1012aqds.c
board/freescale/ls1012ardb/eth.c
board/freescale/ls1012ardb/ls1012ardb.c
configs/ls1012a2g5rdb_qspi_defconfig
configs/ls1012a2g5rdb_tfa_defconfig
configs/ls1012afrdm_qspi_defconfig
configs/ls1012afrdm_tfa_defconfig
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
configs/ls1012afrwy_qspi_defconfig
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
configs/ls1012afrwy_tfa_defconfig
configs/ls1012aqds_qspi_defconfig
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
configs/ls1012aqds_tfa_defconfig
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
configs/ls1012ardb_qspi_defconfig
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
configs/ls1012ardb_tfa_defconfig
@@ -16,8 +16,8 @@
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
+	select SYS_I2C_MXC_I2C1 if !DM_I2C
+	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	imply PANIC_HANG
  
 config ARCH_LS1028A
@@ -4,6 +4,7 @@
 	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
 	!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
 	!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
+	!defined(CONFIG_ARCH_LS1012A) && \
 	!defined(CONFIG_ARCH_U8500)
 #include <asm/arch/gpio.h>
 #endif
@@ -107,10 +107,26 @@
 int misc_init_r(void)
 {
 	u8 mux_sdhc_cd = 0x80;
+	int bus_num = 0;
  
-	i2c_set_bus_num(0);
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
  
+	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
+#else
+	i2c_set_bus_num(bus_num);
+
 	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+#endif
+
 	return 0;
 }
 #endif
@@ -28,12 +28,47 @@
 {
 #ifdef CONFIG_TARGET_LS1012ARDB
 	/* Through reset IO expander reset both RGMII and SGMII PHYs */
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
+	 */
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       0);
+		return;
+	}
+	/* Config port 0
+	 * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
+	 *   are enabled as an output.
+	 */
+	dm_i2c_reg_write(dev, 6, __PHY_MASK);
+
+	/*
+	 * Set port 0 output a value to reset ETH2 interface
+	 * - pin IOXP_RST_ETH2_B output 0b0
+	 */
+	dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
+	mdelay(10);
+	dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
+	/*
+	 * Set port 0 output a value to reset ETH1 interface
+	 * - pin IOXP_RST_ETH1_B output 0b0
+	 */
+	mdelay(10);
+	dm_i2c_reg_write(dev, 2, 0xFF);
+#else
 	i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
 	mdelay(10);
 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
 	mdelay(10);
 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+#endif
 	mdelay(50);
 #endif
 }
@@ -34,13 +34,27 @@
 {
 #ifdef CONFIG_TARGET_LS1012ARDB
 	u8 in1;
+	int ret, bus_num = 0;
  
 	puts("Board: LS1012ARDB ");
  
 	/* Initialize i2c early for Serial flash bank information */
-	i2c_set_bus_num(0);
+#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
  
-	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+	ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
+#endif
+	if (ret < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
  
  
  
@@ -175,11 +189,25 @@
 	bool sdhc2_en = false;
 	u8 mux_sdhc2;
 	u8 io = 0;
+	int ret, bus_num = 0;
  
-	i2c_set_bus_num(0);
+#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
  
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
+#else
+	i2c_set_bus_num(bus_num);
 	/* IO1[7:3] is the field of board revision info. */
-	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
+	ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
+#endif
+	if (ret < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0;
 	}
@@ -202,7 +230,12 @@
 		 *	10 - eMMC Memory
 		 *	11 - SPI
 		 */
-		if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
+#if defined(CONFIG_DM_I2C)
+		ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
+#else
+		ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
+#endif
+		if (ret < 0) {
 			printf("Error reading i2c boot information!\n");
 			return 0;
 		}
  
  
  
  
@@ -233,16 +266,63 @@
  
 static int switch_to_bank1(void)
 {
-	u8 data;
-	int ret;
+	u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
+	int ret, bus_num = 0;
  
-	i2c_set_bus_num(0);
+#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
  
-	data = 0xf4;
-	ret = i2c_write(0x24, 0x3, 1, &data, 1);
+	ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
+				      1, &dev);
 	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+	/*
+	 * --------------------------------------------------------------------
+	 * |bus |I2C address|       Device     |          Notes               |
+	 * --------------------------------------------------------------------
+	 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General   |
+	 * |    |0x26	    | RESET, and INT/  | Purpose parallel Input/Output|
+	 * |    |           | KW41GPIO) - NXP  | (GPIO) expansion for the     |
+	 * |    |           | PCAL9555AHF      | I2C bus                      |
+	 * ----- --------------------------------------------------------------
+	 * - mount three IO expander(PCAL9555AHF) on I2C1
+	 *
+	 * PCAL9555A device address
+	 *           slave address
+	 *  --------------------------------------
+	 *  | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
+	 *  --------------------------------------
+	 *  |     fixed     | hardware selectable|
+	 *
+	 * Output port 1(Pinter register bits = 0x03)
+	 *
+	 * P1_[7~0] = 0xf4
+	 * P1_0 <---> CFG_MUX_QSPI_S0
+	 * P1_1 <---> CFG_MUX_QSPI_S1
+	 * CFG_MUX_QSPI_S[1:0] = 0b00
+	 *
+	 * QSPI chip-select demultiplexer select
+	 * ---------------------------------------------------------------------
+	 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0|              Values
+	 * ---------------------------------------------------------------------
+	 *    0           | 0            |CS routed to SPI memory bank1(default)
+	 * ---------------------------------------------------------------------
+	 *    0           | 1             |CS routed to SPI memory bank2
+	 * ---------------------------------------------------------------------
+	 *
+	 */
+	ret = dm_i2c_write(dev, offset_addr, &data, 1);
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+	ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
+#endif
+
+	if (ret) {
 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
-		       0x24, 0x3, data);
+		       chip_addr, offset_addr, data);
 	}
  
 	return ret;
  
  
  
  
  
  
@@ -250,25 +330,45 @@
  
 static int switch_to_bank2(void)
 {
-	u8 data;
-	int ret;
+	u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
+	u8 chip_addr = 0x24;
+	int ret, i, bus_num = 0;
  
-	i2c_set_bus_num(0);
+#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
  
-	data = 0xfc;
-	ret = i2c_write(0x24, 0x7, 1, &data, 1);
+	ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
+				      1, &dev);
 	if (ret) {
-		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
-		       0x24, 0x7, data);
-		goto err;
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
 	}
+#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
+#endif
  
-	data = 0xf5;
-	ret = i2c_write(0x24, 0x3, 1, &data, 1);
-	if (ret) {
-		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
-		       0x24, 0x3, data);
+	/*
+	 * 1th step: config port 1
+	 *	- the port 1 pin is enabled as an output
+	 * 2th step: output port 1
+	 *	- P1_[7:0] output 0xf5,
+	 *	  then CFG_MUX_QSPI_S[1:0] equal to 0b01,
+	 *	  CS routed to SPI memory bank2
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+#if defined(CONFIG_DM_I2C)
+		ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
+#else /* Non DM I2C support - will be removed */
+		ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
+#endif
+		if (ret) {
+			printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+			       chip_addr, offset_addr[i], data[i]);
+			goto err;
+		}
 	}
+
 err:
 	return ret;
 }
@@ -52,4 +52,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -52,4 +52,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -52,4 +52,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -52,4 +52,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -54,4 +54,7 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -54,4 +54,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -55,4 +55,7 @@
 CONFIG_RSA=y
 CONFIG_CMD_SETEXPR=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -60,4 +60,7 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -76,4 +76,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -68,4 +68,7 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -76,4 +76,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -58,4 +58,7 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -60,4 +60,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -58,4 +58,7 @@
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -61,4 +61,7 @@
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_RTC=y
@@ -66,7 +66,12 @@
 						CONFIG_SYS_SCSI_MAX_LUN)
  
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
+#endif
  
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
...	...	@@ -16,8 +16,8 @@
16	16	select ARCH_EARLY_INIT_R
17	17	select BOARD_EARLY_INIT_F
18	18	select SYS_I2C_MXC
19		- select SYS_I2C_MXC_I2C1
20		- select SYS_I2C_MXC_I2C2
	19	+ select SYS_I2C_MXC_I2C1 if !DM_I2C
	20	+ select SYS_I2C_MXC_I2C2 if !DM_I2C
21	21	imply PANIC_HANG
22	22
23	23	config ARCH_LS1028A
...	...	@@ -4,6 +4,7 @@
4	4	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
5	5	!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
6	6	!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
	7	+ !defined(CONFIG_ARCH_LS1012A) && \
7	8	!defined(CONFIG_ARCH_U8500)
8	9	#include <asm/arch/gpio.h>
9	10	#endif
...	...	@@ -107,10 +107,26 @@
107	107	int misc_init_r(void)
108	108	{
109	109	u8 mux_sdhc_cd = 0x80;
	110	+ int bus_num = 0;
110	111
111		- i2c_set_bus_num(0);
	112	+#ifdef CONFIG_DM_I2C
	113	+ struct udevice *dev;
	114	+ int ret;
112	115
	116	+ ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
	117	+ 1, &dev);
	118	+ if (ret) {
	119	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	120	+ bus_num);
	121	+ return ret;
	122	+ }
	123	+ dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
	124	+#else
	125	+ i2c_set_bus_num(bus_num);
	126	+
113	127	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
	128	+#endif
	129	+
114	130	return 0;
115	131	}
116	132	#endif
...	...	@@ -28,12 +28,47 @@
28	28	{
29	29	#ifdef CONFIG_TARGET_LS1012ARDB
30	30	/* Through reset IO expander reset both RGMII and SGMII PHYs */
	31	+#ifdef CONFIG_DM_I2C
	32	+ struct udevice *dev;
	33	+ int ret;
	34	+
	35	+ /*
	36	+ * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
	37	+ */
	38	+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
	39	+ 1, &dev);
	40	+ if (ret) {
	41	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	42	+ 0);
	43	+ return;
	44	+ }
	45	+ /* Config port 0
	46	+ * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
	47	+ * are enabled as an output.
	48	+ */
	49	+ dm_i2c_reg_write(dev, 6, __PHY_MASK);
	50	+
	51	+ /*
	52	+ * Set port 0 output a value to reset ETH2 interface
	53	+ * - pin IOXP_RST_ETH2_B output 0b0
	54	+ */
	55	+ dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
	56	+ mdelay(10);
	57	+ dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
	58	+ /*
	59	+ * Set port 0 output a value to reset ETH1 interface
	60	+ * - pin IOXP_RST_ETH1_B output 0b0
	61	+ */
	62	+ mdelay(10);
	63	+ dm_i2c_reg_write(dev, 2, 0xFF);
	64	+#else
31	65	i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
32	66	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
33	67	mdelay(10);
34	68	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
35	69	mdelay(10);
36	70	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
	71	+#endif
37	72	mdelay(50);
38	73	#endif
39	74	}
...	...	@@ -34,13 +34,27 @@
34	34	{
35	35	#ifdef CONFIG_TARGET_LS1012ARDB
36	36	u8 in1;
	37	+ int ret, bus_num = 0;
37	38
38	39	puts("Board: LS1012ARDB ");
39	40
40	41	/* Initialize i2c early for Serial flash bank information */
41		- i2c_set_bus_num(0);
	42	+#if defined(CONFIG_DM_I2C)
	43	+ struct udevice *dev;
42	44
43		- if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
	45	+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
	46	+ 1, &dev);
	47	+ if (ret) {
	48	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	49	+ bus_num);
	50	+ return -ENXIO;
	51	+ }
	52	+ ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
	53	+#else /* Non DM I2C support - will be removed */
	54	+ i2c_set_bus_num(bus_num);
	55	+ ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
	56	+#endif
	57	+ if (ret < 0) {
44	58	printf("Error reading i2c boot information!\n");
45	59	return 0; /* Don't want to hang() on this error */
46	60	}
47	61
48	62
49	63
...	...	@@ -175,11 +189,25 @@
175	189	bool sdhc2_en = false;
176	190	u8 mux_sdhc2;
177	191	u8 io = 0;
	192	+ int ret, bus_num = 0;
178	193
179		- i2c_set_bus_num(0);
	194	+#if defined(CONFIG_DM_I2C)
	195	+ struct udevice *dev;
180	196
	197	+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
	198	+ 1, &dev);
	199	+ if (ret) {
	200	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	201	+ bus_num);
	202	+ return -ENXIO;
	203	+ }
	204	+ ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
	205	+#else
	206	+ i2c_set_bus_num(bus_num);
181	207	/* IO1[7:3] is the field of board revision info. */
182		- if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
	208	+ ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
	209	+#endif
	210	+ if (ret < 0) {
183	211	printf("Error reading i2c boot information!\n");
184	212	return 0;
185	213	}
...	...	@@ -202,7 +230,12 @@
202	230	* 10 - eMMC Memory
203	231	* 11 - SPI
204	232	*/
205		- if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
	233	+#if defined(CONFIG_DM_I2C)
	234	+ ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
	235	+#else
	236	+ ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
	237	+#endif
	238	+ if (ret < 0) {
206	239	printf("Error reading i2c boot information!\n");
207	240	return 0;
208	241	}
209	242
210	243
211	244
212	245
...	...	@@ -233,16 +266,63 @@
233	266
234	267	static int switch_to_bank1(void)
235	268	{
236		- u8 data;
237		- int ret;
	269	+ u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
	270	+ int ret, bus_num = 0;
238	271
239		- i2c_set_bus_num(0);
	272	+#if defined(CONFIG_DM_I2C)
	273	+ struct udevice *dev;
240	274
241		- data = 0xf4;
242		- ret = i2c_write(0x24, 0x3, 1, &data, 1);
	275	+ ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
	276	+ 1, &dev);
243	277	if (ret) {
	278	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	279	+ bus_num);
	280	+ return -ENXIO;
	281	+ }
	282	+ /*
	283	+ * --------------------------------------------------------------------
	284	+ * \|bus \|I2C address\| Device \| Notes \|
	285	+ * --------------------------------------------------------------------
	286	+ * \|I2C1\|0x24, 0x25,\| IO expander (CFG,\| Provides 16bits of General \|
	287	+ * \| \|0x26 \| RESET, and INT/ \| Purpose parallel Input/Output\|
	288	+ * \| \| \| KW41GPIO) - NXP \| (GPIO) expansion for the \|
	289	+ * \| \| \| PCAL9555AHF \| I2C bus \|
	290	+ * ----- --------------------------------------------------------------
	291	+ * - mount three IO expander(PCAL9555AHF) on I2C1
	292	+ *
	293	+ * PCAL9555A device address
	294	+ * slave address
	295	+ * --------------------------------------
	296	+ * \| 0 \| 1 \| 0 \| 0 \| A2 \| A1 \| A0 \| R/W \|
	297	+ * --------------------------------------
	298	+ * \| fixed \| hardware selectable\|
	299	+ *
	300	+ * Output port 1(Pinter register bits = 0x03)
	301	+ *
	302	+ * P1_[7~0] = 0xf4
	303	+ * P1_0 <---> CFG_MUX_QSPI_S0
	304	+ * P1_1 <---> CFG_MUX_QSPI_S1
	305	+ * CFG_MUX_QSPI_S[1:0] = 0b00
	306	+ *
	307	+ * QSPI chip-select demultiplexer select
	308	+ * ---------------------------------------------------------------------
	309	+ * CFG_MUX_QSPI_S1\|CFG_MUX_QSPI_S0\| Values
	310	+ * ---------------------------------------------------------------------
	311	+ * 0 \| 0 \|CS routed to SPI memory bank1(default)
	312	+ * ---------------------------------------------------------------------
	313	+ * 0 \| 1 \|CS routed to SPI memory bank2
	314	+ * ---------------------------------------------------------------------
	315	+ *
	316	+ */
	317	+ ret = dm_i2c_write(dev, offset_addr, &data, 1);
	318	+#else /* Non DM I2C support - will be removed */
	319	+ i2c_set_bus_num(bus_num);
	320	+ ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
	321	+#endif
	322	+
	323	+ if (ret) {
244	324	printf("i2c write error to chip : %u, addr : %u, data : %u\n",
245		- 0x24, 0x3, data);
	325	+ chip_addr, offset_addr, data);
246	326	}
247	327
248	328	return ret;
249	329
250	330
251	331
252	332
253	333
254	334
...	...	@@ -250,25 +330,45 @@
250	330
251	331	static int switch_to_bank2(void)
252	332	{
253		- u8 data;
254		- int ret;
	333	+ u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
	334	+ u8 chip_addr = 0x24;
	335	+ int ret, i, bus_num = 0;
255	336
256		- i2c_set_bus_num(0);
	337	+#if defined(CONFIG_DM_I2C)
	338	+ struct udevice *dev;
257	339
258		- data = 0xfc;
259		- ret = i2c_write(0x24, 0x7, 1, &data, 1);
	340	+ ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
	341	+ 1, &dev);
260	342	if (ret) {
261		- printf("i2c write error to chip : %u, addr : %u, data : %u\n",
262		- 0x24, 0x7, data);
263		- goto err;
	343	+ printf("%s: Cannot find udev for a bus %d\n", __func__,
	344	+ bus_num);
	345	+ return -ENXIO;
264	346	}
	347	+#else /* Non DM I2C support - will be removed */
	348	+ i2c_set_bus_num(bus_num);
	349	+#endif
265	350
266		- data = 0xf5;
267		- ret = i2c_write(0x24, 0x3, 1, &data, 1);
268		- if (ret) {
269		- printf("i2c write error to chip : %u, addr : %u, data : %u\n",
270		- 0x24, 0x3, data);
	351	+ /*
	352	+ * 1th step: config port 1
	353	+ * - the port 1 pin is enabled as an output
	354	+ * 2th step: output port 1
	355	+ * - P1_[7:0] output 0xf5,
	356	+ * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
	357	+ * CS routed to SPI memory bank2
	358	+ */
	359	+ for (i = 0; i < sizeof(data); i++) {
	360	+#if defined(CONFIG_DM_I2C)
	361	+ ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
	362	+#else /* Non DM I2C support - will be removed */
	363	+ ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
	364	+#endif
	365	+ if (ret) {
	366	+ printf("i2c write error to chip : %u, addr : %u, data : %u\n",
	367	+ chip_addr, offset_addr[i], data[i]);
	368	+ goto err;
	369	+ }
271	370	}
	371	+
272	372	err:
273	373	return ret;
274	374	}
...	...	@@ -52,4 +52,7 @@
52	52	CONFIG_DM_USB=y
53	53	CONFIG_USB_XHCI_HCD=y
54	54	CONFIG_USB_XHCI_DWC3=y
	55	+CONFIG_DM_I2C=y
	56	+CONFIG_DM_GPIO=y
	57	+CONFIG_DM_RTC=y
...	...	@@ -54,4 +54,7 @@
54	54	CONFIG_USB_XHCI_DWC3=y
55	55	CONFIG_RSA=y
56	56	CONFIG_RSA_SOFTWARE_EXP=y
	57	+CONFIG_DM_I2C=y
	58	+CONFIG_DM_GPIO=y
	59	+CONFIG_DM_RTC=y
...	...	@@ -55,4 +55,7 @@
55	55	CONFIG_RSA=y
56	56	CONFIG_CMD_SETEXPR=y
57	57	CONFIG_RSA_SOFTWARE_EXP=y
	58	+CONFIG_DM_I2C=y
	59	+CONFIG_DM_GPIO=y
	60	+CONFIG_DM_RTC=y
...	...	@@ -60,4 +60,7 @@
60	60	CONFIG_USB_HOST_ETHER=y
61	61	CONFIG_USB_ETHER_RTL8152=y
62	62	CONFIG_USB_XHCI_DWC3=y
	63	+CONFIG_DM_I2C=y
	64	+CONFIG_DM_GPIO=y
	65	+CONFIG_DM_RTC=y
...	...	@@ -76,4 +76,7 @@
76	76	CONFIG_DM_USB=y
77	77	CONFIG_USB_XHCI_HCD=y
78	78	CONFIG_USB_XHCI_DWC3=y
	79	+CONFIG_DM_I2C=y
	80	+CONFIG_DM_GPIO=y
	81	+CONFIG_DM_RTC=y