mmc: atmel_sdhci: Convert to the driver model support

Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Heiko Schocher <hs@denx.de>

mmc: atmel_sdhci: Convert to the driver model support
Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Wenyou Yang · Andreas Bießmann
1 parent 17b68b5a58
Showing 3 changed files with 135 additions and 0 deletions Side-by-side Diff
drivers/mmc/Kconfig
drivers/mmc/atmel_sdhci.c
include/sdhci.h
@@ -34,6 +34,16 @@
           SD 3.0 specifications. Both SD and eMMC devices are supported.
 	  Card-detect gpios are not supported.
  
+config ATMEL_SDHCI
+	bool "Atmel SDHCI controller support"
+	depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+	help
+	  This enables support for the Atmel SDHCI controller, which supports
+	  the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
+	  Memory Card Specification V3.0, and the SDIO V3.0 specification.
+	  It is compliant with the SD Host Controller Standard V3.0
+	  specification.
+
 config ROCKCHIP_DWMMC
 	bool "Rockchip SD/MMC controller support"
 	depends on DM_MMC && OF_CONTROL
@@ -6,12 +6,15 @@
  */
  
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/clk.h>
  
 #define ATMEL_SDHC_MIN_FREQ	400000
  
+#ifndef CONFIG_DM_MMC
 int atmel_sdhci_init(void *regbase, u32 id)
 {
 	struct sdhci_host *host;
@@ -38,4 +41,124 @@
  
 	return 0;
 }
+
+#else
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct atmel_sdhci_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk)
+{
+	struct udevice *dev_clk;
+	int periph, ret;
+
+	ret = clk_get_by_index(dev, index, clk);
+	if (ret)
+		return ret;
+
+	periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+	if (periph < 0)
+		return -EINVAL;
+
+	dev_clk = dev_get_parent(clk->dev);
+	ret = clk_request(dev_clk, clk);
+	if (ret)
+		return ret;
+
+	clk->id = periph;
+
+	return 0;
+}
+
+static int atmel_sdhci_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+	struct sdhci_host *host = dev_get_priv(dev);
+	u32 max_clk;
+	u32 caps, caps_1;
+	u32 clk_base, clk_mul;
+	ulong gck_rate;
+	struct clk clk;
+	int ret;
+
+	ret = atmel_sdhci_get_clk(dev, 0, &clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&clk);
+	if (ret)
+		return ret;
+
+	host->name = dev->name;
+	host->ioaddr = (void *)dev_get_addr(dev);
+
+	host->quirks = 0;
+	host->bus_width	= fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					 "bus-width", 4);
+
+	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+	clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+	caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+	clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
+	gck_rate = clk_base * 1000000 * (clk_mul + 1);
+
+	ret = atmel_sdhci_get_clk(dev, 1, &clk);
+	if (ret)
+		return ret;
+
+	ret = clk_set_rate(&clk, gck_rate);
+	if (ret)
+		return ret;
+
+	max_clk = clk_get_rate(&clk);
+	if (!max_clk)
+		return -EINVAL;
+
+	ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ);
+	if (ret)
+		return ret;
+
+	host->mmc = &plat->mmc;
+	host->mmc->dev = dev;
+	host->mmc->priv = host;
+	upriv->mmc = host->mmc;
+
+	clk_free(&clk);
+
+	return sdhci_probe(dev);
+}
+
+static int atmel_sdhci_bind(struct udevice *dev)
+{
+	struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id atmel_sdhci_ids[] = {
+	{ .compatible = "atmel,sama5d2-sdhci" },
+	{ }
+};
+
+U_BOOT_DRIVER(atmel_sdhci_drv) = {
+	.name		= "atmel_sdhci",
+	.id		= UCLASS_MMC,
+	.of_match	= atmel_sdhci_ids,
+	.ops		= &sdhci_ops,
+	.bind		= atmel_sdhci_bind,
+	.probe		= atmel_sdhci_probe,
+	.priv_auto_alloc_size = sizeof(struct sdhci_host),
+	.platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
+};
+#endif
@@ -166,6 +166,8 @@
 #define  SDHCI_CAN_64BIT	0x10000000
  
 #define SDHCI_CAPABILITIES_1	0x44
+#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
+#define  SDHCI_CLOCK_MUL_SHIFT	16
  
 #define SDHCI_MAX_CURRENT	0x48
...	...	@@ -34,6 +34,16 @@
34	34	SD 3.0 specifications. Both SD and eMMC devices are supported.
35	35	Card-detect gpios are not supported.
36	36
	37	+config ATMEL_SDHCI
	38	+ bool "Atmel SDHCI controller support"
	39	+ depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
	40	+ help
	41	+ This enables support for the Atmel SDHCI controller, which supports
	42	+ the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
	43	+ Memory Card Specification V3.0, and the SDIO V3.0 specification.
	44	+ It is compliant with the SD Host Controller Standard V3.0
	45	+ specification.
	46	+
37	47	config ROCKCHIP_DWMMC
38	48	bool "Rockchip SD/MMC controller support"
39	49	depends on DM_MMC && OF_CONTROL
...	...	@@ -6,12 +6,15 @@
6	6	*/
7	7
8	8	#include <common.h>
	9	+#include <clk.h>
	10	+#include <dm.h>
9	11	#include <malloc.h>
10	12	#include <sdhci.h>
11	13	#include <asm/arch/clk.h>
12	14
13	15	#define ATMEL_SDHC_MIN_FREQ 400000
14	16
	17	+#ifndef CONFIG_DM_MMC
15	18	int atmel_sdhci_init(void *regbase, u32 id)
16	19	{
17	20	struct sdhci_host *host;
...	...	@@ -38,4 +41,124 @@
38	41
39	42	return 0;
40	43	}
	44	+
	45	+#else
	46	+
	47	+DECLARE_GLOBAL_DATA_PTR;
	48	+
	49	+struct atmel_sdhci_plat {
	50	+ struct mmc_config cfg;
	51	+ struct mmc mmc;
	52	+};
	53	+
	54	+static int atmel_sdhci_get_clk(struct udevice dev, int index, struct clk clk)
	55	+{
	56	+ struct udevice *dev_clk;
	57	+ int periph, ret;
	58	+
	59	+ ret = clk_get_by_index(dev, index, clk);
	60	+ if (ret)
	61	+ return ret;
	62	+
	63	+ periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
	64	+ if (periph < 0)
	65	+ return -EINVAL;
	66	+
	67	+ dev_clk = dev_get_parent(clk->dev);
	68	+ ret = clk_request(dev_clk, clk);
	69	+ if (ret)
	70	+ return ret;
	71	+
	72	+ clk->id = periph;
	73	+
	74	+ return 0;
	75	+}
	76	+
	77	+static int atmel_sdhci_probe(struct udevice *dev)
	78	+{
	79	+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	80	+ struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
	81	+ struct sdhci_host *host = dev_get_priv(dev);
	82	+ u32 max_clk;
	83	+ u32 caps, caps_1;
	84	+ u32 clk_base, clk_mul;
	85	+ ulong gck_rate;
	86	+ struct clk clk;
	87	+ int ret;
	88	+
	89	+ ret = atmel_sdhci_get_clk(dev, 0, &clk);
	90	+ if (ret)
	91	+ return ret;
	92	+
	93	+ ret = clk_enable(&clk);
	94	+ if (ret)
	95	+ return ret;
	96	+
	97	+ host->name = dev->name;
	98	+ host->ioaddr = (void *)dev_get_addr(dev);
	99	+
	100	+ host->quirks = 0;
	101	+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	102	+ "bus-width", 4);
	103	+
	104	+ caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	105	+ clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
	106	+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	107	+ clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
	108	+ gck_rate = clk_base * 1000000 * (clk_mul + 1);
	109	+
	110	+ ret = atmel_sdhci_get_clk(dev, 1, &clk);
	111	+ if (ret)
	112	+ return ret;
	113	+
	114	+ ret = clk_set_rate(&clk, gck_rate);
	115	+ if (ret)
	116	+ return ret;
	117	+
	118	+ max_clk = clk_get_rate(&clk);
	119	+ if (!max_clk)
	120	+ return -EINVAL;
	121	+
	122	+ ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ);
	123	+ if (ret)
	124	+ return ret;
	125	+
	126	+ host->mmc = &plat->mmc;
	127	+ host->mmc->dev = dev;
	128	+ host->mmc->priv = host;
	129	+ upriv->mmc = host->mmc;
	130	+
	131	+ clk_free(&clk);
	132	+
	133	+ return sdhci_probe(dev);
	134	+}
	135	+
	136	+static int atmel_sdhci_bind(struct udevice *dev)
	137	+{
	138	+ struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
	139	+ int ret;
	140	+
	141	+ ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
	142	+ if (ret)
	143	+ return ret;
	144	+
	145	+ return 0;
	146	+}
	147	+
	148	+static const struct udevice_id atmel_sdhci_ids[] = {
	149	+ { .compatible = "atmel,sama5d2-sdhci" },
	150	+ { }
	151	+};
	152	+
	153	+U_BOOT_DRIVER(atmel_sdhci_drv) = {
	154	+ .name = "atmel_sdhci",
	155	+ .id = UCLASS_MMC,
	156	+ .of_match = atmel_sdhci_ids,
	157	+ .ops = &sdhci_ops,
	158	+ .bind = atmel_sdhci_bind,
	159	+ .probe = atmel_sdhci_probe,
	160	+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
	161	+ .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
	162	+};
	163	+#endif
...	...	@@ -166,6 +166,8 @@
166	166	#define SDHCI_CAN_64BIT 0x10000000
167	167
168	168	#define SDHCI_CAPABILITIES_1 0x44
	169	+#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
	170	+#define SDHCI_CLOCK_MUL_SHIFT 16
169	171
170	172	#define SDHCI_MAX_CURRENT 0x48
171	173