Eric Lee / smarc-uboot

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Commit a1d6dc3f84071f05574044f337dbdca70fae495d

Authored by Simon Glass
Committed by Bin Meng
1 parent 2153e8fbfc
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: Add chromebook_coral 

Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 11 changed files with 1296 additions and 0 deletions Side-by-side Diff

arch/x86/dts/Makefile
Diff comments   View file @ a1d6dc3
... ... @@ -2,6 +2,7 @@
2 2  
3 3 dtb-y += bayleybay.dtb \
4 4 cherryhill.dtb \
  5 + chromebook_coral.dtb \
5 6 chromebook_link.dtb \
6 7 chromebox_panther.dtb \
7 8 chromebook_samus.dtb \
arch/x86/dts/chromebook_coral.dts
Diff comments   View file @ a1d6dc3
  1 +/* SPDX-License-Identifier: GPL-2.0 */
  2 +/dts-v1/;
  3 +
  4 +#include <dt-bindings/gpio/x86-gpio.h>
  5 +
  6 +/include/ "skeleton.dtsi"
  7 +/include/ "keyboard.dtsi"
  8 +/include/ "reset.dtsi"
  9 +/include/ "rtc.dtsi"
  10 +/include/ "tsc_timer.dtsi"
  11 +
  12 +#ifdef CONFIG_CHROMEOS
  13 +#include "chromeos-x86.dtsi"
  14 +#include "flashmap-x86-ro.dtsi"
  15 +#include "flashmap-16mb-rw.dtsi"
  16 +#endif
  17 +
  18 +#include <asm/intel_pinctrl_defs.h>
  19 +#include <asm/arch-apollolake/cpu.h>
  20 +#include <asm/arch-apollolake/gpio.h>
  21 +#include <asm/arch-apollolake/iomap.h>
  22 +#include <asm/arch-apollolake/pm.h>
  23 +
  24 +/ {
  25 + model = "Google Coral";
  26 + compatible = "google,coral", "intel,apollolake";
  27 +
  28 + aliases {
  29 + cros-ec0 = &cros_ec;
  30 + fsp = &fsp_s;
  31 + spi0 = &spi;
  32 + };
  33 +
  34 + config {
  35 + silent_console = <0>;
  36 + };
  37 +
  38 + chosen {
  39 + stdout-path = &serial;
  40 + };
  41 +
  42 + cpus {
  43 + u-boot,dm-pre-reloc;
  44 + #address-cells = <1>;
  45 + #size-cells = <0>;
  46 +
  47 + cpu@0 {
  48 + u-boot,dm-pre-reloc;
  49 + device_type = "cpu";
  50 + compatible = "intel,apl-cpu";
  51 + reg = <0>;
  52 + intel,apic-id = <0>;
  53 + };
  54 +
  55 + cpu@1 {
  56 + device_type = "cpu";
  57 + compatible = "intel,apl-cpu";
  58 + reg = <1>;
  59 + intel,apic-id = <2>;
  60 + };
  61 +
  62 + cpu@2 {
  63 + device_type = "cpu";
  64 + compatible = "intel,apl-cpu";
  65 + reg = <2>;
  66 + intel,apic-id = <4>;
  67 + };
  68 +
  69 + cpu@3 {
  70 + device_type = "cpu";
  71 + compatible = "intel,apl-cpu";
  72 + reg = <3>;
  73 + intel,apic-id = <6>;
  74 + };
  75 +
  76 + };
  77 +
  78 + keyboard {
  79 + intel,duplicate-por;
  80 + };
  81 +
  82 + pci {
  83 + compatible = "pci-x86";
  84 + #address-cells = <3>;
  85 + #size-cells = <2>;
  86 + u-boot,dm-pre-reloc;
  87 + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  88 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
  89 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
  90 + u-boot,skip-auto-config-until-reloc;
  91 +
  92 + host_bridge: host-bridge@0,0 {
  93 + u-boot,dm-pre-reloc;
  94 + reg = <0x00000000 0 0 0 0>;
  95 + compatible = "intel,apl-hostbridge";
  96 + pciex-region-size = <0x10000000>;
  97 + /*
  98 + * Parameters used by the FSP-S binary blob. This is
  99 + * really unfortunate since these parameters mostly
  100 + * relate to drivers but we need them in one place. We
  101 + * could put them in the driver nodes easily, but then
  102 + * would have to scan each node to find them. So just
  103 + * dump them here for now.
  104 + */
  105 + fsp_s: fsp-s {
  106 + };
  107 + };
  108 +
  109 + punit@0,1 {
  110 + u-boot,dm-pre-reloc;
  111 + reg = <0x00000800 0 0 0 0>;
  112 + compatible = "intel,apl-punit";
  113 + };
  114 +
  115 + p2sb: p2sb@d,0 {
  116 + u-boot,dm-pre-reloc;
  117 + reg = <0x02006810 0 0 0 0>;
  118 + compatible = "intel,apl-p2sb";
  119 + early-regs = <IOMAP_P2SB_BAR 0x100000>;
  120 +
  121 + n {
  122 + compatible = "intel,apl-pinctrl";
  123 + u-boot,dm-pre-reloc;
  124 + intel,p2sb-port-id = <PID_GPIO_N>;
  125 + gpio_n: gpio-n {
  126 + compatible = "intel,gpio";
  127 + u-boot,dm-pre-reloc;
  128 + gpio-controller;
  129 + #gpio-cells = <2>;
  130 + };
  131 + };
  132 +
  133 + nw {
  134 + u-boot,dm-pre-reloc;
  135 + compatible = "intel,apl-pinctrl";
  136 + intel,p2sb-port-id = <PID_GPIO_NW>;
  137 + #gpio-cells = <2>;
  138 + gpio_nw: gpio-nw {
  139 + compatible = "intel,gpio";
  140 + u-boot,dm-pre-reloc;
  141 + gpio-controller;
  142 + #gpio-cells = <2>;
  143 + };
  144 + };
  145 +
  146 + w {
  147 + u-boot,dm-pre-reloc;
  148 + compatible = "intel,apl-pinctrl";
  149 + intel,p2sb-port-id = <PID_GPIO_W>;
  150 + #gpio-cells = <2>;
  151 + gpio_w: gpio-w {
  152 + compatible = "intel,gpio";
  153 + u-boot,dm-pre-reloc;
  154 + gpio-controller;
  155 + #gpio-cells = <2>;
  156 + };
  157 + };
  158 +
  159 + sw {
  160 + u-boot,dm-pre-reloc;
  161 + compatible = "intel,apl-pinctrl";
  162 + intel,p2sb-port-id = <PID_GPIO_SW>;
  163 + #gpio-cells = <2>;
  164 + gpio_sw: gpio-sw {
  165 + compatible = "intel,gpio";
  166 + u-boot,dm-pre-reloc;
  167 + gpio-controller;
  168 + #gpio-cells = <2>;
  169 + };
  170 + };
  171 +
  172 + itss {
  173 + u-boot,dm-pre-reloc;
  174 + compatible = "intel,apl-itss";
  175 + intel,p2sb-port-id = <PID_ITSS>;
  176 + intel,pmc-routes = <
  177 + PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
  178 + PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
  179 + PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
  180 + PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
  181 + PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
  182 + PMC_GPE_N_31_0 GPIO_GPE_N_31_0
  183 + PMC_GPE_N_63_32 GPIO_GPE_N_63_32
  184 + PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
  185 + };
  186 + };
  187 +
  188 + pmc@d,1 {
  189 + u-boot,dm-pre-reloc;
  190 + reg = <0x6900 0 0 0 0>;
  191 +
  192 + /*
  193 + * Values for BAR0, BAR2 and ACPI_BASE for when PCI
  194 + * auto-configure is not available
  195 + */
  196 + early-regs = <0xfe042000 0x2000
  197 + 0xfe044000 0x2000
  198 + IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  199 + compatible = "intel,apl-pmc";
  200 + gpe0-dwx-mask = <0xf>;
  201 + gpe0-dwx-shift-base = <4>;
  202 +
  203 + /*
  204 + * GPE configuration
  205 + * Note that GPE events called out in ASL code rely on
  206 + * this route, i.e., if this route changes then the
  207 + * affected GPE * offset bits also need to be changed.
  208 + * This sets the PMC register GPE_CFG fields.
  209 + */
  210 + gpe0-dw = <PMC_GPE_N_31_0
  211 + PMC_GPE_N_63_32
  212 + PMC_GPE_SW_31_0>;
  213 + gpe0-sts = <0x20>;
  214 + gpe0-en = <0x30>;
  215 + };
  216 +
  217 + spi: fast-spi@d,2 {
  218 + u-boot,dm-pre-reloc;
  219 + reg = <0x02006a10 0 0 0 0>;
  220 + #address-cells = <1>;
  221 + #size-cells = <0>;
  222 + compatible = "intel,fast-spi";
  223 + early-regs = <IOMAP_SPI_BASE 0x1000>;
  224 + intel,hardware-seq = <1>;
  225 +
  226 + fwstore_spi: spi-flash@0 {
  227 + #size-cells = <1>;
  228 + #address-cells = <1>;
  229 + u-boot,dm-pre-reloc;
  230 + reg = <0>;
  231 + compatible = "winbond,w25q128fw",
  232 + "jedec,spi-nor";
  233 + rw-mrc-cache {
  234 + label = "rw-mrc-cache";
  235 + reg = <0x008e0000 0x00010000>;
  236 + u-boot,dm-pre-reloc;
  237 + };
  238 + rw-var-mrc-cache {
  239 + label = "rw-mrc-cache";
  240 + reg = <0x008f0000 0x0001000>;
  241 + u-boot,dm-pre-reloc;
  242 + };
  243 + };
  244 + };
  245 +
  246 + serial: serial@18,2 {
  247 + reg = <0x0200c210 0 0 0 0>;
  248 + u-boot,dm-pre-reloc;
  249 + compatible = "intel,apl-ns16550";
  250 + early-regs = <0xde000000 0x20>;
  251 + reg-shift = <2>;
  252 + clock-frequency = <1843200>;
  253 + current-speed = <115200>;
  254 + };
  255 +
  256 + pch: pch@1f,0 {
  257 + reg = <0x0000f800 0 0 0 0>;
  258 + compatible = "intel,apl-pch";
  259 + u-boot,dm-pre-reloc;
  260 + #address-cells = <1>;
  261 + #size-cells = <1>;
  262 +
  263 + lpc {
  264 + compatible = "intel,apl-lpc";
  265 + #address-cells = <1>;
  266 + #size-cells = <0>;
  267 + u-boot,dm-pre-reloc;
  268 + cros_ec: cros-ec {
  269 + u-boot,dm-pre-reloc;
  270 + compatible = "google,cros-ec-lpc";
  271 + reg = <0x204 1 0x200 1 0x880 0x80>;
  272 +
  273 + /*
  274 + * Describes the flash memory within
  275 + * the EC
  276 + */
  277 + #address-cells = <1>;
  278 + #size-cells = <1>;
  279 + flash@8000000 {
  280 + reg = <0x08000000 0x20000>;
  281 + erase-value = <0xff>;
  282 + };
  283 + };
  284 + };
  285 + };
  286 + };
  287 +
  288 +};
  289 +
  290 +&host_bridge {
  291 + /*
  292 + * PL1 override 12000 mW: the energy calculation is wrong with the
  293 + * current VR solution. Experiments show that SoC TDP max (6W) can be
  294 + * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
  295 + */
  296 + tdp-pl-override-mw = <12000 15000>;
  297 +
  298 + early-pads = <
  299 + /* These two are for the debug UART */
  300 + GPIO_46 /* UART2 RX */
  301 + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  302 + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  303 +
  304 + GPIO_47 /* UART2 TX */
  305 + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  306 + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  307 +
  308 + GPIO_75 /* I2S1_BCLK -- PCH_WP */
  309 + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
  310 + (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
  311 +
  312 + /* I2C2 - TPM */
  313 + GPIO_128 /* LPSS_I2C2_SDA */
  314 + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  315 + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  316 + GPIO_129 /* LPSS_I2C2_SCL */
  317 + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  318 + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  319 + GPIO_28 /* TPM IRQ */
  320 + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  321 + PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
  322 + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
  323 + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
  324 +
  325 + /*
  326 + * WLAN_PE_RST - default to deasserted just in case FSP
  327 + * misbehaves
  328 + */
  329 + GPIO_122 /* SIO_SPI_2_RXD */
  330 + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  331 + PAD_CFG0_RX_DISABLE | 0)
  332 + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  333 +
  334 + /* LPC */
  335 + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  336 + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  337 + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  338 + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  339 + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  340 + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  341 + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  342 + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  343 + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  344 + >;
  345 +
  346 + lpddr4-swizzle = /bits/ 8 <
  347 + /* LP4_PHYS_CH0A */
  348 +
  349 + /* DQA[0:7] pins of LPDDR4 module */
  350 + 6 7 5 4 3 1 0 2
  351 + /* DQA[8:15] pins of LPDDR4 module */
  352 + 12 10 11 13 14 8 9 15
  353 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  354 + 16 22 23 20 18 17 19 21
  355 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  356 + 30 28 29 25 24 26 27 31
  357 +
  358 + /* LP4_PHYS_CH0B */
  359 + /* DQA[0:7] pins of LPDDR4 module */
  360 + 7 3 5 2 6 0 1 4
  361 + /* DQA[8:15] pins of LPDDR4 module */
  362 + 9 14 12 13 10 11 8 15
  363 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  364 + 20 22 23 16 19 17 18 21
  365 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  366 + 28 24 26 27 29 30 31 25
  367 +
  368 + /* LP4_PHYS_CH1A */
  369 +
  370 + /* DQA[0:7] pins of LPDDR4 module */
  371 + 2 1 6 7 5 4 3 0
  372 + /* DQA[8:15] pins of LPDDR4 module */
  373 + 11 10 8 9 12 15 13 14
  374 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  375 + 17 23 19 16 21 22 20 18
  376 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  377 + 31 29 26 25 28 27 24 30
  378 +
  379 + /* LP4_PHYS_CH1B */
  380 +
  381 + /* DQA[0:7] pins of LPDDR4 module */
  382 + 4 3 7 5 6 1 0 2
  383 + /* DQA[8:15] pins of LPDDR4 module */
  384 + 15 9 8 11 14 13 12 10
  385 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  386 + 20 23 22 21 18 19 16 17
  387 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  388 + 25 28 30 31 26 27 24 29>;
  389 +};
  390 +
  391 +&fsp_s {
  392 + u-boot,dm-pre-proper;
  393 +
  394 + /* Disable unused clkreq of PCIe root ports */
  395 + pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
  396 + CLKREQ_DISABLED
  397 + CLKREQ_DISABLED
  398 + CLKREQ_DISABLED
  399 + CLKREQ_DISABLED
  400 + CLKREQ_DISABLED>;
  401 +
  402 + /*
  403 + * GPIO for PERST_0
  404 + * If the Board has PERST_0 signal, assign the GPIO
  405 + * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
  406 + *
  407 + * This are not used yet, so comment them out for now.
  408 + *
  409 + * prt0-gpio = <GPIO_122>;
  410 + *
  411 + * GPIO for SD card detect
  412 + * sdcard-cd-gpio = <GPIO_177>;
  413 + */
  414 +
  415 + /*
  416 + * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
  417 + * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
  418 + *
  419 + * EMMC TX DATA Delay 1
  420 + * Refer to EDS-Vol2-22.3
  421 + * [14:8] steps of delay for HS400, each 125ps
  422 + * [6:0] steps of delay for SDR104/HS200, each 125ps
  423 +
  424 + /*
  425 + * EMMC TX DATA Delay 2
  426 + * Refer to EDS-Vol2-22.3.
  427 + * [30:24] steps of delay for SDR50, each 125ps
  428 + * [22:16] steps of delay for DDR50, each 125ps
  429 + * [14:8] steps of delay for SDR25/HS50, each 125ps
  430 + * [6:0] steps of delay for SDR12, each 125ps
  431 + */
  432 +
  433 + /*
  434 + * EMMC RX CMD/DATA Delay 1
  435 + * Refer to EDS-Vol2-22.3.
  436 + * [30:24] steps of delay for SDR50, each 125ps
  437 + * [22:16] steps of delay for DDR50, each 125ps
  438 + * [14:8] steps of delay for SDR25/HS50, each 125ps
  439 + * [6:0] steps of delay for SDR12, each 125ps
  440 + */
  441 +
  442 + /*
  443 + * EMMC RX CMD/DATA Delay 2
  444 + * Refer to EDS-Vol2-22.3.
  445 + * [17:16] stands for Rx Clock before Output Buffer
  446 + * [14:8] steps of delay for Auto Tuning Mode, each 125ps
  447 + * [6:0] steps of delay for HS200, each 125ps
  448 + */
  449 + emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
  450 +
  451 + /* Enable DPTF */
  452 + dptf-enable;
  453 +
  454 + /* Enable Audio Clock and Power gating */
  455 + hdaudio-clk-gate-enable;
  456 + hdaudio-pwr-gate-enable;
  457 + hdaudio-bios-config-lockdown;
  458 +
  459 + /* Enable lpss s0ix */
  460 + lpss-s0ix-enable;
  461 +
  462 + /*
  463 + * TODO(sjg@chromium.org): Move this to the I2C nodes
  464 + * Intel Common SoC Config
  465 + *+-------------------+---------------------------+
  466 + *| Field | Value |
  467 + *+-------------------+---------------------------+
  468 + *| I2C0 | Audio |
  469 + *| I2C2 | TPM |
  470 + *| I2C3 | Touchscreen |
  471 + *| I2C4 | Trackpad |
  472 + *| I2C5 | Digitizer |
  473 + *+-------------------+---------------------------+
  474 + *
  475 + common_soc_config" = "{
  476 + .i2c[0] = {
  477 + .speed = I2C_SPEED_FAST,
  478 + .rise-time-ns = 104,
  479 + .fall-time-ns = 52,
  480 + },
  481 + .i2c[2] = {
  482 + .early_init = 1,
  483 + .speed = I2C_SPEED_FAST,
  484 + .rise-time-ns = 57,
  485 + .fall-time-ns = 28,
  486 + },
  487 + .i2c[3] = {
  488 + .speed = I2C_SPEED_FAST,
  489 + .rise-time-ns = 76,
  490 + .fall-time-ns = 164,
  491 + },
  492 + .i2c[4] = {
  493 + .speed = I2C_SPEED_FAST,
  494 + .rise-time-ns = 114,
  495 + .fall-time-ns = 164,
  496 + .data_hold_time_ns = 350,
  497 + },
  498 + .i2c[5] = {
  499 + .speed = I2C_SPEED_FAST,
  500 + .rise-time-ns = 152,
  501 + .fall-time-ns = 30,
  502 + },
  503 + }"
  504 + */
  505 +
  506 + /* Minimum SLP S3 assertion width 28ms */
  507 + slp-s3-assertion-width-usecs = <28000>;
  508 +
  509 + pads = <
  510 + /* PCIE_WAKE[0:3]_N */
  511 + PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
  512 + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */
  513 + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */
  514 + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */
  515 +
  516 + /* EMMC interface */
  517 + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
  518 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
  519 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
  520 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
  521 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
  522 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
  523 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
  524 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
  525 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
  526 + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
  527 + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
  528 +
  529 + /* SDIO -- unused */
  530 + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */
  531 + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */
  532 + /* Configure SDIO to enable power gating */
  533 + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
  534 + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */
  535 + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */
  536 + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */
  537 +
  538 + /* SDCARD */
  539 + /* Pull down clock by 20K */
  540 + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
  541 + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
  542 + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
  543 + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
  544 + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
  545 + /* Card detect is active LOW with external pull up */
  546 + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
  547 + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
  548 + /* CLK feedback, internal signal, needs 20K pull down */
  549 + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
  550 + /* No h/w write proect for uSD cards, pull down by 20K */
  551 + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
  552 + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
  553 + PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */
  554 +
  555 + /* SMBus -- unused */
  556 + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */
  557 + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */
  558 + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */
  559 +
  560 + /* LPC */
  561 + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  562 + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  563 + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  564 + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  565 + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  566 + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  567 + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  568 + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  569 + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  570 +
  571 + /* I2C0 - Audio */
  572 + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
  573 + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
  574 +
  575 + /* I2C1 - NFC with external pulls */
  576 + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
  577 + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
  578 +
  579 + /* I2C2 - TPM */
  580 + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
  581 + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
  582 +
  583 + /* I2C3 - touch */
  584 + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
  585 + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
  586 +
  587 + /* I2C4 - trackpad */
  588 + /* LPSS_I2C4_SDA */
  589 + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
  590 + /* LPSS_I2C4_SCL */
  591 + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
  592 +
  593 + /* I2C5 -- pen with external pulls */
  594 + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
  595 + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
  596 +
  597 + /* I2C6-7 -- unused */
  598 + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */
  599 + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */
  600 + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */
  601 + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */
  602 +
  603 + /* Audio Amp - I2S6 */
  604 + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
  605 + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
  606 + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */
  607 + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
  608 +
  609 + /* NFC Reset */
  610 + PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */
  611 +
  612 + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */
  613 +
  614 + /* Touch enable */
  615 + PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */
  616 +
  617 + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */
  618 + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */
  619 + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */
  620 +
  621 + /* PCIE_CLKREQ[0:3]_N */
  622 + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */
  623 + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */
  624 + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */
  625 + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */
  626 +
  627 + /* OSC_CLK_OUT_[0:4] -- unused */
  628 + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
  629 + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
  630 + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
  631 + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
  632 + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
  633 +
  634 + /* PMU Signals */
  635 + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
  636 + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
  637 + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
  638 + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
  639 + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
  640 + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
  641 + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
  642 + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
  643 + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
  644 + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */
  645 + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
  646 + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
  647 +
  648 + /* DDI[0:1] SDA and SCL -- unused */
  649 + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */
  650 + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */
  651 + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */
  652 + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */
  653 +
  654 + /* MIPI I2C -- unused */
  655 + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */
  656 + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */
  657 +
  658 + /* Panel 0 control */
  659 + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
  660 + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
  661 + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
  662 +
  663 + /* Panel 1 control -- unused */
  664 + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
  665 + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
  666 + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
  667 +
  668 + /* Hot plug detect */
  669 + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
  670 + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
  671 +
  672 + /* MDSI signals -- unused */
  673 + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */
  674 + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */
  675 +
  676 + /* USB overcurrent pins */
  677 + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
  678 + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
  679 +
  680 + /* PMC SPI -- almost entirely unused */
  681 + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
  682 + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
  683 + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
  684 + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
  685 + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
  686 + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
  687 +
  688 + /* PMIC Signals Unused signals related to an old PMIC interface */
  689 + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
  690 + PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */
  691 + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */
  692 + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */
  693 + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
  694 + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */
  695 + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
  696 + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
  697 + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
  698 +
  699 + /* I2S1 -- largely unused */
  700 + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */
  701 + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */
  702 + PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */
  703 + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */
  704 + PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
  705 +
  706 + /* DMIC or I2S4 */
  707 + /* AVS_DMIC_CLK_A1 */
  708 + PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
  709 + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
  710 + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */
  711 + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */
  712 + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
  713 +
  714 + /* I2S2 -- Headset amp */
  715 + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */
  716 + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */
  717 + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */
  718 + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */
  719 + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */
  720 +
  721 + /* I2S3 -- largely unused */
  722 + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */
  723 + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */
  724 + PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */
  725 + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */
  726 +
  727 + /* Fast SPI */
  728 + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
  729 + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */
  730 + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
  731 + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */
  732 + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
  733 + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
  734 + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */
  735 + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
  736 + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */
  737 +
  738 + /* SIO_SPI_0 - Used for FP */
  739 + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */
  740 + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */
  741 + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */
  742 + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */
  743 +
  744 + /* SIO_SPI_1 -- largely unused */
  745 + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */
  746 + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */
  747 + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */
  748 + /* Headset interrupt */
  749 + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
  750 + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */
  751 +
  752 + /* SIO_SPI_2 -- unused */
  753 + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */
  754 + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */
  755 + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */
  756 + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */
  757 + /* WLAN_PE_RST - default to deasserted */
  758 + PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */
  759 + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */
  760 +
  761 + /* Debug tracing */
  762 + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
  763 + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
  764 + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
  765 + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */
  766 + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
  767 + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
  768 + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
  769 + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
  770 + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
  771 +
  772 + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
  773 + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */
  774 + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */
  775 + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */
  776 + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
  777 + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
  778 + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */
  779 + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */
  780 + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */
  781 + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
  782 + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */
  783 + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
  784 + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
  785 + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
  786 + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */
  787 + PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */
  788 + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
  789 + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */
  790 + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */
  791 + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
  792 + PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */
  793 + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
  794 + PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */
  795 + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */
  796 + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
  797 + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */
  798 + PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */
  799 + PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */
  800 + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */
  801 +
  802 + /* LPSS_UART[0:2] */
  803 + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
  804 + /* Next 2 are straps */
  805 + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */
  806 + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */
  807 + PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */
  808 + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */
  809 + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */
  810 + PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */
  811 + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
  812 + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */
  813 + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
  814 + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */
  815 + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
  816 +
  817 + /* Camera interface -- completely unused */
  818 + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */
  819 + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */
  820 + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */
  821 + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */
  822 + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */
  823 + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */
  824 + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */
  825 + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */
  826 + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */
  827 + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */
  828 + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */
  829 + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
  830 + >;
  831 +};
board/google/Kconfig
Diff comments   View file @ a1d6dc3
... ... @@ -8,6 +8,20 @@
8 8 prompt "Mainboard model"
9 9 optional
10 10  
  11 +config TARGET_CHROMEBOOK_CORAL
  12 + bool "Chromebook coral"
  13 + help
  14 + This is a range of Intel-based laptops released in 2018. They use an
  15 + Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of
  16 + LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB),
  17 + up two cameras (front-facing 720p and another 5MP option), USB SD
  18 + reader, microphone and speakers. It also includes two USB 3 Type A and
  19 + two Type C ports. The latter are used as power input and can also
  20 + charge external devices as well as a 4K external display. There is a
  21 + Chrome OS EC connected on LPC, a Cr50 secure chip from Google and
  22 + various display options. OEMs products include Acer Chromebook 11
  23 + (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e).
  24 +
11 25 config TARGET_CHROMEBOOK_LINK
12 26 bool "Chromebook link"
13 27 help
... ... @@ -62,6 +76,7 @@
62 76  
63 77 endchoice
64 78  
  79 +source "board/google/chromebook_coral/Kconfig"
65 80 source "board/google/chromebook_link/Kconfig"
66 81 source "board/google/chromebox_panther/Kconfig"
67 82 source "board/google/chromebook_samus/Kconfig"
board/google/chromebook_coral/Kconfig
Diff comments   View file @ a1d6dc3
  1 +if TARGET_CHROMEBOOK_CORAL
  2 +
  3 +config SYS_BOARD
  4 + default "chromebook_coral"
  5 +
  6 +config SYS_VENDOR
  7 + default "google"
  8 +
  9 +config SYS_SOC
  10 + default "apollolake"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "chromebook_coral"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0xffe00000
  17 +
  18 +config BOARD_SPECIFIC_OPTIONS # dummy
  19 + def_bool y
  20 + select X86_RESET_VECTOR
  21 + select INTEL_APOLLOLAKE
  22 + select BOARD_ROMSIZE_KB_16384
  23 +
  24 +config PCIE_ECAM_BASE
  25 + default 0xf0000000
  26 +
  27 +config EARLY_POST_CROS_EC
  28 + bool "Enable early post to Chrome OS EC"
  29 + help
  30 + Allow post codes to be sent to the Chroem OS EC early during boot,
  31 + to enable monitoring of the boot and debugging when things go wrong.
  32 + With this option enabled, the EC console can be used to watch post
  33 + codes the first part of boot.
  34 +
  35 +config SYS_CAR_ADDR
  36 + hex
  37 + default 0xfef00000
  38 +
  39 +config SYS_CAR_SIZE
  40 + hex
  41 + default 0xc0000
  42 +
  43 +endif
board/google/chromebook_coral/MAINTAINERS
Diff comments   View file @ a1d6dc3
  1 +CHROMEBOOK_CORAL_BOARD
  2 +M: Simon Glass <sjg@chromium.org>
  3 +S: Maintained
  4 +F: board/google/chromebook_coral/
  5 +F: include/configs/chromebook_coral.h
  6 +F: configs/chromebook_coral_defconfig
board/google/chromebook_coral/Makefile
Diff comments   View file @ a1d6dc3
  1 +# SPDX-License-Identifier: GPL-2.0+
  2 +#
  3 +# Copyright 2019 Google LLC
  4 +
  5 +obj-y += coral.o
board/google/chromebook_coral/coral.c
Diff comments   View file @ a1d6dc3
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 Google LLC
  4 + */
  5 +
  6 +#include <common.h>
  7 +
  8 +int arch_misc_init(void)
  9 +{
  10 + return 0;
  11 +}
  12 +
  13 +/* This function is needed if CONFIG_CMDLINE is not enabled */
  14 +int board_run_command(const char *cmdline)
  15 +{
  16 + printf("No command line\n");
  17 +
  18 + return 0;
  19 +}
configs/chromebook_coral_defconfig
Diff comments   View file @ a1d6dc3
  1 +CONFIG_X86=y
  2 +CONFIG_SYS_TEXT_BASE=0x1110000
  3 +CONFIG_SYS_MALLOC_F_LEN=0x3d00
  4 +CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
  5 +CONFIG_NR_DRAM_BANKS=8
  6 +CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
  7 +CONFIG_DEBUG_UART_BOARD_INIT=y
  8 +CONFIG_DEBUG_UART_BASE=0xde000000
  9 +CONFIG_DEBUG_UART_CLOCK=1843200
  10 +CONFIG_VENDOR_GOOGLE=y
  11 +CONFIG_TARGET_CHROMEBOOK_CORAL=y
  12 +CONFIG_DEBUG_UART=y
  13 +CONFIG_FSP_VERSION2=y
  14 +CONFIG_HAVE_ACPI_RESUME=y
  15 +CONFIG_INTEL_CAR_CQOS=y
  16 +CONFIG_X86_OFFSET_U_BOOT=0xffe00000
  17 +CONFIG_X86_OFFSET_SPL=0xffe80000
  18 +CONFIG_SPL_TEXT_BASE=0xfef10000
  19 +CONFIG_BOOTSTAGE=y
  20 +CONFIG_SPL_BOOTSTAGE=y
  21 +CONFIG_TPL_BOOTSTAGE=y
  22 +CONFIG_BOOTSTAGE_REPORT=y
  23 +CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
  24 +CONFIG_BOOTSTAGE_STASH=y
  25 +CONFIG_USE_BOOTARGS=y
  26 +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200"
  27 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
  28 +CONFIG_SPL_LOG=y
  29 +CONFIG_LOG_DEFAULT_LEVEL=7
  30 +CONFIG_DISPLAY_BOARDINFO_LATE=y
  31 +CONFIG_LAST_STAGE_INIT=y
  32 +CONFIG_BLOBLIST=y
  33 +# CONFIG_TPL_BLOBLIST is not set
  34 +CONFIG_BLOBLIST_ADDR=0x100000
  35 +CONFIG_HANDOFF=y
  36 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
  37 +CONFIG_SPL_SEPARATE_BSS=y
  38 +CONFIG_SPL_CPU_SUPPORT=y
  39 +CONFIG_SPL_PCI=y
  40 +# CONFIG_SPL_SPI_FLASH_TINY is not set
  41 +CONFIG_HUSH_PARSER=y
  42 +CONFIG_CMD_CPU=y
  43 +CONFIG_CMD_PMC=y
  44 +# CONFIG_CMD_FLASH is not set
  45 +CONFIG_CMD_GPIO=y
  46 +CONFIG_CMD_I2C=y
  47 +CONFIG_CMD_PART=y
  48 +CONFIG_CMD_READ=y
  49 +CONFIG_CMD_SATA=y
  50 +CONFIG_CMD_SPI=y
  51 +CONFIG_CMD_USB=y
  52 +# CONFIG_CMD_SETEXPR is not set
  53 +CONFIG_CMD_TIME=y
  54 +CONFIG_CMD_SOUND=y
  55 +CONFIG_CMD_BOOTSTAGE=y
  56 +CONFIG_CMD_TPM=y
  57 +CONFIG_CMD_TPM_TEST=y
  58 +CONFIG_CMD_EXT2=y
  59 +CONFIG_CMD_EXT4=y
  60 +CONFIG_CMD_EXT4_WRITE=y
  61 +CONFIG_CMD_FAT=y
  62 +CONFIG_CMD_FS_GENERIC=y
  63 +CONFIG_MAC_PARTITION=y
  64 +# CONFIG_SPL_MAC_PARTITION is not set
  65 +# CONFIG_SPL_DOS_PARTITION is not set
  66 +CONFIG_ISO_PARTITION=y
  67 +CONFIG_EFI_PARTITION=y
  68 +# CONFIG_SPL_EFI_PARTITION is not set
  69 +CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
  70 +# CONFIG_NET is not set
  71 +CONFIG_REGMAP=y
  72 +CONFIG_SYSCON=y
  73 +CONFIG_SPL_OF_TRANSLATE=y
  74 +CONFIG_CPU=y
  75 +CONFIG_DM_I2C=y
  76 +CONFIG_SYS_I2C_DW=y
  77 +CONFIG_TPL_MISC=y
  78 +CONFIG_CROS_EC=y
  79 +CONFIG_CROS_EC_LPC=y
  80 +CONFIG_SPI_FLASH_WINBOND=y
  81 +# CONFIG_X86_PCH7 is not set
  82 +# CONFIG_X86_PCH9 is not set
  83 +CONFIG_PINCTRL=y
  84 +# CONFIG_SPL_PINCTRL_FULL is not set
  85 +CONFIG_DEBUG_UART_SHIFT=2
  86 +CONFIG_SYS_NS16550=y
  87 +CONFIG_SOUND=y
  88 +CONFIG_SOUND_I8254=y
  89 +CONFIG_SOUND_RT5677=y
  90 +CONFIG_SPI=y
  91 +CONFIG_ICH_SPI=y
  92 +CONFIG_TPL_SYSRESET=y
  93 +CONFIG_TPM_TIS_LPC=y
  94 +CONFIG_USB_XHCI_HCD=y
  95 +CONFIG_USB_STORAGE=y
  96 +CONFIG_USB_KEYBOARD=y
  97 +CONFIG_SPL_FS_CBFS=y
  98 +# CONFIG_SPL_USE_TINY_PRINTF is not set
  99 +CONFIG_TPL_USE_TINY_PRINTF=y
  100 +CONFIG_CMD_DHRYSTONE=y
  101 +CONFIG_TPM=y
  102 +# CONFIG_EFI_LOADER is not set
doc/board/google/chromebook_coral.rst
Diff comments   View file @ a1d6dc3
  1 +.. SPDX-License-Identifier: GPL-2.0+
  2 +.. sectionauthor:: Simon Glass <sjg@chromium.org>
  3 +
  4 +Chromebook Coral
  5 +================
  6 +
  7 +Coral is a Chromebook (or really about 20 different Chromebooks) which use the
  8 +Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so
  9 +should also work. Some later ones based on Glacier Lake (GLK) need various
  10 +changes in GPIOs, etc. but are very similar.
  11 +
  12 +It is hoped that this port can enable ports to embedded APL boards which are
  13 +starting to appear.
  14 +
  15 +Note that booting U-Boot on APL is already supported by coreboot and
  16 +Slim Bootloader. This documentation refers to a 'bare metal' port.
  17 +
  18 +
  19 +Boot flow - TPL
  20 +---------------
  21 +
  22 +Apollo Lake boots via an IFWI (Integrated Firmware Image). TPL is placed in
  23 +this, in the IBBL entry.
  24 +
  25 +On boot, an on-chip microcontroller called the CSE (Converged Security Engine)
  26 +sets up some SDRAM at ffff8000 and loads the TPL image to that address. The
  27 +SRAM extends up to the top of 32-bit address space, but the last 2KB is the
  28 +start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE
  29 +must be ffff8000. Actually the start16 region is small and it could probably
  30 +move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so
  31 +there is no need to change it at present. The size limit is enforced by
  32 +CONFIG_TPL_SIZE_LIMIT to avoid producing images that won't boot.
  33 +
  34 +TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides
  35 +larger area of RAM for use while booting. CAR is mapped at CONFIG_SYS_CAR_ADDR
  36 +(fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB
  37 +of this space (i.e. below fef10000). This means that the stack and early
  38 +malloc() region in TPL can be 64KB at most.
  39 +
  40 +TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the
  41 +x86-specific functions pci_x86_write_config(), etc. SPL creates a simple-bus
  42 +device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl()
  43 +is called to early init on various devices. This includes placing PCI devices
  44 +at hard-coded addresses in the memory map. PCI auto-config is not used.
  45 +
  46 +Most of the 16KB ROM is mapped into the very top of memory, except for the
  47 +Intel descriptor (first 4KB) and the space for SRAM as above.
  48 +
  49 +TPL does not set up a bloblist since at present it does not have anything to
  50 +pass to SPL.
  51 +
  52 +Once TPL is done it loads SPL from ROM using either the memory-mapped SPI or by
  53 +using the Intel fast SPI driver. SPL is loaded into CAR, at the address given
  54 +by CONFIG_SPL_TEXT_BASE, which is normally fef10000.
  55 +
  56 +Note that booting using the SPI driver results in an TPL image that is about
  57 +26KB in size instead of 19KB. Also boot speed is worse by about 340ms. If you
  58 +really want to use the driver, enable CONFIG_APL_SPI_FLASH_BOOT and set
  59 +BOOT_FROM_FAST_SPI_FLASH to true[2].
  60 +
  61 +
  62 +Boot flow - SPL
  63 +---------------
  64 +
  65 +SPL (running from start_from_tpl.S) continues to use the same stack as TPL.
  66 +It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads
  67 +the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the
  68 +output 'HOB' list (Hand-off-block) is stored into gd->arch.hob_list for parsing.
  69 +There is a 2GB chunk of SDRAM starting at 0 and the rest is at 4GB.
  70 +
  71 +PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so
  72 +proper PCI access is available and normal dm_pci_read_config() calls can be
  73 +used. However PCI auto-config is not used so the same static memory mapping set
  74 +up by TPL is still active.
  75 +
  76 +SPL on x86 always runs with CONFIG_SPL_SEPARATE_BSS=y and BSS is at 120000
  77 +(see u-boot-spl.lds). This works because SPL doesn't access BSS until after
  78 +board_init_r(), as per the rules, and DRAM is available then.
  79 +
  80 +SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper.
  81 +This includes a pointer to the HOB list as well as DRAM information. See
  82 +struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR,
  83 +normally 100000.
  84 +
  85 +SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent
  86 +boots. Be warned that SPL can take 30 seconds without this cache! This is a
  87 +known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
  88 +The MRC caches are used to work around this.
  89 +
  90 +Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
  91 +is normally 1110000. Note that CAR is still active.
  92 +
  93 +
  94 +Boot flow - U-Boot pre-relocation
  95 +---------------------------------
  96 +
  97 +U-Boot (running from start_from_spl.S) starts running in RAM and uses the same
  98 +stack as SPL. It does various init activities before relocation. Notably
  99 +arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table
  100 +in the device tree.
  101 +
  102 +PCI auto-config is not used before relocation, but CONFIG_PCI of course is
  103 +defined, so proper PCI access is available. The same static memory mapping set
  104 +up by TPL is still active until relocation.
  105 +
  106 +As per usual, U-Boot allocates memory at the top of available RAM (a bit below
  107 +2GB in this case) and copies things there ready to relocate itself. Notably
  108 +reserve_arch() does not reserve space for the HOB list returned by FSP-M since
  109 +this is already located in RAM.
  110 +
  111 +U-Boot then shuts down CAR and jumps to its relocated version.
  112 +
  113 +
  114 +Boot flow - U-Boot post-relocation
  115 +---------------------------------
  116 +
  117 +U-Boot starts up normally, running near the top of RAM. After driver model is
  118 +running, arch_fsp_init_r() is called which loads and runs the FSP-S binary.
  119 +This updates the HOB list to include graphics information, used by the fsp_video
  120 +driver.
  121 +
  122 +PCI autoconfig is done and a few devices are probed to complete init. Most
  123 +others are started only when they are used.
  124 +
  125 +Note that FSP-S is supposed to run after CAR has been shut down, which happens
  126 +immediately before U-Boot starts up in its relocated position. Therefore we
  127 +cannot run FSP-S before relocation. On the other hand we must run it before
  128 +PCI auto-config is done, since FSP-S may show or hide devices. The first device
  129 +that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S
  130 +must run before that. A corollary is that loading FSP-S must be done without
  131 +using the SPI driver, to avoid probing PCI and causing an autoconfig, so
  132 +memory-mapped reading is always used for FSP-S.
  133 +
  134 +It would be possible to tear down CAR in SPL instead of U-Boot. The SPL handoff
  135 +information could make sure it does not include any pointers into CAR (in fact
  136 +it doesn't). But tearing down CAR in U-Boot allows the initial state used by TPL
  137 +and SPL to be read by U-Boot, which seems useful. It also matches how older
  138 +platforms start up (those that don't use SPL).
  139 +
  140 +
  141 +Performance
  142 +-----------
  143 +
  144 +Bootstage is used through all phases of U-Boot to keep accurate timimgs for
  145 +boot. Use 'bootstage report' in U-Boot to see the report, e.g.:
  146 +
  147 +Timer summary in microseconds (16 records):
  148 + Mark Elapsed Stage
  149 + 0 0 reset
  150 + 155,325 155,325 TPL
  151 + 204,014 48,689 end TPL
  152 + 204,385 371 SPL
  153 + 738,633 534,248 end SPL
  154 + 739,161 528 board_init_f
  155 + 842,764 103,603 board_init_r
  156 + 1,166,233 323,469 main_loop
  157 + 1,166,283 50 id=175
  158 +
  159 +Accumulated time:
  160 + 62 fast_spi
  161 + 202 dm_r
  162 + 7,779 dm_spl
  163 + 15,555 dm_f
  164 + 208,357 fsp-m
  165 + 239,847 fsp-s
  166 + 292,143 mmap_spi
  167 +
  168 +CPU performance is about 3500 DMIPS:
  169 +
  170 +=> dhry
  171 +1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS
  172 +
  173 +
  174 +Partial memory map
  175 +------------------
  176 +
  177 +ffffffff Top of ROM (and last byte of 32-bit address space)
  178 +ffff8000 TPL loaded here (from IFWI)
  179 +ff000000 Bottom of ROM
  180 +fefc000 Top of CAR region
  181 +fef96000 Stack for FSP-M
  182 +fef40000 59000 FSP-M
  183 +fef11000 SPL loaded here
  184 +fef10000 CONFIG_BLOBLIST_ADDR
  185 +fef10000 Stack top in TPL, SPL and U-Boot before relocation
  186 +fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR
  187 +fef00000 Base of CAR region
  188 +
  189 + f0000 CONFIG_ROM_TABLE_ADDR
  190 + 120000 BSS (defined in u-boot-spl.lds)
  191 + 200000 FSP-S (which is run after U-Boot is relocated)
  192 + 1110000 CONFIG_SYS_TEXT_BASE
  193 +
  194 +
  195 +Supported peripherals
  196 +---------------------
  197 +
  198 +- UART
  199 +- SPI flash
  200 +- Video
  201 +- MMC (dev 0) and micro-SD (dev 1)
  202 +- Chrome OS EC
  203 +- Keyboard
  204 +- USB
  205 +
  206 +
  207 +To do
  208 +-----
  209 +
  210 +- Finish peripherals
  211 + - left-side USB
  212 + - USB-C
  213 + - Cr50 (security chip: a basic driver is running but not included here)
  214 + - I2C (driver exists but not enabled in device tree)
  215 + - Sound (Intel I2S support exists, but need da7219 driver)
  216 + - RTC (driver exists but not enabled in device tree)
  217 + - Various minor features supported by LPC, etc.
  218 +- Booting Chrome OS, e.g. with verified boot
  219 +- Integrate with Chrome OS vboot
  220 +- Improvements to booting from coreboot (i.e. as a coreboot target)
  221 +- Use FSP-T binary instead of our own CAR implementation
  222 +- Use the official FSP package instead of the coreboot one
  223 +- Enable all CPU cores
  224 +- Suspend / resume
  225 +- ACPI
  226 +
  227 +
  228 +Credits
  229 +-------
  230 +
  231 +This is a spare-time project conducted slowly over a long period of time.
  232 +
  233 +Much of the code for this port came from Coreboot, an open-source firmware
  234 +project similar to U-Boot's SPL in terms of features.
  235 +
  236 +Also see [2] for information about the boot flow used by coreboot. It is
  237 +similar, but has an extra postcar stage. U-Boot doesn't need this since it
  238 +supports relocating itself in memory.
  239 +
  240 +
  241 +[2] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf
doc/board/google/index.rst
Diff comments   View file @ a1d6dc3
... ... @@ -6,6 +6,7 @@
6 6 .. toctree::
7 7 :maxdepth: 2
8 8  
  9 + chromebook_coral
9 10 chromebook_link
10 11 chromebook_samus
include/configs/chromebook_coral.h
Diff comments   View file @ a1d6dc3
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 Google LLC
  4 + */
  5 +
  6 +/*
  7 + * board/config.h - configuration options, board-specific
  8 + */
  9 +
  10 +#ifndef __CONFIG_H
  11 +#define __CONFIG_H
  12 +
  13 +#define CONFIG_BOOTCOMMAND \
  14 + "fatload mmc 1:c 1000000 syslinux/vmlinuz.A; zboot 1000000"
  15 +
  16 +#include <configs/x86-common.h>
  17 +#include <configs/x86-chromebook.h>
  18 +
  19 +#undef CONFIG_STD_DEVICES_SETTINGS
  20 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
  21 + "stdout=vidconsole,serial\0" \
  22 + "stderr=vidconsole,serial\0"
  23 +
  24 +#define CONFIG_ENV_SECT_SIZE 0x1000
  25 +#define CONFIG_ENV_OFFSET 0x003f8000
  26 +
  27 +#define CONFIG_TPL_TEXT_BASE 0xffff8000
  28 +
  29 +#define CONFIG_SYS_NS16550_MEM32
  30 +#undef CONFIG_SYS_NS16550_PORT_MAPPED
  31 +
  32 +#endif /* __CONFIG_H */