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Commit a2277cc30cdb40298aca80344f3764db6a0cfb8d

Authored by Wills Wang
Committed by Daniel Schwierzeck
1 parent 6a7b52bc8d
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mips: ath79: add AP143 reference board 

This patch add board-level code and base DT for AP143.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Showing 10 changed files with 359 additions and 0 deletions Side-by-side Diff

arch/mips/dts/Makefile
Diff comments   View file @ a2277cc
... ... @@ -3,6 +3,7 @@
3 3 #
4 4  
5 5 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
  6 +dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
6 7 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
7 8  
8 9 targets += $(dtb-y)
arch/mips/dts/ap143.dts
Diff comments   View file @ a2277cc
  1 +/*
  2 + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/dts-v1/;
  8 +#include "qca953x.dtsi"
  9 +
  10 +/ {
  11 + model = "AP143 Reference Board";
  12 + compatible = "qca,ap143", "qca,qca953x";
  13 +
  14 + aliases {
  15 + spi0 = &spi0;
  16 + serial0 = &uart0;
  17 + };
  18 +
  19 + chosen {
  20 + stdout-path = "serial0:115200n8";
  21 + };
  22 +};
  23 +
  24 +&xtal {
  25 + clock-frequency = <25000000>;
  26 +};
  27 +
  28 +&uart0 {
  29 + status = "okay";
  30 +};
  31 +
  32 +&spi0 {
  33 + spi-max-frequency = <25000000>;
  34 + status = "okay";
  35 + spi-flash@0 {
  36 + #address-cells = <1>;
  37 + #size-cells = <1>;
  38 + compatible = "spi-flash";
  39 + memory-map = <0x9f000000 0x00800000>;
  40 + spi-max-frequency = <25000000>;
  41 + reg = <0>;
  42 + };
  43 +};
arch/mips/dts/qca953x.dtsi
Diff comments   View file @ a2277cc
  1 +/*
  2 + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <dt-bindings/interrupt-controller/irq.h>
  8 +#include "skeleton.dtsi"
  9 +
  10 +/ {
  11 + compatible = "qca,qca953x";
  12 +
  13 + #address-cells = <1>;
  14 + #size-cells = <1>;
  15 +
  16 + cpus {
  17 + #address-cells = <1>;
  18 + #size-cells = <0>;
  19 +
  20 + cpu@0 {
  21 + device_type = "cpu";
  22 + compatible = "mips,mips24Kc";
  23 + reg = <0>;
  24 + };
  25 + };
  26 +
  27 + clocks {
  28 + #address-cells = <1>;
  29 + #size-cells = <1>;
  30 + ranges;
  31 +
  32 + xtal: xtal {
  33 + #clock-cells = <0>;
  34 + compatible = "fixed-clock";
  35 + clock-output-names = "xtal";
  36 + };
  37 + };
  38 +
  39 + pinctrl {
  40 + u-boot,dm-pre-reloc;
  41 + compatible = "qca,qca953x-pinctrl";
  42 + ranges;
  43 + #address-cells = <1>;
  44 + #size-cells = <1>;
  45 + reg = <0x18040000 0x100>;
  46 + };
  47 +
  48 + ahb {
  49 + compatible = "simple-bus";
  50 + ranges;
  51 +
  52 + #address-cells = <1>;
  53 + #size-cells = <1>;
  54 +
  55 + apb {
  56 + compatible = "simple-bus";
  57 + ranges;
  58 +
  59 + #address-cells = <1>;
  60 + #size-cells = <1>;
  61 +
  62 + uart0: uart@18020000 {
  63 + compatible = "ns16550";
  64 + reg = <0x18020000 0x20>;
  65 + reg-shift = <2>;
  66 + clock-frequency = <25000000>;
  67 + interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
  68 +
  69 + status = "disabled";
  70 + };
  71 + };
  72 +
  73 + spi0: spi@1f000000 {
  74 + compatible = "qca,ar7100-spi";
  75 + reg = <0x1f000000 0x10>;
  76 + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
  77 +
  78 + status = "disabled";
  79 +
  80 + #address-cells = <1>;
  81 + #size-cells = <0>;
  82 + };
  83 + };
  84 +};
arch/mips/mach-ath79/Kconfig
Diff comments   View file @ a2277cc
... ... @@ -29,9 +29,14 @@
29 29 bool "AP121 Reference Board"
30 30 select SOC_AR933X
31 31  
  32 +config TARGET_AP143
  33 + bool "AP143 Reference Board"
  34 + select SOC_QCA953X
  35 +
32 36 endchoice
33 37  
34 38 source "board/qca/ap121/Kconfig"
  39 +source "board/qca/ap143/Kconfig"
35 40  
36 41 endmenu
board/qca/ap143/Kconfig
Diff comments   View file @ a2277cc
  1 +if TARGET_AP143
  2 +
  3 +config SYS_VENDOR
  4 + default "qca"
  5 +
  6 +config SYS_BOARD
  7 + default "ap143"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "ap143"
  11 +
  12 +endif
board/qca/ap143/MAINTAINERS
Diff comments   View file @ a2277cc
  1 +AP143 BOARD
  2 +M: Wills Wang <wills.wang@live.com>
  3 +S: Maintained
  4 +F: board/qca/ap143/
  5 +F: include/configs/ap143.h
  6 +F: configs/ap143_defconfig
board/qca/ap143/Makefile
Diff comments   View file @ a2277cc
  1 +#
  2 +# SPDX-License-Identifier: GPL-2.0+
  3 +#
  4 +
  5 +obj-y = ap143.o
board/qca/ap143/ap143.c
Diff comments   View file @ a2277cc
  1 +/*
  2 + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <asm/addrspace.h>
  10 +#include <asm/types.h>
  11 +#include <mach/ar71xx_regs.h>
  12 +#include <mach/ddr.h>
  13 +#include <debug_uart.h>
  14 +
  15 +DECLARE_GLOBAL_DATA_PTR;
  16 +
  17 +#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  18 +void board_debug_uart_init(void)
  19 +{
  20 + void __iomem *regs;
  21 + u32 val;
  22 +
  23 + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
  24 + MAP_NOCACHE);
  25 +
  26 + /*
  27 + * GPIO9 as input, GPIO10 as output
  28 + */
  29 + val = readl(regs + AR71XX_GPIO_REG_OE);
  30 + val |= QCA953X_GPIO(9);
  31 + val &= ~QCA953X_GPIO(10);
  32 + writel(val, regs + AR71XX_GPIO_REG_OE);
  33 +
  34 + /*
  35 + * Enable GPIO10 as UART0_SOUT
  36 + */
  37 + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
  38 + val &= ~QCA953X_GPIO_MUX_MASK(16);
  39 + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
  40 + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
  41 +
  42 + /*
  43 + * Enable GPIO9 as UART0_SIN
  44 + */
  45 + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
  46 + val &= ~QCA953X_GPIO_MUX_MASK(8);
  47 + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
  48 + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
  49 +
  50 + /*
  51 + * Enable GPIO10 output
  52 + */
  53 + val = readl(regs + AR71XX_GPIO_REG_OUT);
  54 + val |= QCA953X_GPIO(10);
  55 + writel(val, regs + AR71XX_GPIO_REG_OUT);
  56 +}
  57 +#endif
  58 +
  59 +int board_early_init_f(void)
  60 +{
  61 +#ifdef CONFIG_DEBUG_UART
  62 + debug_uart_init();
  63 +#endif
  64 + ddr_init();
  65 + return 0;
  66 +}
configs/ap143_defconfig
Diff comments   View file @ a2277cc
  1 +CONFIG_MIPS=y
  2 +CONFIG_SYS_MALLOC_F_LEN=0x800
  3 +CONFIG_DM_SERIAL=y
  4 +CONFIG_DM_SPI=y
  5 +CONFIG_DM_SPI_FLASH=y
  6 +CONFIG_ARCH_ATH79=y
  7 +CONFIG_TARGET_AP143=y
  8 +CONFIG_DEFAULT_DEVICE_TREE="ap143"
  9 +CONFIG_SYS_PROMPT="ap143 # "
  10 +# CONFIG_CMD_BDI is not set
  11 +# CONFIG_CMD_CONSOLE is not set
  12 +# CONFIG_CMD_ELF is not set
  13 +# CONFIG_CMD_IMLS is not set
  14 +# CONFIG_CMD_XIMG is not set
  15 +# CONFIG_CMD_EXPORTENV is not set
  16 +# CONFIG_CMD_IMPORTENV is not set
  17 +# CONFIG_CMD_EDITENV is not set
  18 +# CONFIG_CMD_CRC32 is not set
  19 +# CONFIG_CMD_FLASH is not set
  20 +CONFIG_CMD_SF=y
  21 +CONFIG_CMD_SPI=y
  22 +# CONFIG_CMD_FPGA is not set
  23 +# CONFIG_CMD_NET is not set
  24 +# CONFIG_CMD_NFS is not set
  25 +CONFIG_SPI_FLASH=y
  26 +CONFIG_SPI_FLASH_BAR=y
  27 +CONFIG_SPI_FLASH_ATMEL=y
  28 +CONFIG_SPI_FLASH_EON=y
  29 +CONFIG_SPI_FLASH_GIGADEVICE=y
  30 +CONFIG_SPI_FLASH_MACRONIX=y
  31 +CONFIG_SPI_FLASH_SPANSION=y
  32 +CONFIG_SPI_FLASH_STMICRO=y
  33 +CONFIG_SPI_FLASH_SST=y
  34 +CONFIG_SPI_FLASH_WINBOND=y
  35 +CONFIG_SPI_FLASH_DATAFLASH=y
  36 +CONFIG_SPI_FLASH_MTD=y
  37 +CONFIG_PINCTRL=y
  38 +CONFIG_QCA953X_PINCTRL=y
  39 +CONFIG_DEBUG_UART=y
  40 +CONFIG_DEBUG_UART_BASE=0xb8020000
  41 +CONFIG_DEBUG_UART_CLOCK=25000000
  42 +CONFIG_DEBUG_UART_SHIFT=2
  43 +CONFIG_DEBUG_UART_BOARD_INIT=y
  44 +CONFIG_SYS_NS16550=y
  45 +CONFIG_ATH79_SPI=y
  46 +CONFIG_USE_PRIVATE_LIBGCC=y
  47 +CONFIG_OF_LIBFDT=y
include/configs/ap143.h
Diff comments   View file @ a2277cc
  1 +/*
  2 + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CONFIG_H
  8 +#define __CONFIG_H
  9 +
  10 +#define CONFIG_SYS_TEXT_BASE 0x9f000000
  11 +
  12 +#define CONFIG_DISPLAY_CPUINFO
  13 +#define CONFIG_DISPLAY_BOARDINFO
  14 +#define CONFIG_BOARD_EARLY_INIT_F
  15 +
  16 +#define CONFIG_SYS_HZ 1000
  17 +#define CONFIG_SYS_MHZ 325
  18 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
  19 +
  20 +/* Cache Configuration */
  21 +#define CONFIG_SYS_DCACHE_SIZE 0x8000
  22 +#define CONFIG_SYS_ICACHE_SIZE 0x10000
  23 +#define CONFIG_SYS_CACHELINE_SIZE 32
  24 +
  25 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  26 +
  27 +#define CONFIG_SYS_MALLOC_LEN 0x40000
  28 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
  29 +
  30 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
  31 +#define CONFIG_SYS_LOAD_ADDR 0x81000000
  32 +
  33 +#define CONFIG_SYS_NO_FLASH
  34 +
  35 +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
  36 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
  37 +#define CONFIG_SYS_INIT_SP_ADDR \
  38 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
  39 +
  40 +/*
  41 + * Serial Port
  42 + */
  43 +#define CONFIG_SYS_NS16550_CLK 25000000
  44 +#define CONFIG_BAUDRATE 115200
  45 +#define CONFIG_SYS_BAUDRATE_TABLE \
  46 + {9600, 19200, 38400, 57600, 115200}
  47 +
  48 +#define CONFIG_BOOTDELAY 3
  49 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  50 + "root=/dev/mtdblock2 " \
  51 + "rootfstype=squashfs"
  52 +#define CONFIG_BOOTCOMMAND "sf probe;" \
  53 + "mtdparts default;" \
  54 + "bootm 0x9f300000"
  55 +#define CONFIG_LZMA
  56 +
  57 +#define MTDIDS_DEFAULT "nor0=spi-flash.0"
  58 +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
  59 + "256k(u-boot),64k(u-boot-env)," \
  60 + "2752k(rootfs),896k(uImage)," \
  61 + "64k(NVRAM),64k(ART)"
  62 +
  63 +#define CONFIG_ENV_SPI_MAX_HZ 25000000
  64 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  65 +#define CONFIG_ENV_OFFSET 0x40000
  66 +#define CONFIG_ENV_SECT_SIZE 0x10000
  67 +#define CONFIG_ENV_SIZE 0x10000
  68 +
  69 +/*
  70 + * Command
  71 + */
  72 +#define CONFIG_CMD_MTDPARTS
  73 +
  74 +/* Miscellaneous configurable options */
  75 +#define CONFIG_SYS_CBSIZE 256
  76 +#define CONFIG_SYS_MAXARGS 16
  77 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  78 + sizeof(CONFIG_SYS_PROMPT) + 16)
  79 +#define CONFIG_SYS_LONGHELP
  80 +#define CONFIG_CMDLINE_EDITING
  81 +#define CONFIG_AUTO_COMPLETE
  82 +
  83 +/*
  84 + * Diagnostics
  85 + */
  86 +#define CONFIG_SYS_MEMTEST_START 0x80100000
  87 +#define CONFIG_SYS_MEMTEST_END 0x83f00000
  88 +#define CONFIG_CMD_MEMTEST
  89 +
  90 +#endif /* __CONFIG_H */