samsung: usb: phy: Support for DWC3 PHY

New files, namely samsung_usb_phy.c and samsung-usb-phy-uboot.h have been added to u-boot to provide proper PHY handling at Exynos5 SoCs. This code is used thereafter in the board_usb_init() call. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>

samsung: usb: phy: Support for DWC3 PHY
New files, namely samsung_usb_phy.c and samsung-usb-phy-uboot.h have been added to u-boot to provide proper PHY handling at Exynos5 SoCs. This code is used thereafter in the board_usb_init() call. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
Lukasz Majewski
1 parent 4e633e465b
Showing 3 changed files with 95 additions and 0 deletions Side-by-side Diff
drivers/usb/dwc3/Makefile
drivers/usb/dwc3/samsung_usb_phy.c
include/samsung-usb-phy-uboot.h
@@ -6,4 +6,5 @@
  
 obj-$(CONFIG_USB_DWC3_OMAP)		+= dwc3-omap.o
 obj-$(CONFIG_USB_DWC3_PHY_OMAP)		+= ti_usb_phy.o
+obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG)	+= samsung_usb_phy.o
+/**
+ * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ *
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/power.h>
+#include <asm/arch/xhci-exynos.h>
+
+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
+{
+	u32 reg;
+
+	/* Reset USB 3.0 PHY */
+	writel(0x0, &phy->phy_reg0);
+
+	clrbits_le32(&phy->phy_param0,
+			/* Select PHY CLK source */
+			PHYPARAM0_REF_USE_PAD |
+			/* Set Loss-of-Signal Detector sensitivity */
+			PHYPARAM0_REF_LOSLEVEL_MASK);
+	setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
+
+
+	writel(0x0, &phy->phy_resume);
+
+	/*
+	 * Setting the Frame length Adj value[6:1] to default 0x20
+	 * See xHCI 1.0 spec, 5.2.4
+	 */
+	setbits_le32(&phy->link_system,
+			LINKSYSTEM_XHCI_VERSION_CONTROL |
+			LINKSYSTEM_FLADJ(0x20));
+
+	/* Set Tx De-Emphasis level */
+	clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
+	setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
+
+	setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
+
+	/* PHYTEST POWERDOWN Control */
+	clrbits_le32(&phy->phy_test,
+			PHYTEST_POWERDOWN_SSP |
+			PHYTEST_POWERDOWN_HSP);
+
+	/* UTMI Power Control */
+	writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
+
+		/* Use core clock from main PLL */
+	reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+		/* Default 24Mhz crystal clock */
+		PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
+		PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+		PHYCLKRST_SSC_REFCLKSEL(0) |
+		/* Force PortReset of PHY */
+		PHYCLKRST_PORTRESET |
+		/* Digital power supply in normal operating mode */
+		PHYCLKRST_RETENABLEN |
+		/* Enable ref clock for SS function */
+		PHYCLKRST_REF_SSP_EN |
+		/* Enable spread spectrum */
+		PHYCLKRST_SSC_EN |
+		/* Power down HS Bias and PLL blocks in suspend mode */
+		PHYCLKRST_COMMONONN;
+
+	writel(reg, &phy->phy_clk_rst);
+
+	/* giving time to Phy clock to settle before resetting */
+	udelay(10);
+
+	reg &= ~PHYCLKRST_PORTRESET;
+	writel(reg, &phy->phy_clk_rst);
+}
+/* include/samsung-usb-phy-uboot.h
+ *
+ * Copyright (c) 2015 Samsung Electronics
+ *
+ * USB3 (DWC3) PHY uboot init
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __SAMSUNG_USB_PHY_UBOOT_H_
+#define __SAMSUNG_USB_PHY_UBOOT_H_
+
+#include <asm/arch/xhci-exynos.h>
+
+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy);
+#endif /* __SAMSUNG_USB_PHY_UBOOT_H_ */
...	...	@@ -6,4 +6,5 @@
6	6
7	7	obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
8	8	obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
	9	+obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
	1	+/**
	2	+ * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
	3	+ *
	4	+ * Copyright (C) 2015 Samsung Electronics
	5	+ *
	6	+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
	7	+ *
	8	+ * SPDX-License-Identifier: GPL-2.0
	9	+ */
	10	+
	11	+#include <common.h>
	12	+#include <asm/arch/power.h>
	13	+#include <asm/arch/xhci-exynos.h>
	14	+
	15	+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
	16	+{
	17	+ u32 reg;
	18	+
	19	+ /* Reset USB 3.0 PHY */
	20	+ writel(0x0, &phy->phy_reg0);
	21	+
	22	+ clrbits_le32(&phy->phy_param0,
	23	+ /* Select PHY CLK source */
	24	+ PHYPARAM0_REF_USE_PAD \|
	25	+ /* Set Loss-of-Signal Detector sensitivity */
	26	+ PHYPARAM0_REF_LOSLEVEL_MASK);
	27	+ setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
	28	+
	29	+
	30	+ writel(0x0, &phy->phy_resume);
	31	+
	32	+ /*
	33	+ * Setting the Frame length Adj value[6:1] to default 0x20
	34	+ * See xHCI 1.0 spec, 5.2.4
	35	+ */
	36	+ setbits_le32(&phy->link_system,
	37	+ LINKSYSTEM_XHCI_VERSION_CONTROL \|
	38	+ LINKSYSTEM_FLADJ(0x20));
	39	+
	40	+ /* Set Tx De-Emphasis level */
	41	+ clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
	42	+ setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
	43	+
	44	+ setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
	45	+
	46	+ /* PHYTEST POWERDOWN Control */
	47	+ clrbits_le32(&phy->phy_test,
	48	+ PHYTEST_POWERDOWN_SSP \|
	49	+ PHYTEST_POWERDOWN_HSP);
	50	+
	51	+ /* UTMI Power Control */
	52	+ writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
	53	+
	54	+ /* Use core clock from main PLL */
	55	+ reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK \|
	56	+ /* Default 24Mhz crystal clock */
	57	+ PHYCLKRST_FSEL(FSEL_CLKSEL_24M) \|
	58	+ PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF \|
	59	+ PHYCLKRST_SSC_REFCLKSEL(0) \|
	60	+ /* Force PortReset of PHY */
	61	+ PHYCLKRST_PORTRESET \|
	62	+ /* Digital power supply in normal operating mode */
	63	+ PHYCLKRST_RETENABLEN \|
	64	+ /* Enable ref clock for SS function */
	65	+ PHYCLKRST_REF_SSP_EN \|
	66	+ /* Enable spread spectrum */
	67	+ PHYCLKRST_SSC_EN \|
	68	+ /* Power down HS Bias and PLL blocks in suspend mode */
	69	+ PHYCLKRST_COMMONONN;
	70	+
	71	+ writel(reg, &phy->phy_clk_rst);
	72	+
	73	+ /* giving time to Phy clock to settle before resetting */
	74	+ udelay(10);
	75	+
	76	+ reg &= ~PHYCLKRST_PORTRESET;
	77	+ writel(reg, &phy->phy_clk_rst);
	78	+}
	1	+/* include/samsung-usb-phy-uboot.h
	2	+ *
	3	+ * Copyright (c) 2015 Samsung Electronics
	4	+ *
	5	+ * USB3 (DWC3) PHY uboot init
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef __SAMSUNG_USB_PHY_UBOOT_H_
	11	+#define __SAMSUNG_USB_PHY_UBOOT_H_
	12	+
	13	+#include <asm/arch/xhci-exynos.h>
	14	+
	15	+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy);
	16	+#endif /* __SAMSUNG_USB_PHY_UBOOT_H_ */