p1022ds: add audclk hwconfig setting to enable codec reference clock

The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference clock for the audio codec, but by default both are disabled. Add a 'audclk' hwconfig option that allows the user to choose which clock he wants. The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48, 64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and 88200Hz. Also configure a pin muxing to select some SSI signals, which will disable I2C1. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

p1022ds: add audclk hwconfig setting to enable codec reference clock
The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference clock for the audio codec, but by default both are disabled. Add a 'audclk' hwconfig option that allows the user to choose which clock he wants. The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48, 64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and 88200Hz. Also configure a pin muxing to select some SSI signals, which will disable I2C1. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi · Kumar Gala
1 parent b6bde93090
Showing 3 changed files with 80 additions and 9 deletions Side-by-side Diff
board/freescale/p1022ds/p1022ds.c
doc/README.fsl-hwconfig
include/configs/P1022DS.h
@@ -27,6 +27,7 @@
 #include <asm/mp.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <hwconfig.h>
  
 #include "../common/ngpixis.h"
  
  
  
  
  
  
  
  
@@ -90,34 +91,58 @@
  
 #define CONFIG_TFP410_I2C_ADDR	0x38
  
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK	0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK	0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI	0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12		0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11		0x01
+
 int misc_init_r(void)
 {
 	u8 temp;
+	const char *audclk;
+	size_t arglen;
  
-	/*  Enable the TFP410 Encoder */
+	/* For DVI, enable the TFP410 Encoder. */
  
 	temp = 0xBF;
 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
-	/* Verify if enabled */
-	temp = 0;
 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
 	debug("DVI Encoder Read: 0x%02x\n", temp);
  
 	temp = 0x10;
 	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
-	/* Verify if enabled */
-	temp = 0;
 	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
 		return -1;
-
 	debug("DVI Encoder Read: 0x%02x\n",temp);
  
+	/*
+	 * Enable the reference clock for the WM8776 codec, and route the MUX
+	 * pins for SSI. The default is the 12.288 MHz clock
+	 */
+
+	temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+		CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+	temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	/* Check the first two chars only */
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+	else
+		temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+	out_8(&pixis->brdcfg1, temp);
+
 	return 0;
 }
  
@@ -310,6 +335,27 @@
 }
  
 #ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+	const char *audclk;
+	size_t arglen;
+	u32 freq;
+
+	audclk = hwconfig_arg("audclk", &arglen);
+	if (audclk && (strncmp(audclk, "11", 2) == 0))
+		freq = 11289600;
+	else
+		freq = 12288000;
+
+	do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
@@ -327,6 +373,9 @@
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
 #endif
+
+	/* Update the WM8776 node's clock frequency property */
+	ft_codec_setup(blob, "wlf,wm8776");
 }
 #endif
  
+Freescale-specific 'hwconfig' options.
+
+This file documents Freescale-specific key:value pairs for the 'hwconfig'
+option.  See README.hwconfig for general information about 'hwconfig'.
+
+audclk
+	Specific to the P1022DS reference board.
+
+	This option specifies which of the two oscillator frequencies should be
+	routed to the Wolfson WM8776 codec.  The ngPIXIS can be programmed to
+	route either a 11.2896MHz or a 12.288MHz clock.  The default is
+	12.288MHz.  This option has two effects.  First, the MUX on the board
+	will be programmed accordingly.  Second, the clock-frequency property
+	in the codec node in the device tree will be updated to the correct
+	value.
+
+	'audclk:11'
+		Select the 11.2896MHz clock
+
+	'audclk:12'
+		Select the 12.288MHz clock
@@ -134,6 +134,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
  
 #define CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
...	...	@@ -27,6 +27,7 @@
27	27	#include <asm/mp.h>
28	28	#include <netdev.h>
29	29	#include <i2c.h>
	30	+#include <hwconfig.h>
30	31
31	32	#include "../common/ngpixis.h"
32	33
33	34
34	35
35	36
36	37
37	38
38	39
39	40
...	...	@@ -90,34 +91,58 @@
90	91
91	92	#define CONFIG_TFP410_I2C_ADDR 0x38
92	93
	94	+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
	95	+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
	96	+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
	97	+
	98	+/* Route the I2C1 pins to the SSI port instead. */
	99	+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
	100	+
	101	+/* Choose the 12.288Mhz codec reference clock */
	102	+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
	103	+
	104	+/* Choose the 11.2896Mhz codec reference clock */
	105	+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
	106	+
93	107	int misc_init_r(void)
94	108	{
95	109	u8 temp;
	110	+ const char *audclk;
	111	+ size_t arglen;
96	112
97		- /* Enable the TFP410 Encoder */
	113	+ /* For DVI, enable the TFP410 Encoder. */
98	114
99	115	temp = 0xBF;
100	116	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
101	117	return -1;
102		-
103		- /* Verify if enabled */
104		- temp = 0;
105	118	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
106	119	return -1;
107		-
108	120	debug("DVI Encoder Read: 0x%02x\n", temp);
109	121
110	122	temp = 0x10;
111	123	if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
112	124	return -1;
113		-
114		- /* Verify if enabled */
115		- temp = 0;
116	125	if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
117	126	return -1;
118		-
119	127	debug("DVI Encoder Read: 0x%02x\n",temp);
120	128
	129	+ /*
	130	+ * Enable the reference clock for the WM8776 codec, and route the MUX
	131	+ * pins for SSI. The default is the 12.288 MHz clock
	132	+ */
	133	+
	134	+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK \|
	135	+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
	136	+ temp \|= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
	137	+
	138	+ audclk = hwconfig_arg("audclk", &arglen);
	139	+ /* Check the first two chars only */
	140	+ if (audclk && (strncmp(audclk, "11", 2) == 0))
	141	+ temp \|= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
	142	+ else
	143	+ temp \|= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
	144	+ out_8(&pixis->brdcfg1, temp);
	145	+
121	146	return 0;
122	147	}
123	148
...	...	@@ -310,6 +335,27 @@
310	335	}
311	336
312	337	#ifdef CONFIG_OF_BOARD_SETUP
	338	+/**
	339	+ * ft_codec_setup - fix up the clock-frequency property of the codec node
	340	+ *
	341	+ * Update the clock-frequency property based on the value of the 'audclk'
	342	+ * hwconfig option. If audclk is not specified, then default to 12.288MHz.
	343	+ */
	344	+static void ft_codec_setup(void blob, const char compatible)
	345	+{
	346	+ const char *audclk;
	347	+ size_t arglen;
	348	+ u32 freq;
	349	+
	350	+ audclk = hwconfig_arg("audclk", &arglen);
	351	+ if (audclk && (strncmp(audclk, "11", 2) == 0))
	352	+ freq = 11289600;
	353	+ else
	354	+ freq = 12288000;
	355	+
	356	+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
	357	+}
	358	+
313	359	void ft_board_setup(void blob, bd_t bd)
314	360	{
315	361	phys_addr_t base;
...	...	@@ -327,6 +373,9 @@
327	373	#ifdef CONFIG_FSL_SGMII_RISER
328	374	fsl_sgmii_riser_fdt_fixup(blob);
329	375	#endif
	376	+
	377	+ /* Update the WM8776 node's clock frequency property */
	378	+ ft_codec_setup(blob, "wlf,wm8776");
330	379	}
331	380	#endif
332	381
	1	+Freescale-specific 'hwconfig' options.
	2	+
	3	+This file documents Freescale-specific key:value pairs for the 'hwconfig'
	4	+option. See README.hwconfig for general information about 'hwconfig'.
	5	+
	6	+audclk
	7	+ Specific to the P1022DS reference board.
	8	+
	9	+ This option specifies which of the two oscillator frequencies should be
	10	+ routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to
	11	+ route either a 11.2896MHz or a 12.288MHz clock. The default is
	12	+ 12.288MHz. This option has two effects. First, the MUX on the board
	13	+ will be programmed accordingly. Second, the clock-frequency property
	14	+ in the codec node in the device tree will be updated to the correct
	15	+ value.
	16	+
	17	+ 'audclk:11'
	18	+ Select the 11.2896MHz clock
	19	+
	20	+ 'audclk:12'
	21	+ Select the 12.288MHz clock
...	...	@@ -134,6 +134,7 @@
134	134	#define CONFIG_BOARD_EARLY_INIT_F
135	135	#define CONFIG_BOARD_EARLY_INIT_R
136	136	#define CONFIG_MISC_INIT_R
	137	+#define CONFIG_HWCONFIG
137	138
138	139	#define CONFIG_FSL_NGPIXIS
139	140	#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */