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Commit a2e3b05e16c96ccc5929d60457938cd96912d758

Authored by Bin Meng
1 parent 87077e97d1
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: Add Intel Cougar Canyon 2 board 

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Showing 12 changed files with 298 additions and 0 deletions Side-by-side Diff

arch/x86/cpu/ivybridge/Kconfig
Diff comments   View file @ a2e3b05
... ... @@ -79,5 +79,9 @@
79 79 bool
80 80 default n
81 81  
  82 +config FSP_BROKEN_HOB
  83 + bool
  84 + default y
  85 +
82 86 endif
arch/x86/dts/Makefile
Diff comments   View file @ a2e3b05
... ... @@ -5,6 +5,7 @@
5 5 dtb-y += bayleybay.dtb \
6 6 chromebook_link.dtb \
7 7 chromebox_panther.dtb \
  8 + cougarcanyon2.dtb \
8 9 crownbay.dtb \
9 10 efi.dtb \
10 11 galileo.dtb \
arch/x86/dts/cougarcanyon2.dts
Diff comments   View file @ a2e3b05
  1 +/*
  2 + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/dts-v1/;
  8 +
  9 +/include/ "skeleton.dtsi"
  10 +/include/ "serial.dtsi"
  11 +/include/ "keyboard.dtsi"
  12 +/include/ "rtc.dtsi"
  13 +/include/ "tsc_timer.dtsi"
  14 +
  15 +/ {
  16 + model = "Intel Cougar Canyon 2";
  17 + compatible = "intel,cougarcanyon2", "intel,chiefriver";
  18 +
  19 + aliases {
  20 + spi0 = &spi0;
  21 + };
  22 +
  23 + config {
  24 + silent_console = <0>;
  25 + };
  26 +
  27 + chosen {
  28 + stdout-path = "/serial";
  29 + };
  30 +
  31 + microcode {
  32 + update@0 {
  33 +#include "microcode/m12306a2_00000008.dtsi"
  34 + };
  35 + update@1 {
  36 +#include "microcode/m12306a4_00000007.dtsi"
  37 + };
  38 + update@2 {
  39 +#include "microcode/m12306a5_00000007.dtsi"
  40 + };
  41 + update@3 {
  42 +#include "microcode/m12306a8_00000010.dtsi"
  43 + };
  44 + update@4 {
  45 +#include "microcode/m12306a9_0000001b.dtsi"
  46 + };
  47 + };
  48 +
  49 + fsp {
  50 + compatible = "intel,ivybridge-fsp";
  51 + fsp,enable-ht;
  52 + };
  53 +
  54 + pci {
  55 + #address-cells = <3>;
  56 + #size-cells = <2>;
  57 + compatible = "pci-x86";
  58 + u-boot,dm-pre-reloc;
  59 + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  60 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  61 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  62 +
  63 + pch@1f,0 {
  64 + reg = <0x0000f800 0 0 0 0>;
  65 + compatible = "intel,bd82x6x";
  66 + u-boot,dm-pre-reloc;
  67 + #address-cells = <1>;
  68 + #size-cells = <1>;
  69 +
  70 + spi0: spi {
  71 + #address-cells = <1>;
  72 + #size-cells = <0>;
  73 + compatible = "intel,ich9-spi";
  74 + spi-flash@0 {
  75 + reg = <0>;
  76 + compatible = "winbond,w25q64bv", "spi-flash";
  77 + memory-map = <0xff800000 0x00800000>;
  78 + };
  79 + };
  80 +
  81 + gpioa {
  82 + compatible = "intel,ich6-gpio";
  83 + u-boot,dm-pre-reloc;
  84 + reg = <0 0x10>;
  85 + bank-name = "A";
  86 + };
  87 +
  88 + gpiob {
  89 + compatible = "intel,ich6-gpio";
  90 + u-boot,dm-pre-reloc;
  91 + reg = <0x30 0x10>;
  92 + bank-name = "B";
  93 + };
  94 +
  95 + gpioc {
  96 + compatible = "intel,ich6-gpio";
  97 + u-boot,dm-pre-reloc;
  98 + reg = <0x40 0x10>;
  99 + bank-name = "C";
  100 + };
  101 + };
  102 + };
  103 +
  104 +};
... ... @@ -18,6 +18,14 @@
18 18 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
19 19 PCIe and some other sensor interfaces.
20 20  
  21 +config TARGET_COUGARCANYON2
  22 + bool "Cougar Canyon 2"
  23 + help
  24 + This is the Intel Cougar Canyon 2 Customer Reference Board. It
  25 + is built on the Chief River platform with Intel Ivybridge Processor
  26 + and Panther Point chipset. The board has 4GB RAM, with some other
  27 + peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
  28 +
21 29 config TARGET_CROWNBAY
22 30 bool "Crown Bay"
23 31 help
... ... @@ -54,6 +62,7 @@
54 62 endchoice
55 63  
56 64 source "board/intel/bayleybay/Kconfig"
  65 +source "board/intel/cougarcanyon2/Kconfig"
57 66 source "board/intel/crownbay/Kconfig"
58 67 source "board/intel/galileo/Kconfig"
59 68 source "board/intel/minnowmax/Kconfig"
board/intel/cougarcanyon2/Kconfig
Diff comments   View file @ a2e3b05
  1 +if TARGET_COUGARCANYON2
  2 +
  3 +config SYS_BOARD
  4 + default "cougarcanyon2"
  5 +
  6 +config SYS_VENDOR
  7 + default "intel"
  8 +
  9 +config SYS_SOC
  10 + default "ivybridge"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "cougarcanyon2"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0xffe00000
  17 +
  18 +config BOARD_SPECIFIC_OPTIONS # dummy
  19 + def_bool y
  20 + select X86_RESET_VECTOR
  21 + select NORTHBRIDGE_INTEL_IVYBRIDGE
  22 + select HAVE_FSP
  23 + select BOARD_ROMSIZE_KB_2048
  24 +
  25 +endif
board/intel/cougarcanyon2/MAINTAINERS
Diff comments   View file @ a2e3b05
  1 +INTEL COUGAR CANYON 2 BOARD
  2 +M: Bin Meng <bmeng.cn@gmail.com>
  3 +S: Maintained
  4 +F: board/intel/cougarcanyon2/
  5 +F: include/configs/cougarcanyon2.h
  6 +F: configs/cougarcanyon2_defconfig
board/intel/cougarcanyon2/Makefile
Diff comments   View file @ a2e3b05
  1 +#
  2 +# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += cougarcanyon2.o start.o
board/intel/cougarcanyon2/cougarcanyon2.c
Diff comments   View file @ a2e3b05
  1 +/*
  2 + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <dm.h>
  9 +#include <errno.h>
  10 +#include <pci.h>
  11 +#include <smsc_sio1007.h>
  12 +#include <asm/ibmpc.h>
  13 +#include <asm/pci.h>
  14 +#include <asm/arch/pch.h>
  15 +
  16 +#define SIO1007_RUNTIME_IOPORT 0x180
  17 +
  18 +int board_early_init_f(void)
  19 +{
  20 + struct udevice *pch;
  21 + int ret;
  22 +
  23 + ret = uclass_first_device(UCLASS_PCH, &pch);
  24 + if (ret)
  25 + return ret;
  26 + if (!pch)
  27 + return -ENODEV;
  28 +
  29 + /* Initialize LPC interface to turn on superio chipset decode range */
  30 + dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
  31 + dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
  32 + dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
  33 + (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
  34 + dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
  35 + SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
  36 +
  37 + /* Enable legacy serial port at 0x3f8 */
  38 + sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
  39 +
  40 + /* Enable SIO1007 runtime I/O port at 0x180 */
  41 + sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
  42 +
  43 + /*
  44 + * On Cougar Canyon 2 board, the RS232 transiver connected to serial
  45 + * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
  46 + * Set the pin value to 1 to enable the RS232 transiver.
  47 + */
  48 + sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
  49 + GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
  50 + sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
  51 +
  52 + return 0;
  53 +}
  54 +
  55 +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
  56 +{
  57 + return;
  58 +}
board/intel/cougarcanyon2/start.S
Diff comments   View file @ a2e3b05
  1 +/*
  2 + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +.globl early_board_init
  8 +early_board_init:
  9 + jmp early_board_init_ret
configs/cougarcanyon2_defconfig
Diff comments   View file @ a2e3b05
  1 +CONFIG_X86=y
  2 +CONFIG_VENDOR_INTEL=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
  4 +CONFIG_TARGET_COUGARCANYON2=y
  5 +# CONFIG_CMD_IMLS is not set
  6 +# CONFIG_CMD_FLASH is not set
  7 +CONFIG_CMD_GPIO=y
  8 +# CONFIG_CMD_SETEXPR is not set
  9 +# CONFIG_CMD_NFS is not set
  10 +CONFIG_OF_CONTROL=y
  11 +CONFIG_SPI_FLASH=y
  12 +CONFIG_SPI_FLASH_WINBOND=y
  13 +CONFIG_DM_PCI=y
  14 +CONFIG_DM_RTC=y
  15 +CONFIG_SYS_NS16550=y
  16 +CONFIG_ICH_SPI=y
  17 +CONFIG_TIMER=y
  18 +CONFIG_USB=y
  19 +CONFIG_DM_USB=y
  20 +CONFIG_USE_PRIVATE_LIBGCC=y
... ... @@ -133,6 +133,27 @@
133 133  
134 134 ---
135 135  
  136 +Intel Cougar Canyon 2 specific instructions for bare mode:
  137 +
  138 +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
  139 +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
  140 +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
  141 +time of writing) in the board directory and rename it to fsp.bin.
  142 +
  143 +Now build U-Boot and obtain u-boot.rom
  144 +
  145 +$ make cougarcanyon2_defconfig
  146 +$ make all
  147 +
  148 +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
  149 +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
  150 +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
  151 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
  152 +this image to the SPI-0 flash according to the board manual just once and we are
  153 +all set. For programming U-Boot we just need to program SPI-1 flash.
  154 +
  155 +---
  156 +
136 157 Intel Minnowboard Max instructions for bare mode:
137 158  
138 159 This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
include/configs/cougarcanyon2.h
Diff comments   View file @ a2e3b05
  1 +/*
  2 + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CONFIG_H
  8 +#define __CONFIG_H
  9 +
  10 +#include <configs/x86-common.h>
  11 +
  12 +#define CONFIG_SYS_MONITOR_LEN (2 << 20)
  13 +#define CONFIG_BOARD_EARLY_INIT_F
  14 +
  15 +#define CONFIG_SMSC_SIO1007
  16 +
  17 +#define CONFIG_PCI_PNP
  18 +
  19 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
  20 + "stdout=serial,vga\0" \
  21 + "stderr=serial,vga\0"
  22 +
  23 +#define CONFIG_SCSI_DEV_LIST \
  24 + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  25 +
  26 +/* Environment configuration */
  27 +#define CONFIG_ENV_SECT_SIZE 0x1000
  28 +#define CONFIG_ENV_OFFSET 0x5ff000
  29 +
  30 +/* Video is not supported for now */
  31 +#undef CONFIG_VIDEO
  32 +#undef CONFIG_CFB_CONSOLE
  33 +
  34 +#endif /* __CONFIG_H */