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Commit a2f39e830e509cb63aad2c752573d1c871a1d4bf

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 346cfba4f0
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: remove cm4008 and cm41xx board support 

These are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>

Showing 30 changed files with 2 additions and 2168 deletions Side-by-side Diff

... ... @@ -88,14 +88,6 @@
88 88 bool "Support scb9328"
89 89 select CPU_ARM920T
90 90  
91   -config TARGET_CM4008
92   - bool "Support cm4008"
93   - select CPU_ARM920T
94   -
95   -config TARGET_CM41XX
96   - bool "Support cm41xx"
97   - select CPU_ARM920T
98   -
99 91 config TARGET_VCMA9
100 92 bool "Support VCMA9"
101 93 select CPU_ARM920T
... ... @@ -769,8 +761,6 @@
769 761 source "board/broadcom/bcmcygnus/Kconfig"
770 762 source "board/broadcom/bcmnsp/Kconfig"
771 763 source "board/cirrus/edb93xx/Kconfig"
772   -source "board/cm4008/Kconfig"
773   -source "board/cm41xx/Kconfig"
774 764 source "board/compulab/cm_t335/Kconfig"
775 765 source "board/compulab/cm_fx6/Kconfig"
776 766 source "board/congatec/cgtqmx6eval/Kconfig"
arch/arm/cpu/arm920t/Makefile
Diff comments   View file @ a2f39e8
... ... @@ -13,6 +13,5 @@
13 13 obj-$(if $(filter a320,$(SOC)),y) += a320/
14 14 obj-$(CONFIG_EP93XX) += ep93xx/
15 15 obj-$(CONFIG_IMX) += imx/
16   -obj-$(CONFIG_KS8695) += ks8695/
17 16 obj-$(CONFIG_S3C24X0) += s3c24x0/
arch/arm/cpu/arm920t/ks8695/Makefile
View file @ a2f39e8
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = lowlevel_init.o
9   -obj-y += timer.o
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
View file @ a2f39e8
1   -/*
2   - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
3   - *
4   - * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <config.h>
10   -#include <version.h>
11   -#include <asm/arch/platform.h>
12   -
13   -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
14   -
15   -/*
16   - *************************************************************************
17   - *
18   - * Handy dandy macros
19   - *
20   - *************************************************************************
21   - */
22   -
23   -/* Delay a bit */
24   -.macro DELAY_FOR cycles, reg0
25   - ldr \reg0, =\cycles
26   - subs \reg0, \reg0, #1
27   - subne pc, pc, #0xc
28   -.endm
29   -
30   -/*
31   - *************************************************************************
32   - *
33   - * Some local storage.
34   - *
35   - *************************************************************************
36   - */
37   -
38   -/* Should we boot with an interactive console or not */
39   -.globl serial_console
40   -
41   -/*
42   - *************************************************************************
43   - *
44   - * Raw hardware initialization code. The important thing is to get
45   - * SDRAM setup and running. We do some other basic things here too,
46   - * like getting the PLL set for high speed, and init the LEDs.
47   - *
48   - *************************************************************************
49   - */
50   -
51   -.globl lowlevel_init
52   -lowlevel_init:
53   -
54   -#if DEBUG
55   - /*
56   - * enable UART for early debug trace
57   - */
58   - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
59   - mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
60   - str r2, [r1]
61   - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
62   - mov r2, #KS8695_UART_LINEC_WLEN8
63   - str r2, [r1] /* 8 data bits, no parity, 1 stop */
64   - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
65   - mov r2, #0x41
66   - str r2, [r1] /* write 'A' */
67   -#endif
68   -#if DEBUG
69   - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
70   - mov r2, #0x42
71   - str r2, [r1]
72   -#endif
73   -
74   - /*
75   - * remap the memory and flash regions. we want to end up with
76   - * ram from address 0, and flash at 32MB.
77   - */
78   - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
79   - ldr r2, =0xbfc00040
80   - str r2, [r1] /* large flash map */
81   - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
82   -highflash:
83   - ldr r2, =0x8fe00040
84   - str r2, [r1] /* remap flash range */
85   -
86   - /*
87   - * remap the second select region to the 4MB immediately after
88   - * the first region. This way if you have a larger flash (say 8Mb)
89   - * then you can have it all mapped nicely. Has no effect if you
90   - * only have a 4Mb or smaller flash.
91   - */
92   - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
93   - ldr r2, =0x9fe40040
94   - str r2, [r1] /* remap flash2 region, contiguous */
95   - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
96   - ldr r2, =0x30000005
97   - str r2, [r1] /* enable both flash selects */
98   -
99   -#ifdef CONFIG_CM41xx
100   - /*
101   - * map the second flash chip, using the external IO lines.
102   - */
103   - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
104   - ldr r2, =0xafe80b6d
105   - str r2, [r1] /* remap io0 region, contiguous */
106   - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
107   - ldr r2, =0xbfec0b6d
108   - str r2, [r1] /* remap io1 region, contiguous */
109   - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
110   - ldr r2, =0x30050005
111   - str r2, [r1] /* enable second flash */
112   -#endif
113   -
114   - /*
115   - * before relocating, we have to setup RAM timing
116   - */
117   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
118   -#if (PHYS_SDRAM_1_SIZE == 0x02000000)
119   - ldr r2, =0x7fc0000e /* 32MB */
120   -#else
121   - ldr r2, =0x3fc0000e /* 16MB */
122   -#endif
123   - str r2, [r1] /* configure sdram bank0 setup */
124   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
125   - mov r2, #0
126   - str r2, [r1] /* configure sdram bank1 setup */
127   -
128   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
129   - ldr r2, =0x0000000a
130   - str r2, [r1] /* set RAS/CAS timing */
131   -
132   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
133   - ldr r2, =0x00030000
134   - str r2, [r1] /* send NOP command */
135   - DELAY_FOR 0x100, r0
136   - ldr r2, =0x00010000
137   - str r2, [r1] /* send PRECHARGE-ALL */
138   - DELAY_FOR 0x100, r0
139   -
140   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
141   - ldr r2, =0x00000020
142   - str r2, [r1] /* set for fast refresh */
143   - DELAY_FOR 0x100, r0
144   - ldr r2, =0x00000190
145   - str r2, [r1] /* set normal refresh timing */
146   -
147   - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
148   - ldr r2, =0x00020033
149   - str r2, [r1] /* send mode command */
150   - DELAY_FOR 0x100, r0
151   - ldr r2, =0x01f00000
152   - str r2, [r1] /* enable sdram fifos */
153   -
154   - /*
155   - * set pll to top speed
156   - */
157   - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
158   - mov r2, #0
159   - str r2, [r1] /* set pll clock to 166MHz */
160   -
161   - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
162   - ldr r2, [r1] /* Get switch ctrl0 register */
163   - and r2, r2, #0x0fc00000 /* Mask out LED control bits */
164   - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
165   - str r2, [r1]
166   -
167   -#ifdef CONFIG_CM4008
168   - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
169   - ldr r2, =0x0000fe30
170   - str r2, [r1] /* enable LED's as outputs */
171   - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
172   - ldr r2, =0x0000fe20
173   - str r2, [r1] /* turn on power LED */
174   -#endif
175   -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
176   - ldr r2, [r1] /* get current GPIO input data */
177   - tst r2, #0x8 /* check if "erase" depressed */
178   - beq nobutton
179   - mov r2, #0 /* be quiet on boot, no console */
180   - ldr r1, =serial_console
181   - str r2, [r1]
182   -nobutton:
183   -#endif
184   -
185   - add lr, lr, #0x02000000 /* flash is now mapped high */
186   - add ip, ip, #0x02000000 /* this is a hack */
187   - mov pc, lr /* all done, return */
188   -
189   -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
arch/arm/cpu/arm920t/ks8695/timer.c
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <asm/arch/platform.h>
9   -
10   -/*
11   - * Initial timer set constants. Nothing complicated, just set for a 1ms
12   - * tick.
13   - */
14   -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
15   -#define TIMER_COUNT (TIMER_INTERVAL / 2)
16   -#define TIMER_PULSE TIMER_COUNT
17   -
18   -/*
19   - * Handy KS8695 register access functions.
20   - */
21   -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
22   -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
23   -
24   -ulong timer_ticks;
25   -
26   -int timer_init (void)
27   -{
28   - /* Set the hadware timer for 1ms */
29   - ks8695_write(KS8695_TIMER1, TIMER_COUNT);
30   - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
31   - ks8695_write(KS8695_TIMER_CTRL, 0x2);
32   - timer_ticks = 0;
33   -
34   - return 0;
35   -}
36   -
37   -ulong get_timer_masked(void)
38   -{
39   - /* Check for timer wrap */
40   - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
41   - /* Clear interrupt condition */
42   - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
43   - timer_ticks++;
44   - }
45   - return timer_ticks;
46   -}
47   -
48   -ulong get_timer(ulong base)
49   -{
50   - return (get_timer_masked() - base);
51   -}
52   -
53   -void __udelay(ulong usec)
54   -{
55   - ulong start = get_timer_masked();
56   - ulong end;
57   -
58   - /* Only 1ms resolution :-( */
59   - end = usec / 1000;
60   - while (get_timer(start) < end)
61   - ;
62   -}
63   -
64   -void reset_cpu (ulong ignored)
65   -{
66   - ulong tc;
67   -
68   - /* Set timer0 to watchdog, and let it timeout */
69   - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
70   - ks8695_write(KS8695_TIMER_CTRL, tc);
71   - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
72   - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
73   -
74   - /* Should only wait here till watchdog resets */
75   - for (;;)
76   - ;
77   -}
arch/arm/include/asm/arch-ks8695/platform.h
View file @ a2f39e8
1   -/*
2   - * SPDX-License-Identifier: GPL-2.0+
3   - */
4   -#ifndef __address_h
5   -#define __address_h 1
6   -
7   -#define KS8695_SDRAM_START 0x00000000
8   -#define KS8695_SDRAM_SIZE 0x01000000
9   -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
10   -#define KS8695_MEM_START KS8695_SDRAM_START
11   -
12   -#define KS8695_PCMCIA_IO_BASE 0x03800000
13   -#define KS8695_PCMCIA_IO_SIZE 0x00040000
14   -
15   -#define KS8695_IO_BASE 0x03FF0000
16   -#define KS8695_IO_SIZE 0x00010000
17   -
18   -#define KS8695_SYSTEN_CONFIG 0x00
19   -#define KS8695_SYSTEN_BUS_CLOCK 0x04
20   -
21   -#define KS8695_FLASH_START 0x02800000
22   -#define KS8695_FLASH_SIZE 0x00400000
23   -
24   -/*i/o control registers offset difinitions*/
25   -#define KS8695_IO_CTRL0 0x4000
26   -#define KS8695_IO_CTRL1 0x4004
27   -#define KS8695_IO_CTRL2 0x4008
28   -#define KS8695_IO_CTRL3 0x400C
29   -
30   -/*memory control registers offset difinitions*/
31   -#define KS8695_MEM_CTRL0 0x4010
32   -#define KS8695_MEM_CTRL1 0x4014
33   -#define KS8695_MEM_CTRL2 0x4018
34   -#define KS8695_MEM_CTRL3 0x401C
35   -#define KS8695_MEM_GENERAL 0x4020
36   -#define KS8695_SDRAM_CTRL0 0x4030
37   -#define KS8695_SDRAM_CTRL1 0x4034
38   -#define KS8695_SDRAM_GENERAL 0x4038
39   -#define KS8695_SDRAM_BUFFER 0x403C
40   -#define KS8695_SDRAM_REFRESH 0x4040
41   -
42   -/*WAN control registers offset difinitions*/
43   -#define KS8695_WAN_DMA_TX 0x6000
44   -#define KS8695_WAN_DMA_RX 0x6004
45   -#define KS8695_WAN_DMA_TX_START 0x6008
46   -#define KS8695_WAN_DMA_RX_START 0x600C
47   -#define KS8695_WAN_TX_LIST 0x6010
48   -#define KS8695_WAN_RX_LIST 0x6014
49   -#define KS8695_WAN_MAC_LOW 0x6018
50   -#define KS8695_WAN_MAC_HIGH 0x601C
51   -#define KS8695_WAN_MAC_ELOW 0x6080
52   -#define KS8695_WAN_MAC_EHIGH 0x6084
53   -
54   -/*LAN control registers offset difinitions*/
55   -#define KS8695_LAN_DMA_TX 0x8000
56   -#define KS8695_LAN_DMA_RX 0x8004
57   -#define KS8695_LAN_DMA_TX_START 0x8008
58   -#define KS8695_LAN_DMA_RX_START 0x800C
59   -#define KS8695_LAN_TX_LIST 0x8010
60   -#define KS8695_LAN_RX_LIST 0x8014
61   -#define KS8695_LAN_MAC_LOW 0x8018
62   -#define KS8695_LAN_MAC_HIGH 0x801C
63   -#define KS8695_LAN_MAC_ELOW 0X8080
64   -#define KS8695_LAN_MAC_EHIGH 0X8084
65   -
66   -/*HPNA control registers offset difinitions*/
67   -#define KS8695_HPNA_DMA_TX 0xA000
68   -#define KS8695_HPNA_DMA_RX 0xA004
69   -#define KS8695_HPNA_DMA_TX_START 0xA008
70   -#define KS8695_HPNA_DMA_RX_START 0xA00C
71   -#define KS8695_HPNA_TX_LIST 0xA010
72   -#define KS8695_HPNA_RX_LIST 0xA014
73   -#define KS8695_HPNA_MAC_LOW 0xA018
74   -#define KS8695_HPNA_MAC_HIGH 0xA01C
75   -#define KS8695_HPNA_MAC_ELOW 0xA080
76   -#define KS8695_HPNA_MAC_EHIGH 0xA084
77   -
78   -/*UART control registers offset difinitions*/
79   -#define KS8695_UART_RX_BUFFER 0xE000
80   -#define KS8695_UART_TX_HOLDING 0xE004
81   -
82   -#define KS8695_UART_FIFO_CTRL 0xE008
83   -#define KS8695_UART_FIFO_TRIG01 0x00
84   -#define KS8695_UART_FIFO_TRIG04 0x80
85   -#define KS8695_UART_FIFO_TXRST 0x03
86   -#define KS8695_UART_FIFO_RXRST 0x02
87   -#define KS8695_UART_FIFO_FEN 0x01
88   -
89   -#define KS8695_UART_LINE_CTRL 0xE00C
90   -#define KS8695_UART_LINEC_BRK 0x40
91   -#define KS8695_UART_LINEC_EPS 0x10
92   -#define KS8695_UART_LINEC_PEN 0x08
93   -#define KS8695_UART_LINEC_STP2 0x04
94   -#define KS8695_UART_LINEC_WLEN8 0x03
95   -#define KS8695_UART_LINEC_WLEN7 0x02
96   -#define KS8695_UART_LINEC_WLEN6 0x01
97   -#define KS8695_UART_LINEC_WLEN5 0x00
98   -
99   -#define KS8695_UART_MODEM_CTRL 0xE010
100   -#define KS8695_UART_MODEMC_RTS 0x02
101   -#define KS8695_UART_MODEMC_DTR 0x01
102   -
103   -#define KS8695_UART_LINE_STATUS 0xE014
104   -#define KS8695_UART_LINES_TXFE 0x20
105   -#define KS8695_UART_LINES_BE 0x10
106   -#define KS8695_UART_LINES_FE 0x08
107   -#define KS8695_UART_LINES_PE 0x04
108   -#define KS8695_UART_LINES_OE 0x02
109   -#define KS8695_UART_LINES_RXFE 0x01
110   -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
111   -
112   -#define KS8695_UART_MODEM_STATUS 0xE018
113   -#define KS8695_UART_MODEM_DCD 0x80
114   -#define KS8695_UART_MODEM_DSR 0x20
115   -#define KS8695_UART_MODEM_CTS 0x10
116   -#define KS8695_UART_MODEM_DDCD 0x08
117   -#define KS8695_UART_MODEM_DDSR 0x02
118   -#define KS8695_UART_MODEM_DCTS 0x01
119   -#define UART8695_MODEM_ANY 0xFF
120   -
121   -#define KS8695_UART_DIVISOR 0xE01C
122   -#define KS8695_UART_STATUS 0xE020
123   -
124   -/*Interrupt controlller registers offset difinitions*/
125   -#define KS8695_INT_CONTL 0xE200
126   -#define KS8695_INT_ENABLE 0xE204
127   -#define KS8695_INT_ENABLE_MODEM 0x0800
128   -#define KS8695_INT_ENABLE_ERR 0x0400
129   -#define KS8695_INT_ENABLE_RX 0x0200
130   -#define KS8695_INT_ENABLE_TX 0x0100
131   -
132   -#define KS8695_INT_STATUS 0xE208
133   -#define KS8695_INT_WAN_PRIORITY 0xE20C
134   -#define KS8695_INT_HPNA_PRIORITY 0xE210
135   -#define KS8695_INT_LAN_PRIORITY 0xE214
136   -#define KS8695_INT_TIMER_PRIORITY 0xE218
137   -#define KS8695_INT_UART_PRIORITY 0xE21C
138   -#define KS8695_INT_EXT_PRIORITY 0xE220
139   -#define KS8695_INT_CHAN_PRIORITY 0xE224
140   -#define KS8695_INT_BUSERROR_PRO 0xE228
141   -#define KS8695_INT_MASK_STATUS 0xE22C
142   -#define KS8695_FIQ_PEND_PRIORITY 0xE230
143   -#define KS8695_IRQ_PEND_PRIORITY 0xE234
144   -
145   -/*timer registers offset difinitions*/
146   -#define KS8695_TIMER_CTRL 0xE400
147   -#define KS8695_TIMER1 0xE404
148   -#define KS8695_TIMER0 0xE408
149   -#define KS8695_TIMER1_PCOUNT 0xE40C
150   -#define KS8695_TIMER0_PCOUNT 0xE410
151   -
152   -/*GPIO registers offset difinitions*/
153   -#define KS8695_GPIO_MODE 0xE600
154   -#define KS8695_GPIO_CTRL 0xE604
155   -#define KS8695_GPIO_DATA 0xE608
156   -
157   -/*SWITCH registers offset difinitions*/
158   -#define KS8695_SWITCH_CTRL0 0xE800
159   -#define KS8695_SWITCH_CTRL1 0xE804
160   -#define KS8695_SWITCH_PORT1 0xE808
161   -#define KS8695_SWITCH_PORT2 0xE80C
162   -#define KS8695_SWITCH_PORT3 0xE810
163   -#define KS8695_SWITCH_PORT4 0xE814
164   -#define KS8695_SWITCH_PORT5 0xE818
165   -#define KS8695_SWITCH_AUTO0 0xE81C
166   -#define KS8695_SWITCH_AUTO1 0xE820
167   -#define KS8695_SWITCH_LUE_CTRL 0xE824
168   -#define KS8695_SWITCH_LUE_HIGH 0xE828
169   -#define KS8695_SWITCH_LUE_LOW 0xE82C
170   -#define KS8695_SWITCH_ADVANCED 0xE830
171   -
172   -#define KS8695_SWITCH_LPPM12 0xE874
173   -#define KS8695_SWITCH_LPPM34 0xE878
174   -
175   -/*host communication registers difinitions*/
176   -#define KS8695_DSCP_HIGH 0xE834
177   -#define KS8695_DSCP_LOW 0xE838
178   -#define KS8695_SWITCH_MAC_HIGH 0xE83C
179   -#define KS8695_SWITCH_MAC_LOW 0xE840
180   -
181   -/*miscellaneours registers difinitions*/
182   -#define KS8695_MANAGE_COUNTER 0xE844
183   -#define KS8695_MANAGE_DATA 0xE848
184   -#define KS8695_LAN12_POWERMAGR 0xE84C
185   -#define KS8695_LAN34_POWERMAGR 0xE850
186   -
187   -#define KS8695_DEVICE_ID 0xEA00
188   -#define KS8695_REVISION_ID 0xEA04
189   -
190   -#define KS8695_MISC_CONTROL 0xEA08
191   -#define KS8695_WAN_CONTROL 0xEA0C
192   -#define KS8695_WAN_POWERMAGR 0xEA10
193   -#define KS8695_WAN_PHY_CONTROL 0xEA14
194   -#define KS8695_WAN_PHY_STATUS 0xEA18
195   -
196   -/* bus clock definitions*/
197   -#define KS8695_BUS_CLOCK_125MHZ 0x0
198   -#define KS8695_BUS_CLOCK_100MHZ 0x1
199   -#define KS8695_BUS_CLOCK_62MHZ 0x2
200   -#define KS8695_BUS_CLOCK_50MHZ 0x3
201   -#define KS8695_BUS_CLOCK_41MHZ 0x4
202   -#define KS8695_BUS_CLOCK_33MHZ 0x5
203   -#define KS8695_BUS_CLOCK_31MHZ 0x6
204   -#define KS8695_BUS_CLOCK_25MHZ 0x7
205   -
206   -/* -------------------------------------------------------------------------------
207   - * definations for IRQ
208   - * -------------------------------------------------------------------------------*/
209   -
210   -#define KS8695_INT_EXT_INT0 2
211   -#define KS8695_INT_EXT_INT1 3
212   -#define KS8695_INT_EXT_INT2 4
213   -#define KS8695_INT_EXT_INT3 5
214   -#define KS8695_INT_TIMERINT0 6
215   -#define KS8695_INT_TIMERINT1 7
216   -#define KS8695_INT_UART_TX 8
217   -#define KS8695_INT_UART_RX 9
218   -#define KS8695_INT_UART_LINE_ERR 10
219   -#define KS8695_INT_UART_MODEMS 11
220   -#define KS8695_INT_LAN_STOP_RX 12
221   -#define KS8695_INT_LAN_STOP_TX 13
222   -#define KS8695_INT_LAN_BUF_RX_STATUS 14
223   -#define KS8695_INT_LAN_BUF_TX_STATUS 15
224   -#define KS8695_INT_LAN_RX_STATUS 16
225   -#define KS8695_INT_LAN_TX_STATUS 17
226   -#define KS8695_INT_HPAN_STOP_RX 18
227   -#define KS8695_INT_HPNA_STOP_TX 19
228   -#define KS8695_INT_HPNA_BUF_RX_STATUS 20
229   -#define KS8695_INT_HPNA_BUF_TX_STATUS 21
230   -#define KS8695_INT_HPNA_RX_STATUS 22
231   -#define KS8695_INT_HPNA_TX_STATUS 23
232   -#define KS8695_INT_BUS_ERROR 24
233   -#define KS8695_INT_WAN_STOP_RX 25
234   -#define KS8695_INT_WAN_STOP_TX 26
235   -#define KS8695_INT_WAN_BUF_RX_STATUS 27
236   -#define KS8695_INT_WAN_BUF_TX_STATUS 28
237   -#define KS8695_INT_WAN_RX_STATUS 29
238   -#define KS8695_INT_WAN_TX_STATUS 30
239   -
240   -#define KS8695_INT_UART KS8695_INT_UART_TX
241   -
242   -/* -------------------------------------------------------------------------------
243   - * Interrupt bit positions
244   - *
245   - * -------------------------------------------------------------------------------
246   - */
247   -
248   -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
249   -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
250   -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
251   -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
252   -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
253   -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
254   -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
255   -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
256   -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
257   -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
258   -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
259   -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
260   -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
261   -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
262   -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
263   -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
264   -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
265   -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
266   -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
267   -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
268   -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
269   -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
270   -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
271   -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
272   -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
273   -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
274   -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
275   -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
276   -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
277   -
278   -#define KS8695_SC_VALID_INT 0xFFFFFFFF
279   -#define MAXIRQNUM 31
280   -
281   -/*
282   - * Timer definitions
283   - *
284   - * Use timer 1 & 2
285   - * (both run at 25MHz).
286   - *
287   - */
288   -#define TICKS_PER_uSEC 25
289   -#define mSEC_1 1000
290   -#define mSEC_10 (mSEC_1 * 10)
291   -
292   -#endif
293   -
294   -/* END */
board/cm4008/Kconfig
View file @ a2f39e8
1   -if TARGET_CM4008
2   -
3   -config SYS_BOARD
4   - default "cm4008"
5   -
6   -config SYS_SOC
7   - default "ks8695"
8   -
9   -config SYS_CONFIG_NAME
10   - default "cm4008"
11   -
12   -endif
board/cm4008/MAINTAINERS
View file @ a2f39e8
1   -CM4008 BOARD
2   -M: Greg Ungerer <greg.ungerer@opengear.com>
3   -S: Maintained
4   -F: board/cm4008/
5   -F: include/configs/cm4008.h
6   -F: configs/cm4008_defconfig
board/cm4008/Makefile
View file @ a2f39e8
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := cm4008.o flash.o
board/cm4008/cm4008.c
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2005
3   - * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
4   - *
5   - * (C) Copyright 2002
6   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7   - *
8   - * (C) Copyright 2002
9   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10   - * Marius Groeger <mgroeger@sysgo.de>
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/platform.h>
17   -#include <netdev.h>
18   -
19   -DECLARE_GLOBAL_DATA_PTR;
20   -
21   -/* ------------------------------------------------------------------------- */
22   -
23   -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
24   -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
25   -
26   -/* ------------------------------------------------------------------------- */
27   -
28   -
29   -/*
30   - * Miscelaneous platform dependent initialisations
31   - */
32   -int env_flash_cmdline (void)
33   -{
34   - char *sp = (char *) 0x0201c020;
35   - char *ep;
36   - int len;
37   -
38   - /* Check if "erase" push button is depressed */
39   - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
40   - printf("### Entering network recovery mode...\n");
41   - setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
42   - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
43   - setenv("bootdelay", "2");
44   - return 0;
45   - }
46   -
47   - /* Check for flash based kernel boot args to use as default */
48   - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
49   - ;
50   -
51   - if ((len > 0) && (len <1024))
52   - setenv("bootargs", sp);
53   -
54   - return 0;
55   -}
56   -
57   -int board_late_init (void)
58   -{
59   - return 0;
60   -}
61   -
62   -int board_eth_init(bd_t *bis)
63   -{
64   - return ks8695_eth_initialize();
65   -}
66   -
67   -int board_init (void)
68   -{
69   - /* arch number of CM4008 */
70   - gd->bd->bi_arch_number = 624;
71   -
72   - /* adress of boot parameters */
73   - gd->bd->bi_boot_params = 0x00000100;
74   -
75   - /* power down all but port 0 on the switch */
76   - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
77   - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
78   -
79   - return 0;
80   -}
81   -
82   -int dram_init (void)
83   -{
84   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
85   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
86   -
87   - return (0);
88   -}
board/cm4008/config.mk
View file @ a2f39e8
1   -CONFIG_SYS_TEXT_BASE = 0x00f00000
board/cm4008/flash.c
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2005
3   - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
4   - *
5   - * (C) Copyright 2001
6   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7   - *
8   - * (C) Copyright 2001
9   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <linux/byteorder/swab.h>
16   -#include <asm/sections.h>
17   -
18   -
19   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
20   -
21   -#define mb() __asm__ __volatile__ ("" : : : "memory")
22   -
23   -/*-----------------------------------------------------------------------
24   - * Functions
25   - */
26   -static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
27   -static int write_data (flash_info_t * info, ulong dest, unsigned char data);
28   -static void flash_get_offsets (ulong base, flash_info_t * info);
29   -void inline spin_wheel (void);
30   -
31   -/*-----------------------------------------------------------------------
32   - */
33   -
34   -unsigned long flash_init (void)
35   -{
36   - int i;
37   - ulong size = 0;
38   -
39   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
40   - switch (i) {
41   - case 0:
42   - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
43   - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
44   - break;
45   - case 1:
46   - /* ignore for now */
47   - flash_info[i].flash_id = FLASH_UNKNOWN;
48   - break;
49   - default:
50   - panic ("configured too many flash banks!\n");
51   - break;
52   - }
53   - size += flash_info[i].size;
54   - }
55   -
56   - /* Protect monitor and environment sectors
57   - */
58   - flash_protect (FLAG_PROTECT_SET,
59   - CONFIG_SYS_FLASH_BASE,
60   - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
61   - &flash_info[0]);
62   -
63   - return size;
64   -}
65   -
66   -/*-----------------------------------------------------------------------
67   - */
68   -static void flash_get_offsets (ulong base, flash_info_t * info)
69   -{
70   - int i;
71   -
72   - if (info->flash_id == FLASH_UNKNOWN)
73   - return;
74   -
75   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
76   - for (i = 0; i < info->sector_count; i++) {
77   - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
78   - info->protect[i] = 0;
79   - }
80   - }
81   -}
82   -
83   -/*-----------------------------------------------------------------------
84   - */
85   -void flash_print_info (flash_info_t * info)
86   -{
87   - int i;
88   -
89   - if (info->flash_id == FLASH_UNKNOWN) {
90   - printf ("missing or unknown FLASH type\n");
91   - return;
92   - }
93   -
94   - switch (info->flash_id & FLASH_VENDMASK) {
95   - case FLASH_MAN_INTEL:
96   - printf ("INTEL ");
97   - break;
98   - default:
99   - printf ("Unknown Vendor ");
100   - break;
101   - }
102   -
103   - switch (info->flash_id & FLASH_TYPEMASK) {
104   - case FLASH_28F128J3A:
105   - printf ("28F128J3A\n");
106   - break;
107   - default:
108   - printf ("Unknown Chip Type\n");
109   - break;
110   - }
111   -
112   - printf (" Size: %ld MB in %d Sectors\n",
113   - info->size >> 20, info->sector_count);
114   -
115   - printf (" Sector Start Addresses:");
116   - for (i = 0; i < info->sector_count; ++i) {
117   - if ((i % 5) == 0)
118   - printf ("\n ");
119   - printf (" %08lX%s",
120   - info->start[i], info->protect[i] ? " (RO)" : " ");
121   - }
122   - printf ("\n");
123   - return;
124   -}
125   -
126   -/*
127   - * The following code cannot be run from FLASH!
128   - */
129   -static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
130   -{
131   - volatile unsigned char value;
132   -
133   - /* Write auto select command: read Manufacturer ID */
134   - addr[0x5555] = 0xAA;
135   - addr[0x2AAA] = 0x55;
136   - addr[0x5555] = 0x90;
137   -
138   - mb ();
139   - value = addr[0];
140   -
141   - switch (value) {
142   -
143   - case (unsigned char)INTEL_MANUFACT:
144   - info->flash_id = FLASH_MAN_INTEL;
145   - break;
146   -
147   - default:
148   - info->flash_id = FLASH_UNKNOWN;
149   - info->sector_count = 0;
150   - info->size = 0;
151   - addr[0] = 0xFF; /* restore read mode */
152   - return (0); /* no or unknown flash */
153   - }
154   -
155   - mb ();
156   - value = addr[2]; /* device ID */
157   -
158   - switch (value) {
159   -
160   - case (unsigned char)INTEL_ID_28F640J3A:
161   - info->flash_id += FLASH_28F640J3A;
162   - info->sector_count = 64;
163   - info->size = 0x00800000;
164   - break; /* => 8 MB */
165   -
166   - case (unsigned char)INTEL_ID_28F128J3A:
167   - info->flash_id += FLASH_28F128J3A;
168   - info->sector_count = 128;
169   - info->size = 0x01000000;
170   - break; /* => 16 MB */
171   -
172   - default:
173   - info->flash_id = FLASH_UNKNOWN;
174   - break;
175   - }
176   -
177   - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
178   - printf ("** ERROR: sector count %d > max (%d) **\n",
179   - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
180   - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
181   - }
182   -
183   - addr[0] = 0xFF; /* restore read mode */
184   -
185   - return (info->size);
186   -}
187   -
188   -
189   -/*-----------------------------------------------------------------------
190   - */
191   -
192   -int flash_erase (flash_info_t * info, int s_first, int s_last)
193   -{
194   - int prot, sect;
195   - ulong type;
196   - int rcode = 0;
197   - ulong start;
198   -
199   - if ((s_first < 0) || (s_first > s_last)) {
200   - if (info->flash_id == FLASH_UNKNOWN) {
201   - printf ("- missing\n");
202   - } else {
203   - printf ("- no sectors to erase\n");
204   - }
205   - return 1;
206   - }
207   -
208   - type = (info->flash_id & FLASH_VENDMASK);
209   - if ((type != FLASH_MAN_INTEL)) {
210   - printf ("Can't erase unknown flash type %08lx - aborted\n",
211   - info->flash_id);
212   - return 1;
213   - }
214   -
215   - prot = 0;
216   - for (sect = s_first; sect <= s_last; ++sect) {
217   - if (info->protect[sect]) {
218   - prot++;
219   - }
220   - }
221   -
222   - if (prot)
223   - printf ("- Warning: %d protected sectors will not be erased!\n", prot);
224   - else
225   - printf ("\n");
226   -
227   - /* Disable interrupts which might cause a timeout here */
228   - disable_interrupts();
229   -
230   - /* Start erase on unprotected sectors */
231   - for (sect = s_first; sect <= s_last; sect++) {
232   - if (info->protect[sect] == 0) { /* not protected */
233   - volatile unsigned char *addr;
234   - unsigned char status;
235   -
236   - printf ("Erasing sector %2d ... ", sect);
237   -
238   - /* arm simple, non interrupt dependent timer */
239   - start = get_timer(0);
240   -
241   - addr = (volatile unsigned char *) (info->start[sect]);
242   - *addr = 0x50; /* clear status register */
243   - *addr = 0x20; /* erase setup */
244   - *addr = 0xD0; /* erase confirm */
245   -
246   - while (((status = *addr) & 0x80) != 0x80) {
247   - if (get_timer(start) >
248   - CONFIG_SYS_FLASH_ERASE_TOUT) {
249   - printf ("Timeout\n");
250   - *addr = 0xB0; /* suspend erase */
251   - *addr = 0xFF; /* reset to read mode */
252   - rcode = 1;
253   - break;
254   - }
255   - }
256   -
257   - *addr = 0x50; /* clear status register cmd */
258   - *addr = 0xFF; /* resest to read mode */
259   -
260   - printf (" done\n");
261   - }
262   - }
263   - return rcode;
264   -}
265   -
266   -/*-----------------------------------------------------------------------
267   - * Copy memory to flash, returns:
268   - * 0 - OK
269   - * 1 - write timeout
270   - * 2 - Flash not erased
271   - * 4 - Flash not identified
272   - */
273   -
274   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
275   -{
276   - ulong cp, wp;
277   - unsigned char data;
278   - int count, i, l, rc, port_width;
279   -
280   - if (info->flash_id == FLASH_UNKNOWN)
281   - return 4;
282   -
283   - wp = addr;
284   - port_width = 1;
285   -
286   - /*
287   - * handle unaligned start bytes
288   - */
289   - if ((l = addr - wp) != 0) {
290   - data = 0;
291   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
292   - data = (data << 8) | (*(uchar *) cp);
293   - }
294   - for (; i < port_width && cnt > 0; ++i) {
295   - data = (data << 8) | *src++;
296   - --cnt;
297   - ++cp;
298   - }
299   - for (; cnt == 0 && i < port_width; ++i, ++cp) {
300   - data = (data << 8) | (*(uchar *) cp);
301   - }
302   -
303   - if ((rc = write_data (info, wp, data)) != 0) {
304   - return (rc);
305   - }
306   - wp += port_width;
307   - }
308   -
309   - /*
310   - * handle word aligned part
311   - */
312   - count = 0;
313   - while (cnt >= port_width) {
314   - data = 0;
315   - for (i = 0; i < port_width; ++i) {
316   - data = (data << 8) | *src++;
317   - }
318   - if ((rc = write_data (info, wp, data)) != 0) {
319   - return (rc);
320   - }
321   - wp += port_width;
322   - cnt -= port_width;
323   - if (count++ > 0x800) {
324   - spin_wheel ();
325   - count = 0;
326   - }
327   - }
328   -
329   - if (cnt == 0) {
330   - return (0);
331   - }
332   -
333   - /*
334   - * handle unaligned tail bytes
335   - */
336   - data = 0;
337   - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
338   - data = (data << 8) | *src++;
339   - --cnt;
340   - }
341   - for (; i < port_width; ++i, ++cp) {
342   - data = (data << 8) | (*(uchar *) cp);
343   - }
344   -
345   - return (write_data (info, wp, data));
346   -}
347   -
348   -/*-----------------------------------------------------------------------
349   - * Write a word or halfword to Flash, returns:
350   - * 0 - OK
351   - * 1 - write timeout
352   - * 2 - Flash not erased
353   - */
354   -static int write_data (flash_info_t * info, ulong dest, unsigned char data)
355   -{
356   - volatile unsigned char *addr = (volatile unsigned char *) dest;
357   - ulong status;
358   - ulong start;
359   -
360   - /* Check if Flash is (sufficiently) erased */
361   - if ((*addr & data) != data) {
362   - printf ("not erased at %08lx (%lx)\n", (ulong) addr,
363   - (ulong) * addr);
364   - return (2);
365   - }
366   - /* Disable interrupts which might cause a timeout here */
367   - disable_interrupts();
368   -
369   - *addr = 0x40; /* write setup */
370   - *addr = data;
371   -
372   - /* arm simple, non interrupt dependent timer */
373   - start = get_timer(0);
374   -
375   - /* wait while polling the status register */
376   - while (((status = *addr) & 0x80) != 0x80) {
377   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
378   - *addr = 0xFF; /* restore read mode */
379   - return (1);
380   - }
381   - }
382   -
383   - *addr = 0xFF; /* restore read mode */
384   -
385   - return (0);
386   -}
387   -
388   -void inline spin_wheel (void)
389   -{
390   - static int p = 0;
391   - static char w[] = "\\/-";
392   -
393   - printf ("\010%c", w[p]);
394   - (++p == 3) ? (p = 0) : 0;
395   -}
board/cm41xx/Kconfig
View file @ a2f39e8
1   -if TARGET_CM41XX
2   -
3   -config SYS_BOARD
4   - default "cm41xx"
5   -
6   -config SYS_SOC
7   - default "ks8695"
8   -
9   -config SYS_CONFIG_NAME
10   - default "cm41xx"
11   -
12   -endif
board/cm41xx/MAINTAINERS
View file @ a2f39e8
1   -CM41XX BOARD
2   -#M: -
3   -S: Maintained
4   -F: board/cm41xx/
5   -F: include/configs/cm41xx.h
6   -F: configs/cm41xx_defconfig
board/cm41xx/Makefile
View file @ a2f39e8
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := cm41xx.o flash.o
board/cm41xx/cm41xx.c
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2005
3   - * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
4   - *
5   - * (C) Copyright 2002
6   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7   - *
8   - * (C) Copyright 2002
9   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10   - * Marius Groeger <mgroeger@sysgo.de>
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <asm/arch/platform.h>
17   -#include <netdev.h>
18   -
19   -DECLARE_GLOBAL_DATA_PTR;
20   -
21   -/* ------------------------------------------------------------------------- */
22   -
23   -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
24   -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
25   -
26   -/* ------------------------------------------------------------------------- */
27   -
28   -
29   -/*
30   - * Miscelaneous platform dependent initialisations
31   - */
32   -int env_flash_cmdline (void)
33   -{
34   - char *sp = (char *) 0x0201c020;
35   - char *ep;
36   - int len;
37   -
38   - /* Check if "erase" push button is depressed */
39   - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
40   - printf("### Entering network recovery mode...\n");
41   - setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
42   - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
43   - setenv("bootdelay", "2");
44   - return 0;
45   - }
46   -
47   - /* Check for flash based kernel boot args to use as default */
48   - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
49   - ;
50   -
51   - if ((len > 0) && (len <1024))
52   - setenv("bootargs", sp);
53   -
54   - return 0;
55   -}
56   -
57   -int board_late_init (void)
58   -{
59   - return 0;
60   -}
61   -
62   -int board_eth_init(bd_t *bis)
63   -{
64   - return ks8695_eth_initialize();
65   -}
66   -
67   -int board_init (void)
68   -{
69   - /* arch number of CM41xx */
70   - gd->bd->bi_arch_number = 672;
71   -
72   - /* adress of boot parameters */
73   - gd->bd->bi_boot_params = 0x00000100;
74   -
75   - /* power down all but port 0 on the switch */
76   - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
77   - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
78   -
79   - return 0;
80   -}
81   -
82   -int dram_init (void)
83   -{
84   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
85   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
86   -
87   - return (0);
88   -}
board/cm41xx/config.mk
View file @ a2f39e8
1   -CONFIG_SYS_TEXT_BASE = 0x00f00000
board/cm41xx/flash.c
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2005
3   - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
4   - *
5   - * (C) Copyright 2001
6   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7   - *
8   - * (C) Copyright 2001
9   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <linux/byteorder/swab.h>
16   -#include <asm/sections.h>
17   -
18   -
19   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
20   -
21   -#define mb() __asm__ __volatile__ ("" : : : "memory")
22   -
23   -/*-----------------------------------------------------------------------
24   - * Functions
25   - */
26   -static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
27   -static int write_data (flash_info_t * info, ulong dest, unsigned char data);
28   -static void flash_get_offsets (ulong base, flash_info_t * info);
29   -void inline spin_wheel (void);
30   -
31   -/*-----------------------------------------------------------------------
32   - */
33   -
34   -unsigned long flash_init (void)
35   -{
36   - int i;
37   - ulong size = 0;
38   -
39   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
40   - switch (i) {
41   - case 0:
42   - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
43   - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
44   - break;
45   - case 1:
46   - /* ignore for now */
47   - flash_info[i].flash_id = FLASH_UNKNOWN;
48   - break;
49   - default:
50   - panic ("configured too many flash banks!\n");
51   - break;
52   - }
53   - size += flash_info[i].size;
54   - }
55   -
56   - /* Protect monitor and environment sectors
57   - */
58   - flash_protect (FLAG_PROTECT_SET,
59   - CONFIG_SYS_FLASH_BASE,
60   - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
61   - &flash_info[0]);
62   -
63   - return size;
64   -}
65   -
66   -/*-----------------------------------------------------------------------
67   - */
68   -static void flash_get_offsets (ulong base, flash_info_t * info)
69   -{
70   - int i;
71   -
72   - if (info->flash_id == FLASH_UNKNOWN)
73   - return;
74   -
75   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
76   - for (i = 0; i < info->sector_count; i++) {
77   - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
78   - info->protect[i] = 0;
79   - }
80   - }
81   -}
82   -
83   -/*-----------------------------------------------------------------------
84   - */
85   -void flash_print_info (flash_info_t * info)
86   -{
87   - int i;
88   -
89   - if (info->flash_id == FLASH_UNKNOWN) {
90   - printf ("missing or unknown FLASH type\n");
91   - return;
92   - }
93   -
94   - switch (info->flash_id & FLASH_VENDMASK) {
95   - case FLASH_MAN_INTEL:
96   - printf ("INTEL ");
97   - break;
98   - default:
99   - printf ("Unknown Vendor ");
100   - break;
101   - }
102   -
103   - switch (info->flash_id & FLASH_TYPEMASK) {
104   - case FLASH_28F128J3A:
105   - printf ("28F128J3A\n");
106   - break;
107   - default:
108   - printf ("Unknown Chip Type\n");
109   - break;
110   - }
111   -
112   - printf (" Size: %ld MB in %d Sectors\n",
113   - info->size >> 20, info->sector_count);
114   -
115   - printf (" Sector Start Addresses:");
116   - for (i = 0; i < info->sector_count; ++i) {
117   - if ((i % 5) == 0)
118   - printf ("\n ");
119   - printf (" %08lX%s",
120   - info->start[i], info->protect[i] ? " (RO)" : " ");
121   - }
122   - printf ("\n");
123   - return;
124   -}
125   -
126   -/*
127   - * The following code cannot be run from FLASH!
128   - */
129   -static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
130   -{
131   - volatile unsigned char value;
132   -
133   - /* Write auto select command: read Manufacturer ID */
134   - addr[0x5555] = 0xAA;
135   - addr[0x2AAA] = 0x55;
136   - addr[0x5555] = 0x90;
137   -
138   - mb ();
139   - value = addr[0];
140   -
141   - switch (value) {
142   -
143   - case (unsigned char)INTEL_MANUFACT:
144   - info->flash_id = FLASH_MAN_INTEL;
145   - break;
146   -
147   - default:
148   - info->flash_id = FLASH_UNKNOWN;
149   - info->sector_count = 0;
150   - info->size = 0;
151   - addr[0] = 0xFF; /* restore read mode */
152   - return (0); /* no or unknown flash */
153   - }
154   -
155   - mb ();
156   - value = addr[2]; /* device ID */
157   -
158   - switch (value) {
159   -
160   - case (unsigned char)INTEL_ID_28F640J3A:
161   - info->flash_id += FLASH_28F640J3A;
162   - info->sector_count = 64;
163   - info->size = 0x00800000;
164   - break; /* => 8 MB */
165   -
166   - case (unsigned char)INTEL_ID_28F128J3A:
167   - info->flash_id += FLASH_28F128J3A;
168   - info->sector_count = 128;
169   - info->size = 0x01000000;
170   - break; /* => 16 MB */
171   -
172   - default:
173   - info->flash_id = FLASH_UNKNOWN;
174   - break;
175   - }
176   -
177   - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
178   - printf ("** ERROR: sector count %d > max (%d) **\n",
179   - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
180   - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
181   - }
182   -
183   - addr[0] = 0xFF; /* restore read mode */
184   -
185   - return (info->size);
186   -}
187   -
188   -
189   -/*-----------------------------------------------------------------------
190   - */
191   -
192   -int flash_erase (flash_info_t * info, int s_first, int s_last)
193   -{
194   - int prot, sect;
195   - ulong type;
196   - int rcode = 0;
197   - ulong start;
198   -
199   - if ((s_first < 0) || (s_first > s_last)) {
200   - if (info->flash_id == FLASH_UNKNOWN) {
201   - printf ("- missing\n");
202   - } else {
203   - printf ("- no sectors to erase\n");
204   - }
205   - return 1;
206   - }
207   -
208   - type = (info->flash_id & FLASH_VENDMASK);
209   - if ((type != FLASH_MAN_INTEL)) {
210   - printf ("Can't erase unknown flash type %08lx - aborted\n",
211   - info->flash_id);
212   - return 1;
213   - }
214   -
215   - prot = 0;
216   - for (sect = s_first; sect <= s_last; ++sect) {
217   - if (info->protect[sect]) {
218   - prot++;
219   - }
220   - }
221   -
222   - if (prot)
223   - printf ("- Warning: %d protected sectors will not be erased!\n", prot);
224   - else
225   - printf ("\n");
226   -
227   - /* Disable interrupts which might cause a timeout here */
228   - disable_interrupts();
229   -
230   - /* Start erase on unprotected sectors */
231   - for (sect = s_first; sect <= s_last; sect++) {
232   - if (info->protect[sect] == 0) { /* not protected */
233   - volatile unsigned char *addr;
234   - unsigned char status;
235   -
236   - printf ("Erasing sector %2d ... ", sect);
237   -
238   - /* arm simple, non interrupt dependent timer */
239   - start = get_timer(0);
240   -
241   - addr = (volatile unsigned char *) (info->start[sect]);
242   - *addr = 0x50; /* clear status register */
243   - *addr = 0x20; /* erase setup */
244   - *addr = 0xD0; /* erase confirm */
245   -
246   - while (((status = *addr) & 0x80) != 0x80) {
247   - if (get_timer(start) >
248   - CONFIG_SYS_FLASH_ERASE_TOUT) {
249   - printf ("Timeout\n");
250   - *addr = 0xB0; /* suspend erase */
251   - *addr = 0xFF; /* reset to read mode */
252   - rcode = 1;
253   - break;
254   - }
255   - }
256   -
257   - *addr = 0x50; /* clear status register cmd */
258   - *addr = 0xFF; /* resest to read mode */
259   -
260   - printf (" done\n");
261   - }
262   - }
263   - return rcode;
264   -}
265   -
266   -/*-----------------------------------------------------------------------
267   - * Copy memory to flash, returns:
268   - * 0 - OK
269   - * 1 - write timeout
270   - * 2 - Flash not erased
271   - * 4 - Flash not identified
272   - */
273   -
274   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
275   -{
276   - ulong cp, wp;
277   - unsigned char data;
278   - int count, i, l, rc, port_width;
279   -
280   - if (info->flash_id == FLASH_UNKNOWN)
281   - return 4;
282   -
283   - wp = addr;
284   - port_width = 1;
285   -
286   - /*
287   - * handle unaligned start bytes
288   - */
289   - if ((l = addr - wp) != 0) {
290   - data = 0;
291   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
292   - data = (data << 8) | (*(uchar *) cp);
293   - }
294   - for (; i < port_width && cnt > 0; ++i) {
295   - data = (data << 8) | *src++;
296   - --cnt;
297   - ++cp;
298   - }
299   - for (; cnt == 0 && i < port_width; ++i, ++cp) {
300   - data = (data << 8) | (*(uchar *) cp);
301   - }
302   -
303   - if ((rc = write_data (info, wp, data)) != 0) {
304   - return (rc);
305   - }
306   - wp += port_width;
307   - }
308   -
309   - /*
310   - * handle word aligned part
311   - */
312   - count = 0;
313   - while (cnt >= port_width) {
314   - data = 0;
315   - for (i = 0; i < port_width; ++i) {
316   - data = (data << 8) | *src++;
317   - }
318   - if ((rc = write_data (info, wp, data)) != 0) {
319   - return (rc);
320   - }
321   - wp += port_width;
322   - cnt -= port_width;
323   - if (count++ > 0x800) {
324   - spin_wheel ();
325   - count = 0;
326   - }
327   - }
328   -
329   - if (cnt == 0) {
330   - return (0);
331   - }
332   -
333   - /*
334   - * handle unaligned tail bytes
335   - */
336   - data = 0;
337   - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
338   - data = (data << 8) | *src++;
339   - --cnt;
340   - }
341   - for (; i < port_width; ++i, ++cp) {
342   - data = (data << 8) | (*(uchar *) cp);
343   - }
344   -
345   - return (write_data (info, wp, data));
346   -}
347   -
348   -/*-----------------------------------------------------------------------
349   - * Write a word or halfword to Flash, returns:
350   - * 0 - OK
351   - * 1 - write timeout
352   - * 2 - Flash not erased
353   - */
354   -static int write_data (flash_info_t * info, ulong dest, unsigned char data)
355   -{
356   - volatile unsigned char *addr = (volatile unsigned char *) dest;
357   - ulong status;
358   - ulong start;
359   -
360   - /* Check if Flash is (sufficiently) erased */
361   - if ((*addr & data) != data) {
362   - printf ("not erased at %08lx (%lx)\n", (ulong) addr,
363   - (ulong) * addr);
364   - return (2);
365   - }
366   - /* Disable interrupts which might cause a timeout here */
367   - disable_interrupts();
368   -
369   - *addr = 0x40; /* write setup */
370   - *addr = data;
371   -
372   - /* arm simple, non interrupt dependent timer */
373   - start = get_timer(0);
374   -
375   - /* wait while polling the status register */
376   - while (((status = *addr) & 0x80) != 0x80) {
377   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
378   - *addr = 0xFF; /* restore read mode */
379   - return (1);
380   - }
381   - }
382   -
383   - *addr = 0xFF; /* restore read mode */
384   -
385   - return (0);
386   -}
387   -
388   -void inline spin_wheel (void)
389   -{
390   - static int p = 0;
391   - static char w[] = "\\/-";
392   -
393   - printf ("\010%c", w[p]);
394   - (++p == 3) ? (p = 0) : 0;
395   -}
configs/cm4008_defconfig
View file @ a2f39e8
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_CM4008=y
configs/cm41xx_defconfig
View file @ a2f39e8
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_CM41XX=y
doc/README.scrapyard
Diff comments   View file @ a2f39e8
... ... @@ -12,6 +12,8 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
  16 +cm41xx arm arm920t - -
15 17 dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
16 18 jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
17 19 icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
drivers/net/Makefile
Diff comments   View file @ a2f39e8
... ... @@ -33,7 +33,6 @@
33 33 obj-$(CONFIG_FTMAC100) += ftmac100.o
34 34 obj-$(CONFIG_GRETH) += greth.o
35 35 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
36   -obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
37 36 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
38 37 obj-$(CONFIG_LAN91C96) += lan91c96.o
39 38 obj-$(CONFIG_MACB) += macb.o
drivers/net/ks8695eth.c
View file @ a2f39e8
1   -/*
2   - * ks8695eth.c -- KS8695 ethernet driver
3   - *
4   - * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -/****************************************************************************/
10   -
11   -#include <common.h>
12   -#include <malloc.h>
13   -#include <net.h>
14   -#include <asm/io.h>
15   -#include <asm/arch/platform.h>
16   -
17   -/****************************************************************************/
18   -
19   -/*
20   - * Hardware register access to the KS8695 LAN ethernet port
21   - * (well, it is the 4 port switch really).
22   - */
23   -#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
24   -#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
25   -
26   -/****************************************************************************/
27   -
28   -/*
29   - * Define the descriptor in-memory data structures.
30   - */
31   -struct ks8695_txdesc {
32   - uint32_t owner;
33   - uint32_t ctrl;
34   - uint32_t addr;
35   - uint32_t next;
36   -};
37   -
38   -struct ks8695_rxdesc {
39   - uint32_t status;
40   - uint32_t ctrl;
41   - uint32_t addr;
42   - uint32_t next;
43   -};
44   -
45   -/****************************************************************************/
46   -
47   -/*
48   - * Allocate local data structures to use for receiving and sending
49   - * packets. Just to keep it all nice and simple.
50   - */
51   -
52   -#define TXDESCS 4
53   -#define RXDESCS 4
54   -#define BUFSIZE 2048
55   -
56   -volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
57   -volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
58   -volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
59   -
60   -/****************************************************************************/
61   -
62   -/*
63   - * Ideally we want to use the MAC address stored in flash.
64   - * But we do some sanity checks in case they are not present
65   - * first.
66   - */
67   -unsigned char eth_mac[] = {
68   - 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
69   -};
70   -
71   -void ks8695_getmac(void)
72   -{
73   - unsigned char *fp;
74   - int i;
75   -
76   - /* Check if flash MAC is valid */
77   - fp = (unsigned char *) 0x0201c000;
78   - for (i = 0; (i < 6); i++) {
79   - if ((fp[i] != 0) && (fp[i] != 0xff))
80   - break;
81   - }
82   -
83   - /* If we found a valid looking MAC address then use it */
84   - if (i < 6)
85   - memcpy(&eth_mac[0], fp, 6);
86   -}
87   -
88   -/****************************************************************************/
89   -
90   -static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
91   -{
92   - int i;
93   -
94   - debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
95   -
96   - /* Reset the ethernet engines first */
97   - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
98   - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
99   -
100   - ks8695_getmac();
101   -
102   - /* Set MAC address */
103   - ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
104   - (eth_mac[3] << 16) | (eth_mac[2] << 24)));
105   - ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
106   -
107   - /* Turn the 4 port switch on */
108   - i = ks8695_read(KS8695_SWITCH_CTRL0);
109   - ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
110   - /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
111   -
112   - /* Initialize descriptor rings */
113   - for (i = 0; (i < TXDESCS); i++) {
114   - ks8695_tx[i].owner = 0;
115   - ks8695_tx[i].ctrl = 0;
116   - ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
117   - ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
118   - }
119   - ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
120   - ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
121   -
122   - for (i = 0; (i < RXDESCS); i++) {
123   - ks8695_rx[i].status = 0x80000000;
124   - ks8695_rx[i].ctrl = BUFSIZE - 4;
125   - ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
126   - ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
127   - }
128   - ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
129   - ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
130   -
131   - /* The KS8695 is pretty slow reseting the ethernets... */
132   - udelay(2000000);
133   -
134   - /* Enable the ethernet engine */
135   - ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
136   - ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
137   - ks8695_write(KS8695_LAN_DMA_TX, 0x3);
138   - ks8695_write(KS8695_LAN_DMA_RX, 0x71);
139   - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
140   -
141   - printf("KS8695 ETHERNET: %pM\n", eth_mac);
142   - return 0;
143   -}
144   -
145   -/****************************************************************************/
146   -
147   -static void ks8695_eth_halt(struct eth_device *dev)
148   -{
149   - debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
150   -
151   - /* Reset the ethernet engines */
152   - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
153   - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
154   -}
155   -
156   -/****************************************************************************/
157   -
158   -static int ks8695_eth_recv(struct eth_device *dev)
159   -{
160   - volatile struct ks8695_rxdesc *dp;
161   - int i, len = 0;
162   -
163   - debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
164   -
165   - for (i = 0; (i < RXDESCS); i++) {
166   - dp= &ks8695_rx[i];
167   - if ((dp->status & 0x80000000) == 0) {
168   - len = (dp->status & 0x7ff) - 4;
169   - NetReceive((void *) dp->addr, len);
170   - dp->status = 0x80000000;
171   - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
172   - break;
173   - }
174   - }
175   -
176   - return len;
177   -}
178   -
179   -/****************************************************************************/
180   -
181   -static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
182   -{
183   - volatile struct ks8695_txdesc *dp;
184   - static int next = 0;
185   -
186   - debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
187   - packet, len);
188   -
189   - dp = &ks8695_tx[next];
190   - memcpy((void *) dp->addr, (void *) packet, len);
191   -
192   - if (len < 64) {
193   - memset((void *) (dp->addr + len), 0, 64-len);
194   - len = 64;
195   - }
196   -
197   - dp->ctrl = len | 0xe0000000;
198   - dp->owner = 0x80000000;
199   -
200   - ks8695_write(KS8695_LAN_DMA_TX, 0x3);
201   - ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
202   -
203   - if (++next >= TXDESCS)
204   - next = 0;
205   -
206   - return 0;
207   -}
208   -
209   -/****************************************************************************/
210   -
211   -int ks8695_eth_initialize(void)
212   -{
213   - struct eth_device *dev;
214   -
215   - dev = malloc(sizeof(*dev));
216   - if (dev == NULL)
217   - return -1;
218   - memset(dev, 0, sizeof(*dev));
219   -
220   - dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
221   - dev->init = ks8695_eth_init;
222   - dev->halt = ks8695_eth_halt;
223   - dev->send = ks8695_eth_send;
224   - dev->recv = ks8695_eth_recv;
225   - strcpy(dev->name, "ks8695eth");
226   -
227   - eth_register(dev);
228   - return 0;
229   -}
drivers/serial/Makefile
Diff comments   View file @ a2f39e8
... ... @@ -27,7 +27,6 @@
27 27 obj-$(CONFIG_SYS_NS16550) += ns16550.o
28 28 obj-$(CONFIG_S5P) += serial_s5p.o
29 29 obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
30   -obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
31 30 obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
32 31 obj-$(CONFIG_MXC_UART) += serial_mxc.o
33 32 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
drivers/serial/serial.c
Diff comments   View file @ a2f39e8
... ... @@ -127,7 +127,6 @@
127 127 serial_initfunc(imx_serial_initialize);
128 128 serial_initfunc(iop480_serial_initialize);
129 129 serial_initfunc(jz_serial_initialize);
130   -serial_initfunc(ks8695_serial_initialize);
131 130 serial_initfunc(leon2_serial_initialize);
132 131 serial_initfunc(leon3_serial_initialize);
133 132 serial_initfunc(lh7a40x_serial_initialize);
... ... @@ -220,7 +219,6 @@
220 219 imx_serial_initialize();
221 220 iop480_serial_initialize();
222 221 jz_serial_initialize();
223   - ks8695_serial_initialize();
224 222 leon2_serial_initialize();
225 223 leon3_serial_initialize();
226 224 lh7a40x_serial_initialize();
drivers/serial/serial_ks8695.c
View file @ a2f39e8
1   -/*
2   - * serial.c -- KS8695 serial driver
3   - *
4   - * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#include <common.h>
10   -#include <asm/arch/platform.h>
11   -#include <serial.h>
12   -#include <linux/compiler.h>
13   -
14   -#ifndef CONFIG_SERIAL1
15   -#error "Bad: you didn't configure serial ..."
16   -#endif
17   -
18   -DECLARE_GLOBAL_DATA_PTR;
19   -
20   -/*
21   - * Define the UART hardware register access structure.
22   - */
23   -struct ks8695uart {
24   - unsigned int RX; /* 0x00 - Receive data (r) */
25   - unsigned int TX; /* 0x04 - Transmit data (w) */
26   - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
27   - unsigned int LCR; /* 0x0c - Line Control (r/w) */
28   - unsigned int MCR; /* 0x10 - Modem Control (r/w) */
29   - unsigned int LSR; /* 0x14 - Line Status (r/w) */
30   - unsigned int MSR; /* 0x18 - Modem Status (r/w) */
31   - unsigned int BD; /* 0x1c - Baud Rate (r/w) */
32   - unsigned int SR; /* 0x20 - Status (r/w) */
33   -};
34   -
35   -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
36   -#define KS8695_UART_CLK 25000000
37   -
38   -
39   -/*
40   - * Under some circumstances we want to be "quiet" and not issue any
41   - * serial output - though we want u-boot to otherwise work and behave
42   - * the same. By default be noisy.
43   - */
44   -int serial_console = 1;
45   -
46   -
47   -static void ks8695_serial_setbrg(void)
48   -{
49   - volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
50   -
51   - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
52   - uartp->BD = KS8695_UART_CLK / gd->baudrate;
53   - uartp->LCR = KS8695_UART_LINEC_WLEN8;
54   -}
55   -
56   -static int ks8695_serial_init(void)
57   -{
58   - serial_console = 1;
59   - serial_setbrg();
60   - return 0;
61   -}
62   -
63   -static void ks8695_serial_raw_putc(const char c)
64   -{
65   - volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
66   - int i;
67   -
68   - for (i = 0; (i < 0x100000); i++) {
69   - if (uartp->LSR & KS8695_UART_LINES_TXFE)
70   - break;
71   - }
72   -
73   - uartp->TX = c;
74   -}
75   -
76   -static void ks8695_serial_putc(const char c)
77   -{
78   - if (serial_console) {
79   - ks8695_serial_raw_putc(c);
80   - if (c == '\n')
81   - ks8695_serial_raw_putc('\r');
82   - }
83   -}
84   -
85   -static int ks8695_serial_tstc(void)
86   -{
87   - volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
88   - if (serial_console)
89   - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
90   - return 0;
91   -}
92   -
93   -static int ks8695_serial_getc(void)
94   -{
95   - volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
96   -
97   - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
98   - ;
99   - return (uartp->RX);
100   -}
101   -
102   -static struct serial_device ks8695_serial_drv = {
103   - .name = "ks8695_serial",
104   - .start = ks8695_serial_init,
105   - .stop = NULL,
106   - .setbrg = ks8695_serial_setbrg,
107   - .putc = ks8695_serial_putc,
108   - .puts = default_serial_puts,
109   - .getc = ks8695_serial_getc,
110   - .tstc = ks8695_serial_tstc,
111   -};
112   -
113   -void ks8695_serial_initialize(void)
114   -{
115   - serial_register(&ks8695_serial_drv);
116   -}
117   -
118   -__weak struct serial_device *default_serial_console(void)
119   -{
120   - return &ks8695_serial_drv;
121   -}
include/configs/cm4008.h
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2004
3   - * Greg Ungerer <greg.ungerer@opengear.com>.
4   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -#ifndef __CONFIG_H
9   -#define __CONFIG_H
10   -
11   -/*
12   - * High Level Configuration Options
13   - * (easy to change)
14   - */
15   -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
16   -#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
17   -
18   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
19   -#define CONFIG_SETUP_MEMORY_TAGS 1
20   -#define CONFIG_INITRD_TAG 1
21   -
22   -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
23   -
24   -/*
25   - * Size of malloc() pool
26   - */
27   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
28   -
29   -/*
30   - * Hardware drivers
31   - */
32   -
33   -/*
34   - * select serial console configuration
35   - */
36   -#define CONFIG_ENV_IS_NOWHERE
37   -#define CONFIG_KS8695_SERIAL
38   -#define CONFIG_SERIAL1
39   -#define CONFIG_CONS_INDEX 1
40   -#define CONFIG_BAUDRATE 115200
41   -
42   -/*
43   - * BOOTP options
44   - */
45   -#define CONFIG_BOOTP_BOOTFILESIZE
46   -#define CONFIG_BOOTP_BOOTPATH
47   -#define CONFIG_BOOTP_GATEWAY
48   -#define CONFIG_BOOTP_HOSTNAME
49   -
50   -
51   -/*
52   - * Command line configuration.
53   - */
54   -#include <config_cmd_default.h>
55   -
56   -#undef CONFIG_CMD_SAVEENV
57   -
58   -
59   -#define CONFIG_BOOTDELAY 0
60   -#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
61   -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
62   -
63   -/*
64   - * Miscellaneous configurable options
65   - */
66   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
67   -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
68   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
69   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
70   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
71   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
72   -
73   -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
74   -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
75   -
76   -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
77   -
78   -/*-----------------------------------------------------------------------
79   - * Physical Memory Map
80   - */
81   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
82   -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
83   -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
84   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
85   -
86   -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
87   -
88   -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
89   -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
90   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
91   -
92   -/*-----------------------------------------------------------------------
93   - * FLASH and environment organization
94   - */
95   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
96   -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
97   -
98   -/* timeout values are in ticks */
99   -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
100   -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
101   -
102   -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
103   -
104   -#endif /* __CONFIG_H */
include/configs/cm41xx.h
View file @ a2f39e8
1   -/*
2   - * (C) Copyright 2005
3   - * Greg Ungerer <greg.ungerer@opengear.com>.
4   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -#ifndef __CONFIG_H
9   -#define __CONFIG_H
10   -
11   -/*
12   - * High Level Configuration Options
13   - * (easy to change)
14   - */
15   -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
16   -#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
17   -
18   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
19   -#define CONFIG_SETUP_MEMORY_TAGS 1
20   -#define CONFIG_INITRD_TAG 1
21   -
22   -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
23   -
24   -/*
25   - * Size of malloc() pool
26   - */
27   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
28   -
29   -/*
30   - * Hardware drivers
31   - */
32   -
33   -/*
34   - * select serial console configuration
35   - */
36   -#define CONFIG_ENV_IS_NOWHERE
37   -#define CONFIG_KS8695_SERIAL
38   -#define CONFIG_SERIAL1
39   -#define CONFIG_CONS_INDEX 1
40   -#define CONFIG_BAUDRATE 115200
41   -
42   -/*
43   - * BOOTP options
44   - */
45   -#define CONFIG_BOOTP_BOOTFILESIZE
46   -#define CONFIG_BOOTP_BOOTPATH
47   -#define CONFIG_BOOTP_GATEWAY
48   -#define CONFIG_BOOTP_HOSTNAME
49   -
50   -
51   -/*
52   - * Command line configuration.
53   - */
54   -#include <config_cmd_default.h>
55   -
56   -#undef CONFIG_CMD_SAVEENV
57   -
58   -
59   -#define CONFIG_BOOTDELAY 0
60   -#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
61   -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
62   -
63   -/*
64   - * Miscellaneous configurable options
65   - */
66   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
67   -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
68   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
69   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
70   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
71   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
72   -
73   -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
74   -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
75   -
76   -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
77   -
78   -/*-----------------------------------------------------------------------
79   - * Physical Memory Map
80   - */
81   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
82   -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
83   -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
84   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
85   -
86   -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
87   -
88   -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
89   -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
90   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
91   -
92   -/*-----------------------------------------------------------------------
93   - * FLASH and environment organization
94   - */
95   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
96   -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
97   -
98   -/* timeout values are in ticks */
99   -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
100   -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
101   -
102   -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
103   -
104   -#endif /* __CONFIG_H */
... ... @@ -55,7 +55,6 @@
55 55 int ftmac110_initialize(bd_t *bits);
56 56 int greth_initialize(bd_t *bis);
57 57 void gt6426x_eth_initialize(bd_t *bis);
58   -int ks8695_eth_initialize(void);
59 58 int ks8851_mll_initialize(u8 dev_num, int base_addr);
60 59 int lan91c96_initialize(u8 dev_num, int base_addr);
61 60 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
... ... @@ -182,7 +182,6 @@
182 182 void imx_serial_initialize(void);
183 183 void iop480_serial_initialize(void);
184 184 void jz_serial_initialize(void);
185   -void ks8695_serial_initialize(void);
186 185 void leon2_serial_initialize(void);
187 186 void leon3_serial_initialize(void);
188 187 void lh7a40x_serial_initialize(void);