Eric Lee / smarc-uboot

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Commit a321148b5b38150b011a1df4ad198329a49e98a3

Authored by Stefan Roese
1 parent f7b548adb5
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Update lwmon5 board support 

This patch includes the following changes for the lwmon5 board support:

- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
  This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
  (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 2 changed files with 32 additions and 12 deletions Side-by-side Diff

board/lwmon5/sdram.c
Diff comments   View file @ a321148
... ... @@ -45,10 +45,10 @@
45 45 * memory.
46 46 *
47 47 * If at some time this restriction doesn't apply anymore, just define
48   - * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  48 + * CONFIG_4xx_DCACHE in the board config file and this code should setup
49 49 * everything correctly.
50 50 */
51   -#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
  51 +#ifdef CONFIG_4xx_DCACHE
52 52 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
53 53 #else
54 54 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
55 55  
56 56  
57 57  
... ... @@ -220,18 +220,32 @@
220 220 program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
221 221 MY_TLB_WORD2_I_ENABLE);
222 222  
  223 +#if defined(CONFIG_DDR_ECC)
  224 +#if defined(CONFIG_4xx_DCACHE)
223 225 /*
  226 + * If ECC is enabled, initialize the parity bits.
  227 + */
  228 + program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
  229 +#else /* CONFIG_4xx_DCACHE */
  230 + /*
224 231 * Setup 2nd TLB with same physical address but different virtual address
225 232 * with cache enabled. This is done for fast ECC generation.
226 233 */
227 234 program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
228 235  
229   -#ifdef CONFIG_DDR_ECC
230 236 /*
231 237 * If ECC is enabled, initialize the parity bits.
232 238 */
233 239 program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
234   -#endif
  240 +
  241 + /*
  242 + * Now after initialization (auto-calibration and ECC generation)
  243 + * remove the TLB entries with caches enabled and program again with
  244 + * desired cache functionality
  245 + */
  246 + remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
  247 +#endif /* CONFIG_4xx_DCACHE */
  248 +#endif /* CONFIG_DDR_ECC */
235 249  
236 250 /*
237 251 * Clear possible errors resulting from data-eye-search.
include/configs/lwmon5.h
Diff comments   View file @ a321148
... ... @@ -43,6 +43,8 @@
43 43  
44 44 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
45 45  
  46 +#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
  47 +
46 48 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
47 49 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
48 50 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
... ... @@ -321,6 +323,8 @@
321 323 /* Update size in "reg" property of NOR FLASH device tree nodes */
322 324 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
323 325  
  326 +#define CONFIG_FIT /* enable FIT image support */
  327 +
324 328 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
325 329  
326 330 #define CONFIG_PREBOOT "setenv bootdelay 15"
327 331  
... ... @@ -393,15 +397,17 @@
393 397 #define CONFIG_VIDEO_SW_CURSOR
394 398 #define CONFIG_SPLASH_SCREEN
395 399  
396   -/* USB */
397   -#ifdef CONFIG_440EPX
398   -#define CONFIG_USB_OHCI
  400 +/*
  401 + * USB/EHCI
  402 + */
  403 +#define CONFIG_USB_EHCI /* Enable EHCI USB support */
  404 +#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
  405 +#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
  406 +#define CONFIG_EHCI_DCACHE /* with dcache handling support */
  407 +#define CONFIG_EHCI_MMIO_BIG_ENDIAN
  408 +#define CONFIG_EHCI_DESC_BIG_ENDIAN
  409 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
399 410 #define CONFIG_USB_STORAGE
400   -
401   -/* Comment this out to enable USB 1.1 device */
402   -#define USB_2_0_DEVICE
403   -
404   -#endif /* CONFIG_440EPX */
405 411  
406 412 /* Partitions */
407 413 #define CONFIG_MAC_PARTITION