tsec: use IO accessors for IO accesses

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>

tsec: use IO accessors for IO accesses
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
Mingkai Hu · Andy Fleming
1 parent 73e5476e1e
Showing 2 changed files with 130 additions and 127 deletions Side-by-side Diff
drivers/net/tsec.c
include/tsec.h
@@ -5,7 +5,7 @@
  * terms of the GNU Public License, Version 2, incorporated
  * herein by reference.
  *
- * Copyright 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * author Andy Fleming
  *
@@ -50,7 +50,7 @@
 static int tsec_init(struct eth_device *dev, bd_t * bd);
 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
 static void tsec_halt(struct eth_device *dev);
-static void init_registers(volatile tsec_t * regs);
+static void init_registers(tsec_t *regs);
 static void startup_tsec(struct eth_device *dev);
 static int init_phy(struct eth_device *dev);
 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
  
@@ -166,9 +166,9 @@
 	eth_register(dev);
  
 	/* Reset the MAC */
-	priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
+	setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 	udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
-	priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+	clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 	&& !defined(BITBANGMII)
  
  
@@ -190,16 +190,16 @@
 	char tmpbuf[MAC_ADDR_LEN];
 	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
 	/* Make sure the controller is stopped */
 	tsec_halt(dev);
  
 	/* Init MACCFG2.  Defaults to GMII */
-	regs->maccfg2 = MACCFG2_INIT_SETTINGS;
+	out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  
 	/* Init ECNTRL */
-	regs->ecntrl = ECNTRL_INIT_SETTINGS;
+	out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  
 	/* Copy the station address into the address registers.
 	 * Backwards, because little endian MACS are dumb */
  
@@ -209,11 +209,11 @@
 	tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
 		  tmpbuf[3];
  
-	regs->macstnaddr1 = tempval;
+	out_be32(&regs->macstnaddr1, tempval);
  
 	tempval = *((uint *) (tmpbuf + 4));
  
-	regs->macstnaddr2 = tempval;
+	out_be32(&regs->macstnaddr2, tempval);
  
 	/* reset the indices to zero */
 	rxIdx = 0;
  
  
@@ -230,17 +230,17 @@
 }
  
 /* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
+static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
 		uint reg, uint value)
 {
 	int timeout = 1000000;
  
-	phyregs->miimadd = (addr << 8) | reg;
-	phyregs->miimcon = value;
-	asm("sync");
+	out_be32(&phyregs->miimadd, (addr << 8) | reg);
+	out_be32(&phyregs->miimcon, value);
  
 	timeout = 1000000;
-	while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
+	while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
+		;
 }
  
  
  
  
  
  
  
@@ -254,28 +254,26 @@
  * notvalid bit cleared), and the bus to cease activity (miimind
  * busy bit cleared), and then returns the value
  */
-static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
-				uint phyid, uint regnum)
+static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
 {
 	uint value;
  
 	/* Put the address of the phy, and the register
 	 * number into MIIMADD */
-	phyregs->miimadd = (phyid << 8) | regnum;
+	out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
  
 	/* Clear the command register, and wait */
-	phyregs->miimcom = 0;
-	asm("sync");
+	out_be32(&phyregs->miimcom, 0);
  
 	/* Initiate a read command, and wait */
-	phyregs->miimcom = MIIM_READ_COMMAND;
-	asm("sync");
+	out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
  
 	/* Wait for the the indication that the read is done */
-	while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
+	while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)))
+		;
  
 	/* Grab the value read from the PHY */
-	value = phyregs->miimstat;
+	value = in_be32(&phyregs->miimstat);
  
 	return value;
 }
  
  
@@ -321,18 +319,16 @@
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
 	struct phy_info *curphy;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
 	/* Assign a Physical address to the TBI */
-	regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
-	asm("sync");
+	out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  
 	/* Reset MII (due to new addresses) */
-	priv->phyregs->miimcfg = MIIMCFG_RESET;
-	asm("sync");
-	priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
-	asm("sync");
-	while (priv->phyregs->miimind & MIIMIND_BUSY) ;
+	out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
+	out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
+	while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
+		;
  
 	/* Get the cmd structure corresponding to the attached
 	 * PHY */
@@ -345,7 +341,7 @@
 		return 0;
 	}
  
-	if (regs->ecntrl & ECNTRL_SGMII_MODE)
+	if (in_be32(&regs->ecntrl) & ECNTRL_SGMII_MODE)
 		tsec_configure_serdes(priv);
  
 	priv->phyinfo = curphy;
  
  
@@ -838,16 +834,16 @@
 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 {
 	uint phyid;
-	volatile tsec_mdio_t *regbase = priv->phyregs;
+	tsec_mdio_t *regbase = priv->phyregs;
 	int timeout = 1000000;
  
 	for (phyid = 0; phyid < 4; phyid++) {
-		regbase->miimadd = (phyid << 8) | mii_reg;
-		regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
-		asm("sync");
+		out_be32(&regbase->miimadd, (phyid << 8) | mii_reg);
+		out_be32(&regbase->miimcon, MIIM_CIS8204_SLEDCON_INIT);
  
 		timeout = 1000000;
-		while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
+		while ((in_be32(&regbase->miimind) & MIIMIND_BUSY) && timeout--)
+			;
 	}
  
 	return MIIM_CIS8204_SLEDCON_INIT;
  
  
  
  
  
  
  
  
  
@@ -874,45 +870,45 @@
  * those we don't care about (unless zero is bad, in which case,
  * choose a more appropriate value)
  */
-static void init_registers(volatile tsec_t * regs)
+static void init_registers(tsec_t *regs)
 {
 	/* Clear IEVENT */
-	regs->ievent = IEVENT_INIT_CLEAR;
+	out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  
-	regs->imask = IMASK_INIT_CLEAR;
+	out_be32(&regs->imask, IMASK_INIT_CLEAR);
  
-	regs->hash.iaddr0 = 0;
-	regs->hash.iaddr1 = 0;
-	regs->hash.iaddr2 = 0;
-	regs->hash.iaddr3 = 0;
-	regs->hash.iaddr4 = 0;
-	regs->hash.iaddr5 = 0;
-	regs->hash.iaddr6 = 0;
-	regs->hash.iaddr7 = 0;
+	out_be32(&regs->hash.iaddr0, 0);
+	out_be32(&regs->hash.iaddr1, 0);
+	out_be32(&regs->hash.iaddr2, 0);
+	out_be32(&regs->hash.iaddr3, 0);
+	out_be32(&regs->hash.iaddr4, 0);
+	out_be32(&regs->hash.iaddr5, 0);
+	out_be32(&regs->hash.iaddr6, 0);
+	out_be32(&regs->hash.iaddr7, 0);
  
-	regs->hash.gaddr0 = 0;
-	regs->hash.gaddr1 = 0;
-	regs->hash.gaddr2 = 0;
-	regs->hash.gaddr3 = 0;
-	regs->hash.gaddr4 = 0;
-	regs->hash.gaddr5 = 0;
-	regs->hash.gaddr6 = 0;
-	regs->hash.gaddr7 = 0;
+	out_be32(&regs->hash.gaddr0, 0);
+	out_be32(&regs->hash.gaddr1, 0);
+	out_be32(&regs->hash.gaddr2, 0);
+	out_be32(&regs->hash.gaddr3, 0);
+	out_be32(&regs->hash.gaddr4, 0);
+	out_be32(&regs->hash.gaddr5, 0);
+	out_be32(&regs->hash.gaddr6, 0);
+	out_be32(&regs->hash.gaddr7, 0);
  
-	regs->rctrl = 0x00000000;
+	out_be32(&regs->rctrl, 0x00000000);
  
 	/* Init RMON mib registers */
 	memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
  
-	regs->rmon.cam1 = 0xffffffff;
-	regs->rmon.cam2 = 0xffffffff;
+	out_be32(&regs->rmon.cam1, 0xffffffff);
+	out_be32(&regs->rmon.cam2, 0xffffffff);
  
-	regs->mrblr = MRBLR_INIT_SETTINGS;
+	out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  
-	regs->minflr = MINFLR_INIT_SETTINGS;
+	out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  
-	regs->attr = ATTR_INIT_SETTINGS;
-	regs->attreli = ATTRELI_INIT_SETTINGS;
+	out_be32(&regs->attr, ATTR_INIT_SETTINGS);
+	out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  
 }
  
  
  
  
  
  
  
@@ -922,44 +918,49 @@
 static void adjust_link(struct eth_device *dev)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
+	u32 ecntrl, maccfg2;
  
-	if (priv->link) {
-		if (priv->duplexity != 0)
-			regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
-		else
-			regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
+	if (!priv->link) {
+		printf("%s: No link.\n", dev->name);
+		return;
+	}
  
-		switch (priv->speed) {
-		case 1000:
-			regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
-					 | MACCFG2_GMII);
-			break;
-		case 100:
-		case 10:
-			regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
-					 | MACCFG2_MII);
+	/* clear all bits relative with interface mode */
+	ecntrl = in_be32(&regs->ecntrl);
+	ecntrl &= ~ECNTRL_R100;
  
-			/* Set R100 bit in all modes although
-			 * it is only used in RGMII mode
-			 */
-			if (priv->speed == 100)
-				regs->ecntrl |= ECNTRL_R100;
-			else
-				regs->ecntrl &= ~(ECNTRL_R100);
-			break;
-		default:
-			printf("%s: Speed was bad\n", dev->name);
-			break;
-		}
+	maccfg2 = in_be32(&regs->maccfg2);
+	maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  
-		printf("Speed: %d, %s duplex%s\n", priv->speed,
-		       (priv->duplexity) ? "full" : "half",
-		       (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
+	if (priv->duplexity)
+		maccfg2 |= MACCFG2_FULL_DUPLEX;
  
-	} else {
-		printf("%s: No link.\n", dev->name);
+	switch (priv->speed) {
+	case 1000:
+		maccfg2 |= MACCFG2_GMII;
+		break;
+	case 100:
+	case 10:
+		maccfg2 |= MACCFG2_MII;
+
+		/* Set R100 bit in all modes although
+		 * it is only used in RGMII mode
+		 */
+		if (priv->speed == 100)
+			ecntrl |= ECNTRL_R100;
+		break;
+	default:
+		printf("%s: Speed was bad\n", dev->name);
+		break;
 	}
+
+	out_be32(&regs->ecntrl, ecntrl);
+	out_be32(&regs->maccfg2, maccfg2);
+
+	printf("Speed: %d, %s duplex%s\n", priv->speed,
+			(priv->duplexity) ? "full" : "half",
+			(priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
 }
  
 /* Set up the buffers and their descriptors, and bring up the
  
@@ -969,11 +970,11 @@
 {
 	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
 	/* Point to the buffer descriptors */
-	regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
-	regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
+	out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
+	out_be32(&regs->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
  
 	/* Initialize the Rx Buffer descriptors */
 	for (i = 0; i < PKTBUFSRX; i++) {
  
@@ -998,13 +999,13 @@
 	adjust_link(dev);
  
 	/* Enable Transmit and Receive */
-	regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
+	setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  
 	/* Tell the DMA it is clear to go */
-	regs->dmactrl |= DMACTRL_INIT_SETTINGS;
-	regs->tstat = TSTAT_CLEAR_THALT;
-	regs->rstat = RSTAT_CLEAR_RHALT;
-	regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
+	setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
+	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
+	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
+	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 }
  
 /* This returns the status bits of the device.	The return value
@@ -1017,7 +1018,7 @@
 	int i;
 	int result = 0;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
 	/* Find an empty buffer descriptor */
 	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
@@ -1033,7 +1034,7 @@
 	    (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
  
 	/* Tell the DMA to go */
-	regs->tstat = TSTAT_CLEAR_THALT;
+	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  
 	/* Wait for buffer to be transmitted */
 	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
@@ -1053,7 +1054,7 @@
 {
 	int length;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
 	while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
  
@@ -1076,9 +1077,9 @@
 		rxIdx = (rxIdx + 1) % PKTBUFSRX;
 	}
  
-	if (regs->ievent & IEVENT_BSY) {
-		regs->ievent = IEVENT_BSY;
-		regs->rstat = RSTAT_CLEAR_RHALT;
+	if (in_be32(&regs->ievent) & IEVENT_BSY) {
+		out_be32(&regs->ievent, IEVENT_BSY);
+		out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	}
  
 	return -1;
  
  
  
@@ -1089,15 +1090,16 @@
 static void tsec_halt(struct eth_device *dev)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	volatile tsec_t *regs = priv->regs;
+	tsec_t *regs = priv->regs;
  
-	regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
-	regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
+	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+	setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  
-	while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))
-		!= (IEVENT_GRSC | IEVENT_GTSC)) ;
+	while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
+			!= (IEVENT_GRSC | IEVENT_GTSC))
+		;
  
-	regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
+	clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  
 	/* Shut down the PHY, as needed */
 	if(priv->phyinfo)
  
  
  
@@ -1904,13 +1906,14 @@
 {
 	int i;
 	uint result;
-	volatile tsec_mdio_t *phyregs = priv->phyregs;
+	tsec_mdio_t *phyregs = priv->phyregs;
  
-	phyregs->miimcfg = MIIMCFG_RESET;
+	out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
  
-	phyregs->miimcfg = MIIMCFG_INIT_VALUE;
+	out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
  
-	while (phyregs->miimind & MIIMIND_BUSY) ;
+	while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
+		;
  
 	for (i = 0; cmd->mii_reg != miim_end; i++) {
 		if (cmd->mii_data == miim_read) {
@@ -7,7 +7,7 @@
  *  terms of the GNU Public License, Version 2, incorporated
  *  herein by reference.
  *
- * Copyright 2004, 2007, 2009  Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009, 2011  Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  * author Andy Fleming
@@ -587,9 +587,9 @@
 #define TSEC_FIBER	(1 << 3)	/* PHY uses fiber, eg 1000 Base-X */
  
 struct tsec_private {
-	volatile tsec_t *regs;
-	volatile tsec_mdio_t *phyregs;
-	volatile tsec_mdio_t *phyregs_sgmii;
+	tsec_t *regs;
+	tsec_mdio_t *phyregs;
+	tsec_mdio_t *phyregs_sgmii;
 	struct phy_info *phyinfo;
 	uint phyaddr;
 	u32 flags;
...	...	@@ -5,7 +5,7 @@
5	5	* terms of the GNU Public License, Version 2, incorporated
6	6	* herein by reference.
7	7	*
8		- * Copyright 2004-2010 Freescale Semiconductor, Inc.
	8	+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
9	9	* (C) Copyright 2003, Motorola, Inc.
10	10	* author Andy Fleming
11	11	*
...	...	@@ -50,7 +50,7 @@
50	50	static int tsec_init(struct eth_device dev, bd_t bd);
51	51	static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
52	52	static void tsec_halt(struct eth_device *dev);
53		-static void init_registers(volatile tsec_t * regs);
	53	+static void init_registers(tsec_t *regs);
54	54	static void startup_tsec(struct eth_device *dev);
55	55	static int init_phy(struct eth_device *dev);
56	56	void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
57	57
...	...	@@ -166,9 +166,9 @@
166	166	eth_register(dev);
167	167
168	168	/* Reset the MAC */
169		- priv->regs->maccfg1 \|= MACCFG1_SOFT_RESET;
	169	+ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
170	170	udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
171		- priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
	171	+ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
172	172
173	173	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \
174	174	&& !defined(BITBANGMII)
175	175
176	176
...	...	@@ -190,16 +190,16 @@
190	190	char tmpbuf[MAC_ADDR_LEN];
191	191	int i;
192	192	struct tsec_private priv = (struct tsec_private )dev->priv;
193		- volatile tsec_t *regs = priv->regs;
	193	+ tsec_t *regs = priv->regs;
194	194
195	195	/* Make sure the controller is stopped */
196	196	tsec_halt(dev);
197	197
198	198	/* Init MACCFG2. Defaults to GMII */
199		- regs->maccfg2 = MACCFG2_INIT_SETTINGS;
	199	+ out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
200	200
201	201	/* Init ECNTRL */
202		- regs->ecntrl = ECNTRL_INIT_SETTINGS;
	202	+ out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
203	203
204	204	/* Copy the station address into the address registers.
205	205	* Backwards, because little endian MACS are dumb */
206	206
...	...	@@ -209,11 +209,11 @@
209	209	tempval = (tmpbuf[0] << 24) \| (tmpbuf[1] << 16) \| (tmpbuf[2] << 8) \|
210	210	tmpbuf[3];
211	211
212		- regs->macstnaddr1 = tempval;
	212	+ out_be32(&regs->macstnaddr1, tempval);
213	213
214	214	tempval = ((uint ) (tmpbuf + 4));
215	215
216		- regs->macstnaddr2 = tempval;
	216	+ out_be32(&regs->macstnaddr2, tempval);
217	217
218	218	/* reset the indices to zero */
219	219	rxIdx = 0;
220	220
221	221
...	...	@@ -230,17 +230,17 @@
230	230	}
231	231
232	232	/* Writes the given phy's reg with value, using the specified MDIO regs */
233		-static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
	233	+static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
234	234	uint reg, uint value)
235	235	{
236	236	int timeout = 1000000;
237	237
238		- phyregs->miimadd = (addr << 8) \| reg;
239		- phyregs->miimcon = value;
240		- asm("sync");
	238	+ out_be32(&phyregs->miimadd, (addr << 8) \| reg);
	239	+ out_be32(&phyregs->miimcon, value);
241	240
242	241	timeout = 1000000;
243		- while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
	242	+ while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
	243	+ ;
244	244	}
245	245
246	246
247	247
248	248
249	249
250	250
251	251
...	...	@@ -254,28 +254,26 @@
254	254	* notvalid bit cleared), and the bus to cease activity (miimind
255	255	* busy bit cleared), and then returns the value
256	256	*/
257		-static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
258		- uint phyid, uint regnum)
	257	+static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
259	258	{
260	259	uint value;
261	260
262	261	/* Put the address of the phy, and the register
263	262	* number into MIIMADD */
264		- phyregs->miimadd = (phyid << 8) \| regnum;
	263	+ out_be32(&phyregs->miimadd, (phyid << 8) \| regnum);
265	264
266	265	/* Clear the command register, and wait */
267		- phyregs->miimcom = 0;
268		- asm("sync");
	266	+ out_be32(&phyregs->miimcom, 0);
269	267
270	268	/* Initiate a read command, and wait */
271		- phyregs->miimcom = MIIM_READ_COMMAND;
272		- asm("sync");
	269	+ out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
273	270
274	271	/* Wait for the the indication that the read is done */
275		- while ((phyregs->miimind & (MIIMIND_NOTVALID \| MIIMIND_BUSY))) ;
	272	+ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID \| MIIMIND_BUSY)))
	273	+ ;
276	274
277	275	/* Grab the value read from the PHY */
278		- value = phyregs->miimstat;
	276	+ value = in_be32(&phyregs->miimstat);
279	277
280	278	return value;
281	279	}
282	280
283	281
...	...	@@ -321,18 +319,16 @@
321	319	{
322	320	struct tsec_private priv = (struct tsec_private )dev->priv;
323	321	struct phy_info *curphy;
324		- volatile tsec_t *regs = priv->regs;
	322	+ tsec_t *regs = priv->regs;
325	323
326	324	/* Assign a Physical address to the TBI */
327		- regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
328		- asm("sync");
	325	+ out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
329	326
330	327	/* Reset MII (due to new addresses) */
331		- priv->phyregs->miimcfg = MIIMCFG_RESET;
332		- asm("sync");
333		- priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
334		- asm("sync");
335		- while (priv->phyregs->miimind & MIIMIND_BUSY) ;
	328	+ out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
	329	+ out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
	330	+ while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
	331	+ ;
336	332
337	333	/* Get the cmd structure corresponding to the attached
338	334	* PHY */
...	...	@@ -345,7 +341,7 @@
345	341	return 0;
346	342	}
347	343
348		- if (regs->ecntrl & ECNTRL_SGMII_MODE)
	344	+ if (in_be32(&regs->ecntrl) & ECNTRL_SGMII_MODE)
349	345	tsec_configure_serdes(priv);
350	346
351	347	priv->phyinfo = curphy;
352	348
353	349
...	...	@@ -838,16 +834,16 @@
838	834	static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
839	835	{
840	836	uint phyid;
841		- volatile tsec_mdio_t *regbase = priv->phyregs;
	837	+ tsec_mdio_t *regbase = priv->phyregs;
842	838	int timeout = 1000000;
843	839
844	840	for (phyid = 0; phyid < 4; phyid++) {
845		- regbase->miimadd = (phyid << 8) \| mii_reg;
846		- regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
847		- asm("sync");
	841	+ out_be32(&regbase->miimadd, (phyid << 8) \| mii_reg);
	842	+ out_be32(&regbase->miimcon, MIIM_CIS8204_SLEDCON_INIT);
848	843
849	844	timeout = 1000000;
850		- while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
	845	+ while ((in_be32(&regbase->miimind) & MIIMIND_BUSY) && timeout--)
	846	+ ;
851	847	}
852	848
853	849	return MIIM_CIS8204_SLEDCON_INIT;
854	850
855	851
856	852
857	853
858	854
859	855
860	856
861	857
862	858
...	...	@@ -874,45 +870,45 @@
874	870	* those we don't care about (unless zero is bad, in which case,
875	871	* choose a more appropriate value)
876	872	*/
877		-static void init_registers(volatile tsec_t * regs)
	873	+static void init_registers(tsec_t *regs)
878	874	{
879	875	/* Clear IEVENT */
880		- regs->ievent = IEVENT_INIT_CLEAR;
	876	+ out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
881	877
882		- regs->imask = IMASK_INIT_CLEAR;
	878	+ out_be32(&regs->imask, IMASK_INIT_CLEAR);
883	879
884		- regs->hash.iaddr0 = 0;
885		- regs->hash.iaddr1 = 0;
886		- regs->hash.iaddr2 = 0;
887		- regs->hash.iaddr3 = 0;
888		- regs->hash.iaddr4 = 0;
889		- regs->hash.iaddr5 = 0;
890		- regs->hash.iaddr6 = 0;
891		- regs->hash.iaddr7 = 0;
	880	+ out_be32(&regs->hash.iaddr0, 0);
	881	+ out_be32(&regs->hash.iaddr1, 0);
	882	+ out_be32(&regs->hash.iaddr2, 0);
	883	+ out_be32(&regs->hash.iaddr3, 0);
	884	+ out_be32(&regs->hash.iaddr4, 0);
	885	+ out_be32(&regs->hash.iaddr5, 0);
	886	+ out_be32(&regs->hash.iaddr6, 0);
	887	+ out_be32(&regs->hash.iaddr7, 0);
892	888
893		- regs->hash.gaddr0 = 0;
894		- regs->hash.gaddr1 = 0;
895		- regs->hash.gaddr2 = 0;
896		- regs->hash.gaddr3 = 0;
897		- regs->hash.gaddr4 = 0;
898		- regs->hash.gaddr5 = 0;
899		- regs->hash.gaddr6 = 0;
900		- regs->hash.gaddr7 = 0;
	889	+ out_be32(&regs->hash.gaddr0, 0);
	890	+ out_be32(&regs->hash.gaddr1, 0);
	891	+ out_be32(&regs->hash.gaddr2, 0);
	892	+ out_be32(&regs->hash.gaddr3, 0);
	893	+ out_be32(&regs->hash.gaddr4, 0);
	894	+ out_be32(&regs->hash.gaddr5, 0);
	895	+ out_be32(&regs->hash.gaddr6, 0);
	896	+ out_be32(&regs->hash.gaddr7, 0);
901	897
902		- regs->rctrl = 0x00000000;
	898	+ out_be32(&regs->rctrl, 0x00000000);
903	899
904	900	/* Init RMON mib registers */
905	901	memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
906	902
907		- regs->rmon.cam1 = 0xffffffff;
908		- regs->rmon.cam2 = 0xffffffff;
	903	+ out_be32(&regs->rmon.cam1, 0xffffffff);
	904	+ out_be32(&regs->rmon.cam2, 0xffffffff);
909	905
910		- regs->mrblr = MRBLR_INIT_SETTINGS;
	906	+ out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
911	907
912		- regs->minflr = MINFLR_INIT_SETTINGS;
	908	+ out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
913	909
914		- regs->attr = ATTR_INIT_SETTINGS;
915		- regs->attreli = ATTRELI_INIT_SETTINGS;
	910	+ out_be32(&regs->attr, ATTR_INIT_SETTINGS);
	911	+ out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
916	912
917	913	}
918	914
919	915
920	916
921	917
922	918
923	919
924	920
...	...	@@ -922,44 +918,49 @@
922	918	static void adjust_link(struct eth_device *dev)
923	919	{
924	920	struct tsec_private priv = (struct tsec_private )dev->priv;
925		- volatile tsec_t *regs = priv->regs;
	921	+ tsec_t *regs = priv->regs;
	922	+ u32 ecntrl, maccfg2;
926	923
927		- if (priv->link) {
928		- if (priv->duplexity != 0)
929		- regs->maccfg2 \|= MACCFG2_FULL_DUPLEX;
930		- else
931		- regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
	924	+ if (!priv->link) {
	925	+ printf("%s: No link.\n", dev->name);
	926	+ return;
	927	+ }
932	928
933		- switch (priv->speed) {
934		- case 1000:
935		- regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
936		- \| MACCFG2_GMII);
937		- break;
938		- case 100:
939		- case 10:
940		- regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
941		- \| MACCFG2_MII);
	929	+ /* clear all bits relative with interface mode */
	930	+ ecntrl = in_be32(&regs->ecntrl);
	931	+ ecntrl &= ~ECNTRL_R100;
942	932
943		- /* Set R100 bit in all modes although
944		- * it is only used in RGMII mode
945		- */
946		- if (priv->speed == 100)
947		- regs->ecntrl \|= ECNTRL_R100;
948		- else
949		- regs->ecntrl &= ~(ECNTRL_R100);
950		- break;
951		- default:
952		- printf("%s: Speed was bad\n", dev->name);
953		- break;
954		- }
	933	+ maccfg2 = in_be32(&regs->maccfg2);
	934	+ maccfg2 &= ~(MACCFG2_IF \| MACCFG2_FULL_DUPLEX);
955	935
956		- printf("Speed: %d, %s duplex%s\n", priv->speed,
957		- (priv->duplexity) ? "full" : "half",
958		- (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
	936	+ if (priv->duplexity)
	937	+ maccfg2 \|= MACCFG2_FULL_DUPLEX;
959	938
960		- } else {
961		- printf("%s: No link.\n", dev->name);
	939	+ switch (priv->speed) {
	940	+ case 1000:
	941	+ maccfg2 \|= MACCFG2_GMII;
	942	+ break;
	943	+ case 100:
	944	+ case 10:
	945	+ maccfg2 \|= MACCFG2_MII;
	946	+
	947	+ /* Set R100 bit in all modes although
	948	+ * it is only used in RGMII mode
	949	+ */
	950	+ if (priv->speed == 100)
	951	+ ecntrl \|= ECNTRL_R100;
	952	+ break;
	953	+ default:
	954	+ printf("%s: Speed was bad\n", dev->name);
	955	+ break;
962	956	}
	957	+
	958	+ out_be32(&regs->ecntrl, ecntrl);
	959	+ out_be32(&regs->maccfg2, maccfg2);
	960	+
	961	+ printf("Speed: %d, %s duplex%s\n", priv->speed,
	962	+ (priv->duplexity) ? "full" : "half",
	963	+ (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
963	964	}
964	965
965	966	/* Set up the buffers and their descriptors, and bring up the
966	967
...	...	@@ -969,11 +970,11 @@
969	970	{
970	971	int i;
971	972	struct tsec_private priv = (struct tsec_private )dev->priv;
972		- volatile tsec_t *regs = priv->regs;
	973	+ tsec_t *regs = priv->regs;
973	974
974	975	/* Point to the buffer descriptors */
975		- regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
976		- regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
	976	+ out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
	977	+ out_be32(&regs->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
977	978
978	979	/* Initialize the Rx Buffer descriptors */
979	980	for (i = 0; i < PKTBUFSRX; i++) {
980	981
...	...	@@ -998,13 +999,13 @@
998	999	adjust_link(dev);
999	1000
1000	1001	/* Enable Transmit and Receive */
1001		- regs->maccfg1 \|= (MACCFG1_RX_EN \| MACCFG1_TX_EN);
	1002	+ setbits_be32(&regs->maccfg1, MACCFG1_RX_EN \| MACCFG1_TX_EN);
1002	1003
1003	1004	/* Tell the DMA it is clear to go */
1004		- regs->dmactrl \|= DMACTRL_INIT_SETTINGS;
1005		- regs->tstat = TSTAT_CLEAR_THALT;
1006		- regs->rstat = RSTAT_CLEAR_RHALT;
1007		- regs->dmactrl &= ~(DMACTRL_GRS \| DMACTRL_GTS);
	1005	+ setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
	1006	+ out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
	1007	+ out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
	1008	+ clrbits_be32(&regs->dmactrl, DMACTRL_GRS \| DMACTRL_GTS);
1008	1009	}
1009	1010
1010	1011	/* This returns the status bits of the device. The return value
...	...	@@ -1017,7 +1018,7 @@
1017	1018	int i;
1018	1019	int result = 0;
1019	1020	struct tsec_private priv = (struct tsec_private )dev->priv;
1020		- volatile tsec_t *regs = priv->regs;
	1021	+ tsec_t *regs = priv->regs;
1021	1022
1022	1023	/* Find an empty buffer descriptor */
1023	1024	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
...	...	@@ -1033,7 +1034,7 @@
1033	1034	(TXBD_READY \| TXBD_LAST \| TXBD_CRC \| TXBD_INTERRUPT);
1034	1035
1035	1036	/* Tell the DMA to go */
1036		- regs->tstat = TSTAT_CLEAR_THALT;
	1037	+ out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
1037	1038
1038	1039	/* Wait for buffer to be transmitted */
1039	1040	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
...	...	@@ -1053,7 +1054,7 @@
1053	1054	{
1054	1055	int length;
1055	1056	struct tsec_private priv = (struct tsec_private )dev->priv;
1056		- volatile tsec_t *regs = priv->regs;
	1057	+ tsec_t *regs = priv->regs;
1057	1058
1058	1059	while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
1059	1060
...	...	@@ -1076,9 +1077,9 @@
1076	1077	rxIdx = (rxIdx + 1) % PKTBUFSRX;
1077	1078	}
1078	1079
1079		- if (regs->ievent & IEVENT_BSY) {
1080		- regs->ievent = IEVENT_BSY;
1081		- regs->rstat = RSTAT_CLEAR_RHALT;
	1080	+ if (in_be32(&regs->ievent) & IEVENT_BSY) {
	1081	+ out_be32(&regs->ievent, IEVENT_BSY);
	1082	+ out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
1082	1083	}
1083	1084
1084	1085	return -1;
1085	1086
1086	1087
1087	1088
...	...	@@ -1089,15 +1090,16 @@
1089	1090	static void tsec_halt(struct eth_device *dev)
1090	1091	{
1091	1092	struct tsec_private priv = (struct tsec_private )dev->priv;
1092		- volatile tsec_t *regs = priv->regs;
	1093	+ tsec_t *regs = priv->regs;
1093	1094
1094		- regs->dmactrl &= ~(DMACTRL_GRS \| DMACTRL_GTS);
1095		- regs->dmactrl \|= (DMACTRL_GRS \| DMACTRL_GTS);
	1095	+ clrbits_be32(&regs->dmactrl, DMACTRL_GRS \| DMACTRL_GTS);
	1096	+ setbits_be32(&regs->dmactrl, DMACTRL_GRS \| DMACTRL_GTS);
1096	1097
1097		- while ((regs->ievent & (IEVENT_GRSC \| IEVENT_GTSC))
1098		- != (IEVENT_GRSC \| IEVENT_GTSC)) ;
	1098	+ while ((in_be32(&regs->ievent) & (IEVENT_GRSC \| IEVENT_GTSC))
	1099	+ != (IEVENT_GRSC \| IEVENT_GTSC))
	1100	+ ;
1099	1101
1100		- regs->maccfg1 &= ~(MACCFG1_TX_EN \| MACCFG1_RX_EN);
	1102	+ clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN \| MACCFG1_RX_EN);
1101	1103
1102	1104	/* Shut down the PHY, as needed */
1103	1105	if(priv->phyinfo)
1104	1106
1105	1107
1106	1108
...	...	@@ -1904,13 +1906,14 @@
1904	1906	{
1905	1907	int i;
1906	1908	uint result;
1907		- volatile tsec_mdio_t *phyregs = priv->phyregs;
	1909	+ tsec_mdio_t *phyregs = priv->phyregs;
1908	1910
1909		- phyregs->miimcfg = MIIMCFG_RESET;
	1911	+ out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
1910	1912
1911		- phyregs->miimcfg = MIIMCFG_INIT_VALUE;
	1913	+ out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
1912	1914
1913		- while (phyregs->miimind & MIIMIND_BUSY) ;
	1915	+ while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
	1916	+ ;
1914	1917
1915	1918	for (i = 0; cmd->mii_reg != miim_end; i++) {
1916	1919	if (cmd->mii_data == miim_read) {
...	...	@@ -7,7 +7,7 @@
7	7	* terms of the GNU Public License, Version 2, incorporated
8	8	* herein by reference.
9	9	*
10		- * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
	10	+ * Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc.
11	11	* (C) Copyright 2003, Motorola, Inc.
12	12	* maintained by Xianghua Xiao (x.xiao@motorola.com)
13	13	* author Andy Fleming
...	...	@@ -587,9 +587,9 @@
587	587	#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
588	588
589	589	struct tsec_private {
590		- volatile tsec_t *regs;
591		- volatile tsec_mdio_t *phyregs;
592		- volatile tsec_mdio_t *phyregs_sgmii;
	590	+ tsec_t *regs;
	591	+ tsec_mdio_t *phyregs;
	592	+ tsec_mdio_t *phyregs_sgmii;
593	593	struct phy_info *phyinfo;
594	594	uint phyaddr;
595	595	u32 flags;