Commit a359eaa59857079678a2fa5ff0e4c0894de4ee1d
1 parent
9aa65cab73
Exists in
v2017.01-smarct4x
and in
29 other branches
microblaze: Remove !OF_CONTROL code for timer and interrupt
OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Showing 4 changed files with 1 additions and 45 deletions Side-by-side Diff
arch/microblaze/cpu/interrupts.c
| ... | ... | @@ -115,8 +115,6 @@ |
| 115 | 115 | int interrupt_init(void) |
| 116 | 116 | { |
| 117 | 117 | int i; |
| 118 | - | |
| 119 | -#ifdef CONFIG_OF_CONTROL | |
| 120 | 118 | const void *blob = gd->fdt_blob; |
| 121 | 119 | int node = 0; |
| 122 | 120 | |
| ... | ... | @@ -136,12 +134,7 @@ |
| 136 | 134 | } else { |
| 137 | 135 | return node; |
| 138 | 136 | } |
| 139 | -#else | |
| 140 | -#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) | |
| 141 | - intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR; | |
| 142 | - irq_no = CONFIG_SYS_INTC_0_NUM; | |
| 143 | -#endif | |
| 144 | -#endif | |
| 137 | + | |
| 145 | 138 | if (irq_no) { |
| 146 | 139 | vecs = calloc(1, sizeof(struct irq_action) * irq_no); |
| 147 | 140 | if (vecs == NULL) { |
arch/microblaze/cpu/timer.c
| ... | ... | @@ -31,11 +31,6 @@ |
| 31 | 31 | i = get_timer(0); |
| 32 | 32 | while ((get_timer(0) - i) < (usec / 1000)) |
| 33 | 33 | ; |
| 34 | - } else { | |
| 35 | -#ifndef CONFIG_OF_CONTROL | |
| 36 | - for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++) | |
| 37 | - ; | |
| 38 | -#endif | |
| 39 | 34 | } |
| 40 | 35 | } |
| 41 | 36 | |
| ... | ... | @@ -51,8 +46,6 @@ |
| 51 | 46 | int irq = -1; |
| 52 | 47 | u32 preload = 0; |
| 53 | 48 | u32 ret = 0; |
| 54 | - | |
| 55 | -#ifdef CONFIG_OF_CONTROL | |
| 56 | 49 | const void *blob = gd->fdt_blob; |
| 57 | 50 | int node = 0; |
| 58 | 51 | u32 cell[2]; |
| ... | ... | @@ -83,13 +76,6 @@ |
| 83 | 76 | return node; |
| 84 | 77 | } |
| 85 | 78 | |
| 86 | -#else | |
| 87 | -#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) | |
| 88 | - preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ; | |
| 89 | - irq = CONFIG_SYS_TIMER_0_IRQ; | |
| 90 | - tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); | |
| 91 | -#endif | |
| 92 | -#endif | |
| 93 | 79 | if (tmr && preload && irq >= 0) { |
| 94 | 80 | tmr->loadreg = preload; |
| 95 | 81 | tmr->control = TIMER_INTERRUPT | TIMER_RESET; |
board/xilinx/microblaze-generic/xparameters.h
| ... | ... | @@ -13,20 +13,9 @@ |
| 13 | 13 | |
| 14 | 14 | #define XILINX_BOARD_NAME microblaze-generic |
| 15 | 15 | |
| 16 | -/* System Clock Frequency */ | |
| 17 | -#define XILINX_CLOCK_FREQ 100000000 | |
| 18 | - | |
| 19 | 16 | /* Microblaze is microblaze_0 */ |
| 20 | 17 | #define XILINX_USE_MSR_INSTR 1 |
| 21 | 18 | #define XILINX_FSL_NUMBER 3 |
| 22 | - | |
| 23 | -/* Interrupt controller is opb_intc_0 */ | |
| 24 | -#define XILINX_INTC_BASEADDR 0x41200000 | |
| 25 | -#define XILINX_INTC_NUM_INTR_INPUTS 6 | |
| 26 | - | |
| 27 | -/* Timer pheriphery is opb_timer_1 */ | |
| 28 | -#define XILINX_TIMER_BASEADDR 0x41c00000 | |
| 29 | -#define XILINX_TIMER_IRQ 0 | |
| 30 | 19 | |
| 31 | 20 | /* GPIO is LEDs_4Bit*/ |
| 32 | 21 | #define XILINX_GPIO_BASEADDR 0x40000000 |
include/configs/microblaze-generic.h
| ... | ... | @@ -47,18 +47,6 @@ |
| 47 | 47 | #endif |
| 48 | 48 | #define CONFIG_BOARD_LATE_INIT |
| 49 | 49 | |
| 50 | -/* interrupt controller */ | |
| 51 | -#ifdef XILINX_INTC_BASEADDR | |
| 52 | -# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR | |
| 53 | -# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS | |
| 54 | -#endif | |
| 55 | - | |
| 56 | -/* timer */ | |
| 57 | -#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) | |
| 58 | -# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR | |
| 59 | -# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ | |
| 60 | -#endif | |
| 61 | - | |
| 62 | 50 | /* watchdog */ |
| 63 | 51 | #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) |
| 64 | 52 | # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR |