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Commit a46d821fc88674246b74569dcdc54cdac91dfc4c

Authored by wdenk 2002-09-13 06:01:13 +0800

1 parent da27dcf008

Exists in master and in 54 other branches

Initial revision

Showing 13 changed files with 2028 additions and 0 deletions Side-by-side Diff

common/cmd_diag.c
include/cmd_diag.h
post/cpu/andi.c
post/cpu/asm.S
post/cpu/complex.c
post/cpu/load.c
post/cpu/multi.c
post/cpu/rlwimi.c
post/cpu/rlwinm.c
post/cpu/rlwnm.c
post/cpu/srawi.c
post/cpu/store.c
post/cpu/string.c

common/cmd_diag.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+/*
	25	+ * Diagnostics support
	26	+ */
	27	+#include <common.h>
	28	+#include <command.h>
	29	+#include <cmd_diag.h>
	30	+#include <post.h>
	31	+
	32	+#if (CONFIG_COMMANDS & CFG_CMD_DIAG) && defined(CONFIG_POST)
	33	+
	34	+int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	35	+{
	36	+ unsigned int i;
	37	+
	38	+ if (argc == 1 \|\| strcmp (argv[1], "run") != 0) {
	39	+ /* List test info */
	40	+ if (argc == 1) {
	41	+ printf ("Available hardware tests:\n");
	42	+ post_info (NULL);
	43	+ printf ("Use 'diag [<test1> [<test2> ...]]'"
	44	+ " to get more info.\n");
	45	+ printf ("Use 'diag run [<test1> [<test2> ...]]'"
	46	+ " to run tests.\n");
	47	+ } else {
	48	+ for (i = 1; i < argc; i++) {
	49	+ if (post_info (argv[i]) != 0)
	50	+ printf ("%s - no such test\n", argv[i]);
	51	+ }
	52	+ }
	53	+ } else {
	54	+ /* Run tests */
	55	+ if (argc == 2) {
	56	+ post_run (NULL, POST_RAM \| POST_MANUAL);
	57	+ } else {
	58	+ for (i = 2; i < argc; i++) {
	59	+ if (post_run (argv[i], POST_RAM \| POST_MANUAL) != 0)
	60	+ printf ("%s - unable to execute the test\n",
	61	+ argv[i]);
	62	+ }
	63	+ }
	64	+ }
	65	+
	66	+ return 0;
	67	+}
	68	+
	69	+#endif /* CFG_CMD_DIAG */

include/cmd_diag.h

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+/*
	25	+ * Diagnostics support
	26	+ */
	27	+#ifndef _CMD_DIAG_H
	28	+#define _CMD_DIAG_H
	29	+
	30	+#include <common.h>
	31	+
	32	+#if (CONFIG_COMMANDS & CFG_CMD_DIAG) && defined(CONFIG_POST)
	33	+#define CMD_TBL_DIAG MK_CMD_TBL_ENTRY( \
	34	+ "diag", 4, CFG_MAXARGS, 0, do_diag, \
	35	+ "diag - perform board diagnostics\n", \
	36	+ " - print list of available tests\n" \
	37	+ "diag [test1 [test2]]\n" \
	38	+ " - print information about specified tests\n" \
	39	+ "diag run - run all available tests\n" \
	40	+ "diag run [test1 [test2]]\n" \
	41	+ " - run specified tests\n" \
	42	+),
	43	+
	44	+int do_diag (cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
	45	+#else
	46	+#define CMD_TBL_DIAG
	47	+#endif /* CFG_CMD_DIAG */
	48	+
	49	+#endif /* _CMD_DIAG_H */

post/cpu/andi.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Logic instructions: andi., andis.
	29	+ *
	30	+ * The test contains a pre-built table of instructions, operands and
	31	+ * expected results. For each table entry, the test will cyclically use
	32	+ * different sets of operand registers and result registers.
	33	+ */
	34	+
	35	+#ifdef CONFIG_POST
	36	+
	37	+#include <post.h>
	38	+#include "cpu_asm.h"
	39	+
	40	+#if CONFIG_POST & CFG_POST_CPU
	41	+
	42	+extern void cpu_post_exec_21 (ulong code, ulong cr, ulong *res, ulong op);
	43	+extern ulong cpu_post_makecr (long v);
	44	+
	45	+static struct cpu_post_andi_s
	46	+{
	47	+ ulong cmd;
	48	+ ulong op1;
	49	+ ushort op2;
	50	+ ulong res;
	51	+} cpu_post_andi_table[] =
	52	+{
	53	+ {
	54	+ OP_ANDI_,
	55	+ 0x80008000,
	56	+ 0xffff,
	57	+ 0x00008000
	58	+ },
	59	+ {
	60	+ OP_ANDIS_,
	61	+ 0x80008000,
	62	+ 0xffff,
	63	+ 0x80000000
	64	+ },
	65	+};
	66	+static unsigned int cpu_post_andi_size =
	67	+ sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s);
	68	+
	69	+int cpu_post_test_andi (void)
	70	+{
	71	+ int ret = 0;
	72	+ unsigned int i, reg;
	73	+ int flag = disable_interrupts();
	74	+
	75	+ for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
	76	+ {
	77	+ struct cpu_post_andi_s *test = cpu_post_andi_table + i;
	78	+
	79	+ for (reg = 0; reg < 32 && ret == 0; reg++)
	80	+ {
	81	+ unsigned int reg0 = (reg + 0) % 32;
	82	+ unsigned int reg1 = (reg + 1) % 32;
	83	+ unsigned int stk = reg < 16 ? 31 : 15;
	84	+ unsigned long codecr[] =
	85	+ {
	86	+ ASM_STW(stk, 1, -4),
	87	+ ASM_ADDI(stk, 1, -16),
	88	+ ASM_STW(3, stk, 8),
	89	+ ASM_STW(reg0, stk, 4),
	90	+ ASM_STW(reg1, stk, 0),
	91	+ ASM_LWZ(reg0, stk, 8),
	92	+ ASM_11IX(test->cmd, reg1, reg0, test->op2),
	93	+ ASM_STW(reg1, stk, 8),
	94	+ ASM_LWZ(reg1, stk, 0),
	95	+ ASM_LWZ(reg0, stk, 4),
	96	+ ASM_LWZ(3, stk, 8),
	97	+ ASM_ADDI(1, stk, 16),
	98	+ ASM_LWZ(stk, 1, -4),
	99	+ ASM_BLR,
	100	+ };
	101	+ ulong res;
	102	+ ulong cr;
	103	+
	104	+ cpu_post_exec_21 (codecr, & cr, & res, test->op1);
	105	+
	106	+ ret = res == test->res &&
	107	+ (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
	108	+
	109	+ if (ret != 0)
	110	+ {
	111	+ post_log ("Error at andi test %d !\n", i);
	112	+ }
	113	+ }
	114	+ }
	115	+
	116	+ if (flag)
	117	+ enable_interrupts();
	118	+
	119	+ return ret;
	120	+}
	121	+
	122	+#endif
	123	+#endif

post/cpu/asm.S

Diff comments View file @ a46d821

	1	+/*
	2	+ * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
	3	+ *
	4	+ * See file CREDITS for list of people who contributed to this
	5	+ * project.
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ */
	22	+
	23	+#include <config.h>
	24	+
	25	+#ifdef CONFIG_POST
	26	+
	27	+#include <post.h>
	28	+#include <ppc_asm.tmpl>
	29	+#include <ppc_defs.h>
	30	+#include <asm/cache.h>
	31	+
	32	+#if CONFIG_POST & CFG_POST_CPU
	33	+
	34	+/* void cpu_post_exec_02 (ulong code, ulong op1, ulong op2); /
	35	+ .global cpu_post_exec_02
	36	+cpu_post_exec_02:
	37	+ mflr r0
	38	+ stwu r0, -4(r1)
	39	+
	40	+ subi r1, r1, 104
	41	+ stmw r6, 0(r1)
	42	+
	43	+ mtlr r3
	44	+ mr r3, r4
	45	+ mr r4, r5
	46	+ blrl
	47	+
	48	+ lmw r6, 0(r1)
	49	+ addi r1, r1, 104
	50	+
	51	+ lwz r0, 0(r1)
	52	+ addi r1, r1, 4
	53	+ mtlr r0
	54	+ blr
	55	+
	56	+/* void cpu_post_exec_04 (ulong code, ulong op1, ulong op2, ulong op3, ulong op4); /
	57	+ .global cpu_post_exec_04
	58	+cpu_post_exec_04:
	59	+ mflr r0
	60	+ stwu r0, -4(r1)
	61	+
	62	+ subi r1, r1, 96
	63	+ stmw r8, 0(r1)
	64	+
	65	+ mtlr r3
	66	+ mr r3, r4
	67	+ mr r4, r5
	68	+ mr r5, r6
	69	+ mtxer r7
	70	+ blrl
	71	+
	72	+ lmw r8, 0(r1)
	73	+ addi r1, r1, 96
	74	+
	75	+ lwz r0, 0(r1)
	76	+ addi r1, r1, 4
	77	+ mtlr r0
	78	+ blr
	79	+
	80	+/* void cpu_post_exec_12 (ulong code, ulong res, ulong op1, ulong op2); */
	81	+ .global cpu_post_exec_12
	82	+cpu_post_exec_12:
	83	+ mflr r0
	84	+ stwu r0, -4(r1)
	85	+ stwu r4, -4(r1)
	86	+
	87	+ mtlr r3
	88	+ mr r3, r5
	89	+ mr r4, r6
	90	+ blrl
	91	+
	92	+ lwz r4, 0(r1)
	93	+ stw r3, 0(r4)
	94	+
	95	+ lwz r0, 4(r1)
	96	+ addi r1, r1, 8
	97	+ mtlr r0
	98	+ blr
	99	+
	100	+/* void cpu_post_exec_11 (ulong code, ulong res, ulong op1); */
	101	+ .global cpu_post_exec_11
	102	+cpu_post_exec_11:
	103	+ mflr r0
	104	+ stwu r0, -4(r1)
	105	+ stwu r4, -4(r1)
	106	+
	107	+ mtlr r3
	108	+ mr r3, r5
	109	+ blrl
	110	+
	111	+ lwz r4, 0(r1)
	112	+ stw r3, 0(r4)
	113	+
	114	+ lwz r0, 4(r1)
	115	+ addi r1, r1, 8
	116	+ mtlr r0
	117	+ blr
	118	+
	119	+/* void cpu_post_exec_21 (ulong code, ulong cr, ulong res, ulong op1); /
	120	+ .global cpu_post_exec_21
	121	+cpu_post_exec_21:
	122	+ mflr r0
	123	+ stwu r0, -4(r1)
	124	+ stwu r4, -4(r1)
	125	+ stwu r5, -4(r1)
	126	+
	127	+ li r0, 0
	128	+ mtxer r0
	129	+ lwz r0, 0(r4)
	130	+ mtcr r0
	131	+
	132	+ mtlr r3
	133	+ mr r3, r6
	134	+ blrl
	135	+
	136	+ mfcr r0
	137	+ lwz r4, 4(r1)
	138	+ stw r0, 0(r4)
	139	+ lwz r4, 0(r1)
	140	+ stw r3, 0(r4)
	141	+
	142	+ lwz r0, 8(r1)
	143	+ addi r1, r1, 12
	144	+ mtlr r0
	145	+ blr
	146	+
	147	+/* void cpu_post_exec_22 (ulong code, ulong cr, ulong *res, ulong op1,
	148	+ ulong op2); */
	149	+ .global cpu_post_exec_22
	150	+cpu_post_exec_22:
	151	+ mflr r0
	152	+ stwu r0, -4(r1)
	153	+ stwu r4, -4(r1)
	154	+ stwu r5, -4(r1)
	155	+
	156	+ li r0, 0
	157	+ mtxer r0
	158	+ lwz r0, 0(r4)
	159	+ mtcr r0
	160	+
	161	+ mtlr r3
	162	+ mr r3, r6
	163	+ mr r4, r7
	164	+ blrl
	165	+
	166	+ mfcr r0
	167	+ lwz r4, 4(r1)
	168	+ stw r0, 0(r4)
	169	+ lwz r4, 0(r1)
	170	+ stw r3, 0(r4)
	171	+
	172	+ lwz r0, 8(r1)
	173	+ addi r1, r1, 12
	174	+ mtlr r0
	175	+ blr
	176	+
	177	+/* void cpu_post_exec_12w (ulong code, ulong op1, ulong op2, ulong op3); */
	178	+ .global cpu_post_exec_12w
	179	+cpu_post_exec_12w:
	180	+ mflr r0
	181	+ stwu r0, -4(r1)
	182	+ stwu r4, -4(r1)
	183	+
	184	+ mtlr r3
	185	+ lwz r3, 0(r4)
	186	+ mr r4, r5
	187	+ mr r5, r6
	188	+ blrl
	189	+
	190	+ lwz r4, 0(r1)
	191	+ stw r3, 0(r4)
	192	+
	193	+ lwz r0, 4(r1)
	194	+ addi r1, r1, 8
	195	+ mtlr r0
	196	+ blr
	197	+
	198	+/* void cpu_post_exec_11w (ulong code, ulong op1, ulong op2); */
	199	+ .global cpu_post_exec_11w
	200	+cpu_post_exec_11w:
	201	+ mflr r0
	202	+ stwu r0, -4(r1)
	203	+ stwu r4, -4(r1)
	204	+
	205	+ mtlr r3
	206	+ lwz r3, 0(r4)
	207	+ mr r4, r5
	208	+ blrl
	209	+
	210	+ lwz r4, 0(r1)
	211	+ stw r3, 0(r4)
	212	+
	213	+ lwz r0, 4(r1)
	214	+ addi r1, r1, 8
	215	+ mtlr r0
	216	+ blr
	217	+
	218	+/* void cpu_post_exec_22w (ulong code, ulong op1, ulong op2, ulong op3); /
	219	+ .global cpu_post_exec_22w
	220	+cpu_post_exec_22w:
	221	+ mflr r0
	222	+ stwu r0, -4(r1)
	223	+ stwu r4, -4(r1)
	224	+ stwu r6, -4(r1)
	225	+
	226	+ mtlr r3
	227	+ lwz r3, 0(r4)
	228	+ mr r4, r5
	229	+ blrl
	230	+
	231	+ lwz r4, 4(r1)
	232	+ stw r3, 0(r4)
	233	+ lwz r4, 0(r1)
	234	+ stw r5, 0(r4)
	235	+
	236	+ lwz r0, 8(r1)
	237	+ addi r1, r1, 12
	238	+ mtlr r0
	239	+ blr
	240	+
	241	+/* void cpu_post_exec_21w (ulong code, ulong op1, ulong op2); /
	242	+ .global cpu_post_exec_21w
	243	+cpu_post_exec_21w:
	244	+ mflr r0
	245	+ stwu r0, -4(r1)
	246	+ stwu r4, -4(r1)
	247	+ stwu r5, -4(r1)
	248	+
	249	+ mtlr r3
	250	+ lwz r3, 0(r4)
	251	+ blrl
	252	+
	253	+ lwz r5, 4(r1)
	254	+ stw r3, 0(r5)
	255	+ lwz r5, 0(r1)
	256	+ stw r4, 0(r5)
	257	+
	258	+ lwz r0, 8(r1)
	259	+ addi r1, r1, 12
	260	+ mtlr r0
	261	+ blr
	262	+
	263	+/* void cpu_post_exec_21x (ulong code, ulong op1, ulong op2, ulong op3); /
	264	+ .global cpu_post_exec_21x
	265	+cpu_post_exec_21x:
	266	+ mflr r0
	267	+ stwu r0, -4(r1)
	268	+ stwu r4, -4(r1)
	269	+ stwu r5, -4(r1)
	270	+
	271	+ mtlr r3
	272	+ mr r3, r6
	273	+ blrl
	274	+
	275	+ lwz r5, 4(r1)
	276	+ stw r3, 0(r5)
	277	+ lwz r5, 0(r1)
	278	+ stw r4, 0(r5)
	279	+
	280	+ lwz r0, 8(r1)
	281	+ addi r1, r1, 12
	282	+ mtlr r0
	283	+ blr
	284	+
	285	+/* void cpu_post_exec_31 (ulong code, ulong ctr, ulong lr, ulong jump,
	286	+ ulong cr); */
	287	+ .global cpu_post_exec_31
	288	+cpu_post_exec_31:
	289	+ mflr r0
	290	+ stwu r0, -4(r1)
	291	+ stwu r4, -4(r1)
	292	+ stwu r5, -4(r1)
	293	+ stwu r6, -4(r1)
	294	+
	295	+ mtlr r3
	296	+ lwz r3, 0(r4)
	297	+ lwz r4, 0(r5)
	298	+ mr r6, r7
	299	+ blrl
	300	+
	301	+ lwz r7, 8(r1)
	302	+ stw r3, 0(r7)
	303	+ lwz r7, 4(r1)
	304	+ stw r4, 0(r7)
	305	+ lwz r7, 0(r1)
	306	+ stw r5, 0(r7)
	307	+
	308	+ lwz r0, 12(r1)
	309	+ addi r1, r1, 16
	310	+ mtlr r0
	311	+ blr
	312	+
	313	+/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
	314	+ .global cpu_post_complex_1_asm
	315	+cpu_post_complex_1_asm:
	316	+ li r9,0
	317	+ cmpw r9,r7
	318	+ bge cpu_post_complex_1_done
	319	+ mtctr r7
	320	+cpu_post_complex_1_loop:
	321	+ mullw r0,r3,r4
	322	+ subf r0,r5,r0
	323	+ divw r0,r0,r6
	324	+ add r9,r9,r0
	325	+ bdnz cpu_post_complex_1_loop
	326	+cpu_post_complex_1_done:
	327	+ mr r3,r9
	328	+ blr
	329	+
	330	+/* int cpu_post_complex_2_asm (int x, int n); */
	331	+ .global cpu_post_complex_2_asm
	332	+cpu_post_complex_2_asm:
	333	+ mr. r0,r4
	334	+ mtctr r0
	335	+ mr r0,r3
	336	+ li r3,1
	337	+ li r4,1
	338	+ blelr
	339	+cpu_post_complex_2_loop:
	340	+ mullw r3,r3,r0
	341	+ add r3,r3,r4
	342	+ bdnz cpu_post_complex_2_loop
	343	+blr
	344	+
	345	+#endif
	346	+#endif

post/cpu/complex.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Complex calculations
	29	+ *
	30	+ * The calculations in this test are just a combination of simpler
	31	+ * calculations, but probably under different timing conditions, etc.
	32	+ */
	33	+
	34	+#ifdef CONFIG_POST
	35	+
	36	+#include <post.h>
	37	+#include "cpu_asm.h"
	38	+
	39	+#if CONFIG_POST & CFG_POST_CPU
	40	+
	41	+extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n);
	42	+extern int cpu_post_complex_2_asm (int x, int n);
	43	+
	44	+ /*
	45	+ * n
	46	+ * SUM (a1 * a2 - a3) / a4 = n * result
	47	+ * i=1
	48	+ */
	49	+static int cpu_post_test_complex_1 (void)
	50	+{
	51	+ int a1 = 666;
	52	+ int a2 = 667;
	53	+ int a3 = 668;
	54	+ int a4 = 66;
	55	+ int n = 100;
	56	+ int result = 6720; /* (a1 * a2 - a3) / a4 */
	57	+
	58	+ if (cpu_post_complex_1_asm(a1, a2, a3, a4, n) != n * result)
	59	+ {
	60	+ return -1;
	61	+ }
	62	+
	63	+ return 0;
	64	+}
	65	+
	66	+ /* (1 + x + x^2 + ... + x^n) * (1 - x) = 1 - x^(n+1)
	67	+ */
	68	+static int cpu_post_test_complex_2 (void)
	69	+{
	70	+ int ret = -1;
	71	+ int x;
	72	+ int n;
	73	+ int k;
	74	+ int left;
	75	+ int right;
	76	+
	77	+ for (x = -8; x <= 8; x ++)
	78	+ {
	79	+ n = 9;
	80	+
	81	+ left = cpu_post_complex_2_asm(x, n);
	82	+ left *= 1 - x;
	83	+
	84	+ right = 1;
	85	+ for (k = 0; k <= n; k ++)
	86	+ {
	87	+ right *= x;
	88	+ }
	89	+ right = 1 - right;
	90	+
	91	+ if (left != right)
	92	+ {
	93	+ goto Done;
	94	+ }
	95	+ }
	96	+
	97	+ ret = 0;
	98	+ Done:
	99	+
	100	+ return ret;
	101	+}
	102	+
	103	+int cpu_post_test_complex (void)
	104	+{
	105	+ int ret = 0;
	106	+
	107	+ if (ret == 0)
	108	+ {
	109	+ ret = cpu_post_test_complex_1();
	110	+ }
	111	+
	112	+ if (ret == 0)
	113	+ {
	114	+ ret = cpu_post_test_complex_2();
	115	+ }
	116	+
	117	+ if (ret != 0)
	118	+ {
	119	+ post_log ("Error at complex test !\n");
	120	+ }
	121	+
	122	+ return ret;
	123	+}
	124	+
	125	+#endif
	126	+#endif

post/cpu/load.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u)
	29	+ *
	30	+ * All operations are performed on a 16-byte array. The array
	31	+ * is 4-byte aligned. The base register points to offset 8.
	32	+ * The immediate offset (index register) ranges in [-8 ... +7].
	33	+ * The test cases are composed so that they do not
	34	+ * cause alignment exceptions.
	35	+ * The test contains a pre-built table describing all test cases.
	36	+ * The table entry contains:
	37	+ * the instruction opcode, the array contents, the value of the index
	38	+ * register and the expected value of the destination register.
	39	+ * After executing the instruction, the test verifies the
	40	+ * value of the destination register and the value of the base
	41	+ * register (it must change for "load with update" instructions).
	42	+ */
	43	+
	44	+#ifdef CONFIG_POST
	45	+
	46	+#include <post.h>
	47	+#include "cpu_asm.h"
	48	+
	49	+#if CONFIG_POST & CFG_POST_CPU
	50	+
	51	+extern void cpu_post_exec_22w (ulong code, ulong op1, ulong op2, ulong *op3);
	52	+extern void cpu_post_exec_21w (ulong code, ulong op1, ulong *op2);
	53	+
	54	+static struct cpu_post_load_s
	55	+{
	56	+ ulong cmd;
	57	+ uint width;
	58	+ int update;
	59	+ int index;
	60	+ ulong offset;
	61	+} cpu_post_load_table[] =
	62	+{
	63	+ {
	64	+ OP_LWZ,
	65	+ 4,
	66	+ 0,
	67	+ 0,
	68	+ 4
	69	+ },
	70	+ {
	71	+ OP_LHA,
	72	+ 3,
	73	+ 0,
	74	+ 0,
	75	+ 2
	76	+ },
	77	+ {
	78	+ OP_LHZ,
	79	+ 2,
	80	+ 0,
	81	+ 0,
	82	+ 2
	83	+ },
	84	+ {
	85	+ OP_LBZ,
	86	+ 1,
	87	+ 0,
	88	+ 0,
	89	+ 1
	90	+ },
	91	+ {
	92	+ OP_LWZU,
	93	+ 4,
	94	+ 1,
	95	+ 0,
	96	+ 4
	97	+ },
	98	+ {
	99	+ OP_LHAU,
	100	+ 3,
	101	+ 1,
	102	+ 0,
	103	+ 2
	104	+ },
	105	+ {
	106	+ OP_LHZU,
	107	+ 2,
	108	+ 1,
	109	+ 0,
	110	+ 2
	111	+ },
	112	+ {
	113	+ OP_LBZU,
	114	+ 1,
	115	+ 1,
	116	+ 0,
	117	+ 1
	118	+ },
	119	+ {
	120	+ OP_LWZX,
	121	+ 4,
	122	+ 0,
	123	+ 1,
	124	+ 4
	125	+ },
	126	+ {
	127	+ OP_LHAX,
	128	+ 3,
	129	+ 0,
	130	+ 1,
	131	+ 2
	132	+ },
	133	+ {
	134	+ OP_LHZX,
	135	+ 2,
	136	+ 0,
	137	+ 1,
	138	+ 2
	139	+ },
	140	+ {
	141	+ OP_LBZX,
	142	+ 1,
	143	+ 0,
	144	+ 1,
	145	+ 1
	146	+ },
	147	+ {
	148	+ OP_LWZUX,
	149	+ 4,
	150	+ 1,
	151	+ 1,
	152	+ 4
	153	+ },
	154	+ {
	155	+ OP_LHAUX,
	156	+ 3,
	157	+ 1,
	158	+ 1,
	159	+ 2
	160	+ },
	161	+ {
	162	+ OP_LHZUX,
	163	+ 2,
	164	+ 1,
	165	+ 1,
	166	+ 2
	167	+ },
	168	+ {
	169	+ OP_LBZUX,
	170	+ 1,
	171	+ 1,
	172	+ 1,
	173	+ 1
	174	+ },
	175	+};
	176	+static unsigned int cpu_post_load_size =
	177	+ sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s);
	178	+
	179	+int cpu_post_test_load (void)
	180	+{
	181	+ int ret = 0;
	182	+ unsigned int i;
	183	+
	184	+ for (i = 0; i < cpu_post_load_size && ret == 0; i++)
	185	+ {
	186	+ struct cpu_post_load_s *test = cpu_post_load_table + i;
	187	+ uchar data[16] =
	188	+ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
	189	+ ulong base0 = (ulong) (data + 8);
	190	+ ulong base = base0;
	191	+ ulong value;
	192	+
	193	+ if (test->index)
	194	+ {
	195	+ ulong code[] =
	196	+ {
	197	+ ASM_12(test->cmd, 5, 3, 4),
	198	+ ASM_BLR,
	199	+ };
	200	+
	201	+ cpu_post_exec_22w (code, &base, test->offset, &value);
	202	+ }
	203	+ else
	204	+ {
	205	+ ulong code[] =
	206	+ {
	207	+ ASM_11I(test->cmd, 4, 3, test->offset),
	208	+ ASM_BLR,
	209	+ };
	210	+
	211	+ cpu_post_exec_21w (code, &base, &value);
	212	+ }
	213	+
	214	+ if (ret == 0)
	215	+ {
	216	+ if (test->update)
	217	+ ret = base == base0 + test->offset ? 0 : -1;
	218	+ else
	219	+ ret = base == base0 ? 0 : -1;
	220	+ }
	221	+
	222	+ if (ret == 0)
	223	+ {
	224	+ switch (test->width)
	225	+ {
	226	+ case 1:
	227	+ ret = (uchar )(base0 + test->offset) == value ?
	228	+ 0 : -1;
	229	+ break;
	230	+ case 2:
	231	+ ret = (ushort )(base0 + test->offset) == value ?
	232	+ 0 : -1;
	233	+ break;
	234	+ case 3:
	235	+ ret = (short )(base0 + test->offset) == value ?
	236	+ 0 : -1;
	237	+ break;
	238	+ case 4:
	239	+ ret = (ulong )(base0 + test->offset) == value ?
	240	+ 0 : -1;
	241	+ break;
	242	+ }
	243	+ }
	244	+
	245	+ if (ret != 0)
	246	+ {
	247	+ post_log ("Error at load test %d !\n", i);
	248	+ }
	249	+ }
	250	+
	251	+ return ret;
	252	+}
	253	+
	254	+#endif
	255	+#endif

post/cpu/multi.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Load/store multiple word instructions: lmw, stmw
	29	+ *
	30	+ * 26 consecutive words are loaded from a source memory buffer
	31	+ * into GPRs r6 through r31. After that, 26 consecutive words are stored
	32	+ * from the GPRs r6 through r31 into a target memory buffer. The contents
	33	+ * of the source and target buffers are then compared.
	34	+ */
	35	+
	36	+#ifdef CONFIG_POST
	37	+
	38	+#include <post.h>
	39	+#include "cpu_asm.h"
	40	+
	41	+#if CONFIG_POST & CFG_POST_CPU
	42	+
	43	+extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2);
	44	+
	45	+int cpu_post_test_multi (void)
	46	+{
	47	+ int ret = 0;
	48	+ unsigned int i;
	49	+
	50	+ if (ret == 0)
	51	+ {
	52	+ ulong src [26], dst [26];
	53	+
	54	+ ulong code[] =
	55	+ {
	56	+ ASM_LMW(5, 3, 0),
	57	+ ASM_STMW(5, 4, 0),
	58	+ ASM_BLR,
	59	+ };
	60	+
	61	+ for (i = 0; i < sizeof(src) / sizeof(src[0]); i ++)
	62	+ {
	63	+ src[i] = i;
	64	+ dst[i] = 0;
	65	+ }
	66	+
	67	+ cpu_post_exec_02(code, (ulong)src, (ulong)dst);
	68	+
	69	+ ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1;
	70	+ }
	71	+
	72	+ if (ret != 0)
	73	+ {
	74	+ post_log ("Error at multi test !\n");
	75	+ }
	76	+
	77	+ return ret;
	78	+}
	79	+
	80	+#endif
	81	+#endif

post/cpu/rlwimi.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Shift instructions: rlwimi
	29	+ *
	30	+ * The test contains a pre-built table of instructions, operands and
	31	+ * expected results. For each table entry, the test will cyclically use
	32	+ * different sets of operand registers and result registers.
	33	+ */
	34	+
	35	+#ifdef CONFIG_POST
	36	+
	37	+#include <post.h>
	38	+#include "cpu_asm.h"
	39	+
	40	+#if CONFIG_POST & CFG_POST_CPU
	41	+
	42	+extern void cpu_post_exec_22 (ulong code, ulong cr, ulong *res, ulong op1,
	43	+ ulong op2);
	44	+extern ulong cpu_post_makecr (long v);
	45	+
	46	+static struct cpu_post_rlwimi_s
	47	+{
	48	+ ulong cmd;
	49	+ ulong op0;
	50	+ ulong op1;
	51	+ uchar op2;
	52	+ uchar mb;
	53	+ uchar me;
	54	+ ulong res;
	55	+} cpu_post_rlwimi_table[] =
	56	+{
	57	+ {
	58	+ OP_RLWIMI,
	59	+ 0xff00ffff,
	60	+ 0x0000aa00,
	61	+ 8,
	62	+ 8,
	63	+ 15,
	64	+ 0xffaaffff
	65	+ },
	66	+};
	67	+static unsigned int cpu_post_rlwimi_size =
	68	+ sizeof (cpu_post_rlwimi_table) / sizeof (struct cpu_post_rlwimi_s);
	69	+
	70	+int cpu_post_test_rlwimi (void)
	71	+{
	72	+ int ret = 0;
	73	+ unsigned int i, reg;
	74	+ int flag = disable_interrupts();
	75	+
	76	+ for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++)
	77	+ {
	78	+ struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i;
	79	+
	80	+ for (reg = 0; reg < 32 && ret == 0; reg++)
	81	+ {
	82	+ unsigned int reg0 = (reg + 0) % 32;
	83	+ unsigned int reg1 = (reg + 1) % 32;
	84	+ unsigned int stk = reg < 16 ? 31 : 15;
	85	+ unsigned long code[] =
	86	+ {
	87	+ ASM_STW(stk, 1, -4),
	88	+ ASM_ADDI(stk, 1, -20),
	89	+ ASM_STW(3, stk, 8),
	90	+ ASM_STW(4, stk, 12),
	91	+ ASM_STW(reg0, stk, 4),
	92	+ ASM_STW(reg1, stk, 0),
	93	+ ASM_LWZ(reg1, stk, 8),
	94	+ ASM_LWZ(reg0, stk, 12),
	95	+ ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
	96	+ ASM_STW(reg1, stk, 8),
	97	+ ASM_LWZ(reg1, stk, 0),
	98	+ ASM_LWZ(reg0, stk, 4),
	99	+ ASM_LWZ(3, stk, 8),
	100	+ ASM_ADDI(1, stk, 20),
	101	+ ASM_LWZ(stk, 1, -4),
	102	+ ASM_BLR,
	103	+ };
	104	+ unsigned long codecr[] =
	105	+ {
	106	+ ASM_STW(stk, 1, -4),
	107	+ ASM_ADDI(stk, 1, -20),
	108	+ ASM_STW(3, stk, 8),
	109	+ ASM_STW(4, stk, 12),
	110	+ ASM_STW(reg0, stk, 4),
	111	+ ASM_STW(reg1, stk, 0),
	112	+ ASM_LWZ(reg1, stk, 8),
	113	+ ASM_LWZ(reg0, stk, 12),
	114	+ ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) \|
	115	+ BIT_C,
	116	+ ASM_STW(reg1, stk, 8),
	117	+ ASM_LWZ(reg1, stk, 0),
	118	+ ASM_LWZ(reg0, stk, 4),
	119	+ ASM_LWZ(3, stk, 8),
	120	+ ASM_ADDI(1, stk, 20),
	121	+ ASM_LWZ(stk, 1, -4),
	122	+ ASM_BLR,
	123	+ };
	124	+ ulong res;
	125	+ ulong cr;
	126	+
	127	+ if (ret == 0)
	128	+ {
	129	+ cr = 0;
	130	+ cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
	131	+
	132	+ ret = res == test->res && cr == 0 ? 0 : -1;
	133	+
	134	+ if (ret != 0)
	135	+ {
	136	+ post_log ("Error at rlwimi test %d !\n", i);
	137	+ }
	138	+ }
	139	+
	140	+ if (ret == 0)
	141	+ {
	142	+ cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
	143	+
	144	+ ret = res == test->res &&
	145	+ (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
	146	+
	147	+ if (ret != 0)
	148	+ {
	149	+ post_log ("Error at rlwimi test %d !\n", i);
	150	+ }
	151	+ }
	152	+ }
	153	+ }
	154	+
	155	+ if (flag)
	156	+ enable_interrupts();
	157	+
	158	+ return ret;
	159	+}
	160	+
	161	+#endif
	162	+#endif

post/cpu/rlwinm.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Shift instructions: rlwinm
	29	+ *
	30	+ * The test contains a pre-built table of instructions, operands and
	31	+ * expected results. For each table entry, the test will cyclically use
	32	+ * different sets of operand registers and result registers.
	33	+ */
	34	+
	35	+#ifdef CONFIG_POST
	36	+
	37	+#include <post.h>
	38	+#include "cpu_asm.h"
	39	+
	40	+#if CONFIG_POST & CFG_POST_CPU
	41	+
	42	+extern void cpu_post_exec_21 (ulong code, ulong cr, ulong *res, ulong op1);
	43	+extern ulong cpu_post_makecr (long v);
	44	+
	45	+static struct cpu_post_rlwinm_s
	46	+{
	47	+ ulong cmd;
	48	+ ulong op1;
	49	+ uchar op2;
	50	+ uchar mb;
	51	+ uchar me;
	52	+ ulong res;
	53	+} cpu_post_rlwinm_table[] =
	54	+{
	55	+ {
	56	+ OP_RLWINM,
	57	+ 0xffff0000,
	58	+ 24,
	59	+ 16,
	60	+ 23,
	61	+ 0x0000ff00
	62	+ },
	63	+};
	64	+static unsigned int cpu_post_rlwinm_size =
	65	+ sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s);
	66	+
	67	+int cpu_post_test_rlwinm (void)
	68	+{
	69	+ int ret = 0;
	70	+ unsigned int i, reg;
	71	+ int flag = disable_interrupts();
	72	+
	73	+ for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
	74	+ {
	75	+ struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
	76	+
	77	+ for (reg = 0; reg < 32 && ret == 0; reg++)
	78	+ {
	79	+ unsigned int reg0 = (reg + 0) % 32;
	80	+ unsigned int reg1 = (reg + 1) % 32;
	81	+ unsigned int stk = reg < 16 ? 31 : 15;
	82	+ unsigned long code[] =
	83	+ {
	84	+ ASM_STW(stk, 1, -4),
	85	+ ASM_ADDI(stk, 1, -16),
	86	+ ASM_STW(3, stk, 8),
	87	+ ASM_STW(reg0, stk, 4),
	88	+ ASM_STW(reg1, stk, 0),
	89	+ ASM_LWZ(reg0, stk, 8),
	90	+ ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
	91	+ ASM_STW(reg1, stk, 8),
	92	+ ASM_LWZ(reg1, stk, 0),
	93	+ ASM_LWZ(reg0, stk, 4),
	94	+ ASM_LWZ(3, stk, 8),
	95	+ ASM_ADDI(1, stk, 16),
	96	+ ASM_LWZ(stk, 1, -4),
	97	+ ASM_BLR,
	98	+ };
	99	+ unsigned long codecr[] =
	100	+ {
	101	+ ASM_STW(stk, 1, -4),
	102	+ ASM_ADDI(stk, 1, -16),
	103	+ ASM_STW(3, stk, 8),
	104	+ ASM_STW(reg0, stk, 4),
	105	+ ASM_STW(reg1, stk, 0),
	106	+ ASM_LWZ(reg0, stk, 8),
	107	+ ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
	108	+ test->me) \| BIT_C,
	109	+ ASM_STW(reg1, stk, 8),
	110	+ ASM_LWZ(reg1, stk, 0),
	111	+ ASM_LWZ(reg0, stk, 4),
	112	+ ASM_LWZ(3, stk, 8),
	113	+ ASM_ADDI(1, stk, 16),
	114	+ ASM_LWZ(stk, 1, -4),
	115	+ ASM_BLR,
	116	+ };
	117	+ ulong res;
	118	+ ulong cr;
	119	+
	120	+ if (ret == 0)
	121	+ {
	122	+ cr = 0;
	123	+ cpu_post_exec_21 (code, & cr, & res, test->op1);
	124	+
	125	+ ret = res == test->res && cr == 0 ? 0 : -1;
	126	+
	127	+ if (ret != 0)
	128	+ {
	129	+ post_log ("Error at rlwinm test %d !\n", i);
	130	+ }
	131	+ }
	132	+
	133	+ if (ret == 0)
	134	+ {
	135	+ cpu_post_exec_21 (codecr, & cr, & res, test->op1);
	136	+
	137	+ ret = res == test->res &&
	138	+ (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
	139	+
	140	+ if (ret != 0)
	141	+ {
	142	+ post_log ("Error at rlwinm test %d !\n", i);
	143	+ }
	144	+ }
	145	+ }
	146	+ }
	147	+
	148	+ if (flag)
	149	+ enable_interrupts();
	150	+
	151	+ return ret;
	152	+}
	153	+
	154	+#endif
	155	+#endif

post/cpu/rlwnm.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Shift instructions: rlwnm
	29	+ *
	30	+ * The test contains a pre-built table of instructions, operands and
	31	+ * expected results. For each table entry, the test will cyclically use
	32	+ * different sets of operand registers and result registers.
	33	+ */
	34	+
	35	+#ifdef CONFIG_POST
	36	+
	37	+#include <post.h>
	38	+#include "cpu_asm.h"
	39	+
	40	+#if CONFIG_POST & CFG_POST_CPU
	41	+
	42	+extern void cpu_post_exec_22 (ulong code, ulong cr, ulong *res, ulong op1,
	43	+ ulong op2);
	44	+extern ulong cpu_post_makecr (long v);
	45	+
	46	+static struct cpu_post_rlwnm_s
	47	+{
	48	+ ulong cmd;
	49	+ ulong op1;
	50	+ ulong op2;
	51	+ uchar mb;
	52	+ uchar me;
	53	+ ulong res;
	54	+} cpu_post_rlwnm_table[] =
	55	+{
	56	+ {
	57	+ OP_RLWNM,
	58	+ 0xffff0000,
	59	+ 24,
	60	+ 16,
	61	+ 23,
	62	+ 0x0000ff00
	63	+ },
	64	+};
	65	+static unsigned int cpu_post_rlwnm_size =
	66	+ sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s);
	67	+
	68	+int cpu_post_test_rlwnm (void)
	69	+{
	70	+ int ret = 0;
	71	+ unsigned int i, reg;
	72	+ int flag = disable_interrupts();
	73	+
	74	+ for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
	75	+ {
	76	+ struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
	77	+
	78	+ for (reg = 0; reg < 32 && ret == 0; reg++)
	79	+ {
	80	+ unsigned int reg0 = (reg + 0) % 32;
	81	+ unsigned int reg1 = (reg + 1) % 32;
	82	+ unsigned int reg2 = (reg + 2) % 32;
	83	+ unsigned int stk = reg < 16 ? 31 : 15;
	84	+ unsigned long code[] =
	85	+ {
	86	+ ASM_STW(stk, 1, -4),
	87	+ ASM_ADDI(stk, 1, -24),
	88	+ ASM_STW(3, stk, 12),
	89	+ ASM_STW(4, stk, 16),
	90	+ ASM_STW(reg0, stk, 8),
	91	+ ASM_STW(reg1, stk, 4),
	92	+ ASM_STW(reg2, stk, 0),
	93	+ ASM_LWZ(reg1, stk, 12),
	94	+ ASM_LWZ(reg0, stk, 16),
	95	+ ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
	96	+ ASM_STW(reg2, stk, 12),
	97	+ ASM_LWZ(reg2, stk, 0),
	98	+ ASM_LWZ(reg1, stk, 4),
	99	+ ASM_LWZ(reg0, stk, 8),
	100	+ ASM_LWZ(3, stk, 12),
	101	+ ASM_ADDI(1, stk, 24),
	102	+ ASM_LWZ(stk, 1, -4),
	103	+ ASM_BLR,
	104	+ };
	105	+ unsigned long codecr[] =
	106	+ {
	107	+ ASM_STW(stk, 1, -4),
	108	+ ASM_ADDI(stk, 1, -24),
	109	+ ASM_STW(3, stk, 12),
	110	+ ASM_STW(4, stk, 16),
	111	+ ASM_STW(reg0, stk, 8),
	112	+ ASM_STW(reg1, stk, 4),
	113	+ ASM_STW(reg2, stk, 0),
	114	+ ASM_LWZ(reg1, stk, 12),
	115	+ ASM_LWZ(reg0, stk, 16),
	116	+ ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) \|
	117	+ BIT_C,
	118	+ ASM_STW(reg2, stk, 12),
	119	+ ASM_LWZ(reg2, stk, 0),
	120	+ ASM_LWZ(reg1, stk, 4),
	121	+ ASM_LWZ(reg0, stk, 8),
	122	+ ASM_LWZ(3, stk, 12),
	123	+ ASM_ADDI(1, stk, 24),
	124	+ ASM_LWZ(stk, 1, -4),
	125	+ ASM_BLR,
	126	+ };
	127	+ ulong res;
	128	+ ulong cr;
	129	+
	130	+ if (ret == 0)
	131	+ {
	132	+ cr = 0;
	133	+ cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
	134	+
	135	+ ret = res == test->res && cr == 0 ? 0 : -1;
	136	+
	137	+ if (ret != 0)
	138	+ {
	139	+ post_log ("Error at rlwnm test %d !\n", i);
	140	+ }
	141	+ }
	142	+
	143	+ if (ret == 0)
	144	+ {
	145	+ cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
	146	+
	147	+ ret = res == test->res &&
	148	+ (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
	149	+
	150	+ if (ret != 0)
	151	+ {
	152	+ post_log ("Error at rlwnm test %d !\n", i);
	153	+ }
	154	+ }
	155	+ }
	156	+ }
	157	+
	158	+ if (flag)
	159	+ enable_interrupts();
	160	+
	161	+ return ret;
	162	+}
	163	+
	164	+#endif
	165	+#endif

post/cpu/srawi.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Shift instructions: srawi
	29	+ *
	30	+ * The test contains a pre-built table of instructions, operands and
	31	+ * expected results. For each table entry, the test will cyclically use
	32	+ * different sets of operand registers and result registers.
	33	+ */
	34	+
	35	+#ifdef CONFIG_POST
	36	+
	37	+#include <post.h>
	38	+#include "cpu_asm.h"
	39	+
	40	+#if CONFIG_POST & CFG_POST_CPU
	41	+
	42	+extern void cpu_post_exec_21 (ulong code, ulong cr, ulong *res, ulong op);
	43	+extern ulong cpu_post_makecr (long v);
	44	+
	45	+static struct cpu_post_srawi_s
	46	+{
	47	+ ulong cmd;
	48	+ ulong op1;
	49	+ uchar op2;
	50	+ ulong res;
	51	+} cpu_post_srawi_table[] =
	52	+{
	53	+ {
	54	+ OP_SRAWI,
	55	+ 0x8000,
	56	+ 3,
	57	+ 0x1000
	58	+ },
	59	+ {
	60	+ OP_SRAWI,
	61	+ 0x80000000,
	62	+ 3,
	63	+ 0xf0000000
	64	+ },
	65	+};
	66	+static unsigned int cpu_post_srawi_size =
	67	+ sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s);
	68	+
	69	+int cpu_post_test_srawi (void)
	70	+{
	71	+ int ret = 0;
	72	+ unsigned int i, reg;
	73	+ int flag = disable_interrupts();
	74	+
	75	+ for (i = 0; i < cpu_post_srawi_size && ret == 0; i++)
	76	+ {
	77	+ struct cpu_post_srawi_s *test = cpu_post_srawi_table + i;
	78	+
	79	+ for (reg = 0; reg < 32 && ret == 0; reg++)
	80	+ {
	81	+ unsigned int reg0 = (reg + 0) % 32;
	82	+ unsigned int reg1 = (reg + 1) % 32;
	83	+ unsigned int stk = reg < 16 ? 31 : 15;
	84	+ unsigned long code[] =
	85	+ {
	86	+ ASM_STW(stk, 1, -4),
	87	+ ASM_ADDI(stk, 1, -16),
	88	+ ASM_STW(3, stk, 8),
	89	+ ASM_STW(reg0, stk, 4),
	90	+ ASM_STW(reg1, stk, 0),
	91	+ ASM_LWZ(reg0, stk, 8),
	92	+ ASM_11S(test->cmd, reg1, reg0, test->op2),
	93	+ ASM_STW(reg1, stk, 8),
	94	+ ASM_LWZ(reg1, stk, 0),
	95	+ ASM_LWZ(reg0, stk, 4),
	96	+ ASM_LWZ(3, stk, 8),
	97	+ ASM_ADDI(1, stk, 16),
	98	+ ASM_LWZ(stk, 1, -4),
	99	+ ASM_BLR,
	100	+ };
	101	+ unsigned long codecr[] =
	102	+ {
	103	+ ASM_STW(stk, 1, -4),
	104	+ ASM_ADDI(stk, 1, -16),
	105	+ ASM_STW(3, stk, 8),
	106	+ ASM_STW(reg0, stk, 4),
	107	+ ASM_STW(reg1, stk, 0),
	108	+ ASM_LWZ(reg0, stk, 8),
	109	+ ASM_11S(test->cmd, reg1, reg0, test->op2) \| BIT_C,
	110	+ ASM_STW(reg1, stk, 8),
	111	+ ASM_LWZ(reg1, stk, 0),
	112	+ ASM_LWZ(reg0, stk, 4),
	113	+ ASM_LWZ(3, stk, 8),
	114	+ ASM_ADDI(1, stk, 16),
	115	+ ASM_LWZ(stk, 1, -4),
	116	+ ASM_BLR,
	117	+ };
	118	+ ulong res;
	119	+ ulong cr;
	120	+
	121	+ if (ret == 0)
	122	+ {
	123	+ cr = 0;
	124	+ cpu_post_exec_21 (code, & cr, & res, test->op1);
	125	+
	126	+ ret = res == test->res && cr == 0 ? 0 : -1;
	127	+
	128	+ if (ret != 0)
	129	+ {
	130	+ post_log ("Error at srawi test %d !\n", i);
	131	+ }
	132	+ }
	133	+
	134	+ if (ret == 0)
	135	+ {
	136	+ cpu_post_exec_21 (codecr, & cr, & res, test->op1);
	137	+
	138	+ ret = res == test->res &&
	139	+ (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
	140	+
	141	+ if (ret != 0)
	142	+ {
	143	+ post_log ("Error at srawi test %d !\n", i);
	144	+ }
	145	+ }
	146	+ }
	147	+ }
	148	+
	149	+ if (flag)
	150	+ enable_interrupts();
	151	+
	152	+ return ret;
	153	+}
	154	+
	155	+#endif
	156	+#endif

post/cpu/store.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u)
	29	+ *
	30	+ * All operations are performed on a 16-byte array. The array
	31	+ * is 4-byte aligned. The base register points to offset 8.
	32	+ * The immediate offset (index register) ranges in [-8 ... +7].
	33	+ * The test cases are composed so that they do not
	34	+ * cause alignment exceptions.
	35	+ * The test contains a pre-built table describing all test cases.
	36	+ * The table entry contains:
	37	+ * the instruction opcode, the value of the index register and
	38	+ * the value of the source register. After executing the
	39	+ * instruction, the test verifies the contents of the array
	40	+ * and the value of the base register (it must change for "store
	41	+ * with update" instructions).
	42	+ */
	43	+
	44	+#ifdef CONFIG_POST
	45	+
	46	+#include <post.h>
	47	+#include "cpu_asm.h"
	48	+
	49	+#if CONFIG_POST & CFG_POST_CPU
	50	+
	51	+extern void cpu_post_exec_12w (ulong code, ulong op1, ulong op2, ulong op3);
	52	+extern void cpu_post_exec_11w (ulong code, ulong op1, ulong op2);
	53	+
	54	+static struct cpu_post_store_s
	55	+{
	56	+ ulong cmd;
	57	+ uint width;
	58	+ int update;
	59	+ int index;
	60	+ ulong offset;
	61	+ ulong value;
	62	+} cpu_post_store_table[] =
	63	+{
	64	+ {
	65	+ OP_STW,
	66	+ 4,
	67	+ 0,
	68	+ 0,
	69	+ -4,
	70	+ 0xff00ff00
	71	+ },
	72	+ {
	73	+ OP_STH,
	74	+ 2,
	75	+ 0,
	76	+ 0,
	77	+ -2,
	78	+ 0xff00
	79	+ },
	80	+ {
	81	+ OP_STB,
	82	+ 1,
	83	+ 0,
	84	+ 0,
	85	+ -1,
	86	+ 0xff
	87	+ },
	88	+ {
	89	+ OP_STWU,
	90	+ 4,
	91	+ 1,
	92	+ 0,
	93	+ -4,
	94	+ 0xff00ff00
	95	+ },
	96	+ {
	97	+ OP_STHU,
	98	+ 2,
	99	+ 1,
	100	+ 0,
	101	+ -2,
	102	+ 0xff00
	103	+ },
	104	+ {
	105	+ OP_STBU,
	106	+ 1,
	107	+ 1,
	108	+ 0,
	109	+ -1,
	110	+ 0xff
	111	+ },
	112	+ {
	113	+ OP_STWX,
	114	+ 4,
	115	+ 0,
	116	+ 1,
	117	+ -4,
	118	+ 0xff00ff00
	119	+ },
	120	+ {
	121	+ OP_STHX,
	122	+ 2,
	123	+ 0,
	124	+ 1,
	125	+ -2,
	126	+ 0xff00
	127	+ },
	128	+ {
	129	+ OP_STBX,
	130	+ 1,
	131	+ 0,
	132	+ 1,
	133	+ -1,
	134	+ 0xff
	135	+ },
	136	+ {
	137	+ OP_STWUX,
	138	+ 4,
	139	+ 1,
	140	+ 1,
	141	+ -4,
	142	+ 0xff00ff00
	143	+ },
	144	+ {
	145	+ OP_STHUX,
	146	+ 2,
	147	+ 1,
	148	+ 1,
	149	+ -2,
	150	+ 0xff00
	151	+ },
	152	+ {
	153	+ OP_STBUX,
	154	+ 1,
	155	+ 1,
	156	+ 1,
	157	+ -1,
	158	+ 0xff
	159	+ },
	160	+};
	161	+static unsigned int cpu_post_store_size =
	162	+ sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s);
	163	+
	164	+int cpu_post_test_store (void)
	165	+{
	166	+ int ret = 0;
	167	+ unsigned int i;
	168	+
	169	+ for (i = 0; i < cpu_post_store_size && ret == 0; i++)
	170	+ {
	171	+ struct cpu_post_store_s *test = cpu_post_store_table + i;
	172	+ uchar data[16] =
	173	+ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
	174	+ ulong base0 = (ulong) (data + 8);
	175	+ ulong base = base0;
	176	+
	177	+ if (test->index)
	178	+ {
	179	+ ulong code[] =
	180	+ {
	181	+ ASM_12(test->cmd, 5, 3, 4),
	182	+ ASM_BLR,
	183	+ };
	184	+
	185	+ cpu_post_exec_12w (code, &base, test->offset, test->value);
	186	+ }
	187	+ else
	188	+ {
	189	+ ulong code[] =
	190	+ {
	191	+ ASM_11I(test->cmd, 4, 3, test->offset),
	192	+ ASM_BLR,
	193	+ };
	194	+
	195	+ cpu_post_exec_11w (code, &base, test->value);
	196	+ }
	197	+
	198	+ if (ret == 0)
	199	+ {
	200	+ if (test->update)
	201	+ ret = base == base0 + test->offset ? 0 : -1;
	202	+ else
	203	+ ret = base == base0 ? 0 : -1;
	204	+ }
	205	+
	206	+ if (ret == 0)
	207	+ {
	208	+ switch (test->width)
	209	+ {
	210	+ case 1:
	211	+ ret = (uchar )(base0 + test->offset) == test->value ?
	212	+ 0 : -1;
	213	+ break;
	214	+ case 2:
	215	+ ret = (ushort )(base0 + test->offset) == test->value ?
	216	+ 0 : -1;
	217	+ break;
	218	+ case 4:
	219	+ ret = (ulong )(base0 + test->offset) == test->value ?
	220	+ 0 : -1;
	221	+ break;
	222	+ }
	223	+ }
	224	+
	225	+ if (ret != 0)
	226	+ {
	227	+ post_log ("Error at store test %d !\n", i);
	228	+ }
	229	+ }
	230	+
	231	+ return ret;
	232	+}
	233	+
	234	+#endif
	235	+#endif

post/cpu/string.c

Diff comments View file @ a46d821

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+
	26	+/*
	27	+ * CPU test
	28	+ * Load/store string instructions: lswi, stswi, lswx, stswx
	29	+ *
	30	+ * Several consecutive bytes from a source memory buffer are loaded
	31	+ * left to right into GPRs. After that, the bytes are stored
	32	+ * from the GPRs into a target memory buffer. The contents
	33	+ * of the source and target buffers are then compared.
	34	+ */
	35	+
	36	+#ifdef CONFIG_POST
	37	+
	38	+#include <post.h>
	39	+#include "cpu_asm.h"
	40	+
	41	+#if CONFIG_POST & CFG_POST_CPU
	42	+
	43	+extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2);
	44	+extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3,
	45	+ ulong op4);
	46	+
	47	+#include <bedbug/regs.h>
	48	+int cpu_post_test_string (void)
	49	+{
	50	+ int ret = 0;
	51	+ unsigned int i;
	52	+
	53	+ if (ret == 0)
	54	+ {
	55	+ char src [31], dst [31];
	56	+
	57	+ ulong code[] =
	58	+ {
	59	+ ASM_LSWI(5, 3, 31),
	60	+ ASM_STSWI(5, 4, 31),
	61	+ ASM_BLR,
	62	+ };
	63	+
	64	+ for (i = 0; i < sizeof(src); i ++)
	65	+ {
	66	+ src[i] = (char) i;
	67	+ dst[i] = 0;
	68	+ }
	69	+
	70	+ cpu_post_exec_02(code, (ulong)src, (ulong)dst);
	71	+
	72	+ ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1;
	73	+ }
	74	+
	75	+ if (ret == 0)
	76	+ {
	77	+ char src [95], dst [95];
	78	+
	79	+ ulong code[] =
	80	+ {
	81	+ ASM_LSWX(8, 3, 5),
	82	+ ASM_STSWX(8, 4, 5),
	83	+ ASM_BLR,
	84	+ };
	85	+
	86	+ for (i = 0; i < sizeof(src); i ++)
	87	+ {
	88	+ src[i] = (char) i;
	89	+ dst[i] = 0;
	90	+ }
	91	+
	92	+ cpu_post_exec_04(code, (ulong)src, (ulong)dst, 0, sizeof(src));
	93	+
	94	+ ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1;
	95	+ }
	96	+
	97	+ if (ret != 0)
	98	+ {
	99	+ post_log ("Error at string test !\n");
	100	+ }
	101	+
	102	+ return ret;
	103	+}
	104	+
	105	+#endif
	106	+#endif