Merge branch 'master' of git://git.denx.de/u-boot-usb

Tom Rini
2 parents c2774e6149 3426b2038c
Showing 4 changed files Side-by-side Diff
drivers/usb/eth/mcs7830.c
drivers/usb/host/Kconfig
drivers/usb/host/Makefile
drivers/usb/host/ehci-rcar_gen3.c
@@ -622,10 +622,12 @@
 	int len;
  
 	len = mcs7830_recv_common(ueth, buf);
-	if (len <= 0)
+	if (len >= 0) {
 		net_process_received_packet(buf, len);
+		return 0;
+	}
  
-	return 0;
+	return len;
 }
  
 /*
@@ -133,6 +133,14 @@
 	  This driver supports combination of Chipidea USB controller
 	  and Synapsys USB PHY in host mode only.
  
+config USB_EHCI_RCAR_GEN3
+	bool "Support for Renesas RCar M3/H3 EHCI USB controller"
+	depends on RCAR_GEN3
+	default y
+	---help---
+	  Enables support for the on-chip EHCI controller on Renesas
+	  R8A7795 and R8A7796 SoCs.
+
 config USB_EHCI_ZYNQ
 	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
 	depends on ARCH_ZYNQ
@@ -51,6 +51,7 @@
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
+obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
  
 # xhci
+/*
+ * drivers/usb/host/ehci-rcar_gen3.
+ *	This file is EHCI HCD (Host Controller Driver) for USB.
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <usb/ehci-ci.h>
+#include "ehci.h"
+
+#define RCAR_GEN3_USB_BASE(n)	(0xEE080000 + ((n) * 0x20000))
+
+#define EHCI_USBCMD		0x120
+
+#define CORE_SPD_RSM_TIMSET	0x30c
+#define CORE_OC_TIMSET		0x310
+
+/* Register offset */
+#define AHB_OFFSET		0x200
+
+#define BASE_HSUSB		0xE6590000
+#define REG_LPSTS		(BASE_HSUSB + 0x0102)	/* 16bit */
+#define SUSPM			0x4000
+#define SUSPM_NORMAL		BIT(14)
+#define REG_UGCTRL2		(BASE_HSUSB + 0x0184)	/* 32bit */
+#define USB0SEL			0x00000030
+#define USB0SEL_EHCI		0x00000010
+
+#define SMSTPCR7		0xE615014C
+#define SMSTPCR700		BIT(0)	/* EHCI3 */
+#define SMSTPCR701		BIT(1)	/* EHCI2 */
+#define SMSTPCR702		BIT(2)	/* EHCI1 */
+#define SMSTPCR703		BIT(3)	/* EHCI0 */
+#define SMSTPCR704		BIT(4)	/* HSUSB */
+
+#define AHB_PLL_RST		BIT(1)
+
+#define USBH_INTBEN		BIT(2)
+#define USBH_INTAEN		BIT(1)
+
+#define AHB_INT_ENABLE		0x200
+#define AHB_USBCTR		0x20c
+
+int ehci_hcd_stop(int index)
+{
+#if defined(CONFIG_R8A7795)
+	const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
+#else
+	const u32 mask = SMSTPCR703 | SMSTPCR702;
+#endif
+	const u32 base = RCAR_GEN3_USB_BASE(index);
+	int ret;
+
+	/* Reset EHCI */
+	setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
+	ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
+			   CMD_RESET, false, 10, true);
+	if (ret) {
+		printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
+		       index, ret);
+	}
+
+	setbits_le32(SMSTPCR7, BIT(3 - index));
+
+	if ((readl(SMSTPCR7) & mask) == mask)
+		setbits_le32(SMSTPCR7, SMSTPCR704);
+
+	return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	const void __iomem *base =
+		(void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
+	struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
+
+	clrbits_le32(SMSTPCR7, BIT(3 - index));
+	clrbits_le32(SMSTPCR7, SMSTPCR704);
+
+	*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
+	*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
+			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+	/* Enable interrupt */
+	setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
+	writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
+	writel(0x000209ab, base + CORE_OC_TIMSET);
+
+	/* Choice USB0SEL */
+	clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
+
+	/* Clock & Reset */
+	clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
+
+	/* low power status */
+	clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
+
+	return 0;
+}
...	...	@@ -622,10 +622,12 @@
622	622	int len;
623	623
624	624	len = mcs7830_recv_common(ueth, buf);
625		- if (len <= 0)
	625	+ if (len >= 0) {
626	626	net_process_received_packet(buf, len);
	627	+ return 0;
	628	+ }
627	629
628		- return 0;
	630	+ return len;
629	631	}
630	632
631	633	/*
...	...	@@ -133,6 +133,14 @@
133	133	This driver supports combination of Chipidea USB controller
134	134	and Synapsys USB PHY in host mode only.
135	135
	136	+config USB_EHCI_RCAR_GEN3
	137	+ bool "Support for Renesas RCar M3/H3 EHCI USB controller"
	138	+ depends on RCAR_GEN3
	139	+ default y
	140	+ ---help---
	141	+ Enables support for the on-chip EHCI controller on Renesas
	142	+ R8A7795 and R8A7796 SoCs.
	143	+
136	144	config USB_EHCI_ZYNQ
137	145	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
138	146	depends on ARCH_ZYNQ
...	...	@@ -51,6 +51,7 @@
51	51	obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
52	52	obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
53	53	obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
	54	+obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
54	55	obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
55	56
56	57	# xhci
	1	+/*
	2	+ * drivers/usb/host/ehci-rcar_gen3.
	3	+ * This file is EHCI HCD (Host Controller Driver) for USB.
	4	+ *
	5	+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#include <common.h>
	11	+#include <errno.h>
	12	+#include <wait_bit.h>
	13	+#include <asm/io.h>
	14	+#include <usb/ehci-ci.h>
	15	+#include "ehci.h"
	16	+
	17	+#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
	18	+
	19	+#define EHCI_USBCMD 0x120
	20	+
	21	+#define CORE_SPD_RSM_TIMSET 0x30c
	22	+#define CORE_OC_TIMSET 0x310
	23	+
	24	+/* Register offset */
	25	+#define AHB_OFFSET 0x200
	26	+
	27	+#define BASE_HSUSB 0xE6590000
	28	+#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
	29	+#define SUSPM 0x4000
	30	+#define SUSPM_NORMAL BIT(14)
	31	+#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
	32	+#define USB0SEL 0x00000030
	33	+#define USB0SEL_EHCI 0x00000010
	34	+
	35	+#define SMSTPCR7 0xE615014C
	36	+#define SMSTPCR700 BIT(0) /* EHCI3 */
	37	+#define SMSTPCR701 BIT(1) /* EHCI2 */
	38	+#define SMSTPCR702 BIT(2) /* EHCI1 */
	39	+#define SMSTPCR703 BIT(3) /* EHCI0 */
	40	+#define SMSTPCR704 BIT(4) /* HSUSB */
	41	+
	42	+#define AHB_PLL_RST BIT(1)
	43	+
	44	+#define USBH_INTBEN BIT(2)
	45	+#define USBH_INTAEN BIT(1)
	46	+
	47	+#define AHB_INT_ENABLE 0x200
	48	+#define AHB_USBCTR 0x20c
	49	+
	50	+int ehci_hcd_stop(int index)
	51	+{
	52	+#if defined(CONFIG_R8A7795)
	53	+ const u32 mask = SMSTPCR703 \| SMSTPCR702 \| SMSTPCR701 \| SMSTPCR700;
	54	+#else
	55	+ const u32 mask = SMSTPCR703 \| SMSTPCR702;
	56	+#endif
	57	+ const u32 base = RCAR_GEN3_USB_BASE(index);
	58	+ int ret;
	59	+
	60	+ /* Reset EHCI */
	61	+ setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
	62	+ ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
	63	+ CMD_RESET, false, 10, true);
	64	+ if (ret) {
	65	+ printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
	66	+ index, ret);
	67	+ }
	68	+
	69	+ setbits_le32(SMSTPCR7, BIT(3 - index));
	70	+
	71	+ if ((readl(SMSTPCR7) & mask) == mask)
	72	+ setbits_le32(SMSTPCR7, SMSTPCR704);
	73	+
	74	+ return 0;
	75	+}
	76	+
	77	+int ehci_hcd_init(int index, enum usb_init_type init,
	78	+ struct ehci_hccr hccr, struct ehci_hcor hcor)
	79	+{
	80	+ const void __iomem *base =
	81	+ (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
	82	+ struct usb_ehci ehci = (struct usb_ehci )(uintptr_t)base;
	83	+
	84	+ clrbits_le32(SMSTPCR7, BIT(3 - index));
	85	+ clrbits_le32(SMSTPCR7, SMSTPCR704);
	86	+
	87	+ hccr = (struct ehci_hccr )((uintptr_t)&ehci->caplength);
	88	+ hcor = (struct ehci_hcor )((uintptr_t)*hccr +
	89	+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	90	+
	91	+ /* Enable interrupt */
	92	+ setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN \| USBH_INTAEN);
	93	+ writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
	94	+ writel(0x000209ab, base + CORE_OC_TIMSET);
	95	+
	96	+ /* Choice USB0SEL */
	97	+ clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
	98	+
	99	+ /* Clock & Reset */
	100	+ clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
	101	+
	102	+ /* low power status */
	103	+ clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
	104	+
	105	+ return 0;
	106	+}