Add support for PCS440EP board

Patch by Stefan Roese, 02 Jun 2006

Add support for PCS440EP board
Patch by Stefan Roese, 02 Jun 2006
Stefan Roese
1 parent 392c252efd
Showing 14 changed files with 1987 additions and 50 deletions Side-by-side Diff
CHANGELOG
MAINTAINERS
MAKEALL
Makefile
board/pcs440ep/Makefile
board/pcs440ep/config.mk
board/pcs440ep/flash.c
board/pcs440ep/init.S
board/pcs440ep/pcs440ep.c
board/pcs440ep/u-boot.lds
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/start.S
include/configs/pcs440ep.h
include/ppc440.h
@@ -7,6 +7,9 @@
   MPC8272 boards. Eventually this should be used on all boards?]
   Patch by Wolfgang Grandegger, 17 Jan 2006
  
+* Add support for PCS440EP board
+  Patch by Stefan Roese, 02 Jun 2006
+
 * Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
   Patch by Stefan Roese, 29 May 2006
  
@@ -283,6 +283,7 @@
 	ebony			PPC440GP
 	ocotea			PPC440GX
 	p3p440			PPC440GP
+	pcs440ep		PPC440EP
 	sycamore		PPC405GPr
 	walnut			PPC405GP
 	yellowstone		PPC440GR
@@ -71,11 +71,11 @@
 	HH405		HUB405		JSE		KAREF		\
 	luan		METROBOX	MIP405		MIP405T		\
 	ML2		ml300		ocotea		OCRTC		\
-	ORSG		p3p440		PCI405		PIP405		\
-	PLU405		PMC405	        PPChameleonEVB	sbc405		\
-	VOH405		VOM405          W7OLMC		W7OLMG		\
-	walnut		WUH405		XPEDITE1K	yellowstone	\
-	yosemite							\
+	ORSG		p3p440		PCI405		pcs440ep	\
+	PIP405		PLU405		PMC405	        PPChameleonEVB	\
+	sbc405		VOH405		VOM405          W7OLMC		\
+	W7OLMG		walnut		WUH405		XPEDITE1K	\
+	yellowstone	yosemite					\
 "
  
 #########################################################################
@@ -919,6 +919,9 @@
 PCI405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
  
+pcs440ep_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
+
 PIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
  
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PCS440EP board
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifndef CFG_FLASH_READ0
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	return (size_b0 + size_b1);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_SST020:	printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	volatile CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+        case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B:
+                info->flash_id += FLASH_AM040;
+                info->sector_count = 8;
+                info->size = 0x0080000; /* => 512 ko */
+                break;
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+		info->flash_id += FLASH_SST020;
+		info->sector_count = 64;
+		info->size = 0x00040000;
+		break;				/* => 256 kB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00001000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+
+				/* re-enable interrupts if necessary */
+				if (flag) {
+					enable_interrupts();
+					flag = 0;
+				}
+
+				/* data polling for D7 */
+				start = get_timer (0);
+				while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+				       (CFG_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+						return (1);
+				}
+			} else {
+				if (sect == s_first) {
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				}
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			}
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i)
+			data = (data << 8) | *src++;
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *)cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* PCI */
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* USB 2.0 Device */
+    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+    tlbtab_end
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static void set_leds(int val)
+{
+	unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+				 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+	out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
+}
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	set_leds(0);			/* display boot info counter */
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+	 * via define from board config file.
+	 *-------------------------------------------------------------------*/
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(uic0pr, 0xfffffe1f);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(sdr_pfc0, 0x00000100);	/* Pin function: enable GPIO49-63 */
+	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins, select IRQ5 */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	uint pbcr;
+	int size_val = 0;
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[1]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_ENV_ADDR_REDUND,
+			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: PCS440EP");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+	set_leds(1);			/* display boot info counter */
+	dram_size = spd_sdram();
+	set_leds(2);			/* display boot info counter */
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 EP PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* PCS440EP is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/pcs440ep/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  
@@ -101,7 +101,118 @@
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
  
+#if defined(CFG_440_GPIO_TABLE)
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
  
+void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
+{
+	unsigned char i=0, j=0, reg_offset = 0, gpio_core;
+	unsigned long gpio_reg, gpio_core_add;
+
+	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
+		j = 0;
+		reg_offset = 0;
+		/* GPIO config of the GPIOs 0 to 31 */
+		for (i=0; i<GPIO_MAX; i++, j++) {
+			if (i == GPIO_MAX/2) {
+				reg_offset = 4;
+				j = i-16;
+			}
+
+			gpio_core_add = (*gpio_tab)[gpio_core][i].add;
+
+			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
+			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
+
+				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
+				case GPIO_SEL:
+					break;
+
+				case GPIO_ALT1:
+					gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT2:
+					gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT3:
+					gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+					break;
+				}
+			}
+
+			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
+			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
+
+				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
+				case GPIO_SEL:
+					if (gpio_core == GPIO0) {
+						gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
+						out32(GPIO0_TCR, gpio_reg);
+					}
+
+					if (gpio_core == GPIO1) {
+						gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
+						out32(GPIO1_TCR, gpio_reg);
+					}
+
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT1:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT2:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT3:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+				}
+			}
+		}
+	}
+}
+#endif /* CFG_440_GPIO_TABLE */
+
 /*
  * Breath some life into the CPU...
  *
  
@@ -129,10 +240,16 @@
 	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 #endif /* CONFIG_405EP */
  
+#if defined(CFG_440_GPIO_TABLE)
+	set_chip_gpio_configuration(&gpio_tab);
+#endif /* CFG_440_GPIO_TABLE */
+
 	/*
 	 * External Bus Controller (EBC) Setup
 	 */
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+     defined(CONFIG_405EP) || defined(CONFIG_405))
 	/*
 	 * Move the next instructions into icache, since these modify the flash
 	 * we are running from!
@@ -148,6 +265,7 @@
 	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
 	asm volatile("	mtctr	3"		::: "ctr");
 	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
+#endif
  
 	mtebc(pb0ap, CFG_EBC_PB0AP);
 	mtebc(pb0cr, CFG_EBC_PB0CR);
@@ -1198,12 +1198,19 @@
 	.globl	relocate_code
 relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	dccci	0,0			    /* Invalidate data cache, now no longer our stack */
+	/*
+	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
+	 * to speed up the boot process. Now this cache needs to be disabled.
+	 */
+	iccci	0,0			/* Invalidate inst cache */
+	dccci	0,0			/* Invalidate data cache, now no longer our stack */
 	sync
+	isync
 	addi	r1,r0,0x0000		/* TLB entry #0 */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
+	sync
 	isync
 #endif
 	mr	r1,  r3		/* Set new stack pointer		*/
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * pcs440ep.h - configuration for PCS440EP board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK		/* no external clk used		*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define SPD_EEPROM_ADDRESS      {0x50, 0x51}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pcs440ep\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/pcs440ep/uImage\0"				\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff00000\0"					\
+	"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
+		"cp.b 100000 fff80000 80000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        2
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_USB	)
+
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
+
+#define CFG_FLASH		FLASH_BASE0_PRELIM
+#define CFG_SRAM		0xF1000000
+#define CFG_FPGA		0xF2000000
+#define CFG_CF1			0xF0000000
+#define CFG_CF2			0xF0100000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 1 (SRAM) initialization						*/
+#define CFG_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
+#define CFG_EBC_PB1CR		(CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CFG_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
+#define CFG_EBC_PB2CR		(CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 3 (CompactFlash) initialization					*/
+#define CFG_EBC_PB3AP		0x080BD400
+#define CFG_EBC_PB3CR		(CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 4 (CompactFlash) initialization					*/
+#define CFG_EBC_PB4AP		0x080BD400
+#define CFG_EBC_PB4CR		(CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /*		GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6	EBC_CS_N(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7	EBC_CS_N(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8	EBC_CS_N(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9	EBC_CS_N(4)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10	EBC_CS_N(5)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11	EBC_BUS_ERR			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12	ZII_p0Rxd(0)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13	ZII_p0Rxd(1)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14	ZII_p0Rxd(2)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15	ZII_p0Rxd(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16	ZII_p0Txd(0)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17	ZII_p0Txd(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18	ZII_p0Txd(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19	ZII_p0Txd(3)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20	ZII_p0Rx_er			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21	ZII_p0Rx_dv			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22	ZII_p0RxCrs			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23	ZII_p0Tx_er			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24	ZII_p0Tx_en			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25	ZII_p0Col			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26			USB2D_RXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28			USB2D_TXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32	USB2D_OPMODE0			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33	USB2D_OPMODE1			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37	UART0_RTS_N			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40	UIC_IRQ(0)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41	UIC_IRQ(1)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42	UIC_IRQ(2)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43	UIC_IRQ(3)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{ GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
@@ -1357,55 +1357,105 @@
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
+#define GPIO0			0
+#define GPIO1			1
+
 #if defined(CONFIG_440GP)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000700)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
  
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
  
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000B00)
-#define GPIO_BASE1             (CFG_PERIPHERAL_BASE+0x00000C00)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
  
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_OSRL             (GPIO_BASE0+0x8)
-#define GPIO0_OSRH             (GPIO_BASE0+0xC)
-#define GPIO0_TSRL             (GPIO_BASE0+0x10)
-#define GPIO0_TSRH             (GPIO_BASE0+0x14)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
-#define GPIO0_RR1              (GPIO_BASE0+0x20)
-#define GPIO0_RR2              (GPIO_BASE0+0x24)
-#define GPIO0_RR3	       (GPIO_BASE0+0x28)
-#define GPIO0_ISR1L            (GPIO_BASE0+0x30)
-#define GPIO0_ISR1H            (GPIO_BASE0+0x34)
-#define GPIO0_ISR2L            (GPIO_BASE0+0x38)
-#define GPIO0_ISR2H            (GPIO_BASE0+0x3C)
-#define GPIO0_ISR3L            (GPIO_BASE0+0x40)
-#define GPIO0_ISR3H            (GPIO_BASE0+0x44)
+/* Offsets */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
  
-#define GPIO1_OR               (GPIO_BASE1+0x0)
-#define GPIO1_TCR              (GPIO_BASE1+0x4)
-#define GPIO1_OSRL             (GPIO_BASE1+0x8)
-#define GPIO1_OSRH             (GPIO_BASE1+0xC)
-#define GPIO1_TSRL             (GPIO_BASE1+0x10)
-#define GPIO1_TSRH             (GPIO_BASE1+0x14)
-#define GPIO1_ODR              (GPIO_BASE1+0x18)
-#define GPIO1_IR               (GPIO_BASE1+0x1C)
-#define GPIO1_RR1              (GPIO_BASE1+0x20)
-#define GPIO1_RR2              (GPIO_BASE1+0x24)
-#define GPIO1_RR3              (GPIO_BASE1+0x28)
-#define GPIO1_ISR1L            (GPIO_BASE1+0x30)
-#define GPIO1_ISR1H            (GPIO_BASE1+0x34)
-#define GPIO1_ISR2L            (GPIO_BASE1+0x38)
-#define GPIO1_ISR2H            (GPIO_BASE1+0x3C)
-#define GPIO1_ISR3L            (GPIO_BASE1+0x40)
-#define GPIO1_ISR3H            (GPIO_BASE1+0x44)
+#define GPIO_OS(x)	(x+GPIOx_OSL)	/* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	/* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	/* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	/* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	/* GPIO Input register3 High or Low */
+
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_OSRL             (GPIO0_BASE+0x8)
+#define GPIO0_OSRH             (GPIO0_BASE+0xC)
+#define GPIO0_TSRL             (GPIO0_BASE+0x10)
+#define GPIO0_TSRH             (GPIO0_BASE+0x14)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
+#define GPIO0_RR1              (GPIO0_BASE+0x20)
+#define GPIO0_RR2              (GPIO0_BASE+0x24)
+#define GPIO0_RR3	       (GPIO0_BASE+0x28)
+#define GPIO0_ISR1L            (GPIO0_BASE+0x30)
+#define GPIO0_ISR1H            (GPIO0_BASE+0x34)
+#define GPIO0_ISR2L            (GPIO0_BASE+0x38)
+#define GPIO0_ISR2H            (GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L            (GPIO0_BASE+0x40)
+#define GPIO0_ISR3H            (GPIO0_BASE+0x44)
+
+#define GPIO1_OR               (GPIO1_BASE+0x0)
+#define GPIO1_TCR              (GPIO1_BASE+0x4)
+#define GPIO1_OSRL             (GPIO1_BASE+0x8)
+#define GPIO1_OSRH             (GPIO1_BASE+0xC)
+#define GPIO1_TSRL             (GPIO1_BASE+0x10)
+#define GPIO1_TSRH             (GPIO1_BASE+0x14)
+#define GPIO1_ODR              (GPIO1_BASE+0x18)
+#define GPIO1_IR               (GPIO1_BASE+0x1C)
+#define GPIO1_RR1              (GPIO1_BASE+0x20)
+#define GPIO1_RR2              (GPIO1_BASE+0x24)
+#define GPIO1_RR3              (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L            (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H            (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L            (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H            (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L            (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H            (GPIO1_BASE+0x44)
 #endif
+
+#define GPIO_GROUP_MAX	    2
+#define GPIO_MAX	    32
+#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
+#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+					    /* For the other GPIO number, you must shift */
+
+#ifndef __ASSEMBLY__
+
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long	add;	/* gpio core base address */
+	gpio_driver_t  in_out; /* Driver Setting */
+	gpio_select_t  alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+
+#endif /* __ASSEMBLY__ */
  
 /*
  * Macros for accessing the indirect EBC registers
...	...	@@ -7,6 +7,9 @@
7	7	MPC8272 boards. Eventually this should be used on all boards?]
8	8	Patch by Wolfgang Grandegger, 17 Jan 2006
9	9
	10	+* Add support for PCS440EP board
	11	+ Patch by Stefan Roese, 02 Jun 2006
	12	+
10	13	* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
11	14	Patch by Stefan Roese, 29 May 2006
12	15
...	...	@@ -283,6 +283,7 @@
283	283	ebony PPC440GP
284	284	ocotea PPC440GX
285	285	p3p440 PPC440GP
	286	+ pcs440ep PPC440EP
286	287	sycamore PPC405GPr
287	288	walnut PPC405GP
288	289	yellowstone PPC440GR
...	...	@@ -71,11 +71,11 @@
71	71	HH405 HUB405 JSE KAREF \
72	72	luan METROBOX MIP405 MIP405T \
73	73	ML2 ml300 ocotea OCRTC \
74		- ORSG p3p440 PCI405 PIP405 \
75		- PLU405 PMC405 PPChameleonEVB sbc405 \
76		- VOH405 VOM405 W7OLMC W7OLMG \
77		- walnut WUH405 XPEDITE1K yellowstone \
78		- yosemite \
	74	+ ORSG p3p440 PCI405 pcs440ep \
	75	+ PIP405 PLU405 PMC405 PPChameleonEVB \
	76	+ sbc405 VOH405 VOM405 W7OLMC \
	77	+ W7OLMG walnut WUH405 XPEDITE1K \
	78	+ yellowstone yosemite \
79	79	"
80	80
81	81	#########################################################################
...	...	@@ -919,6 +919,9 @@
919	919	PCI405_config: unconfig
920	920	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
921	921
	922	+pcs440ep_config: unconfig
	923	+ @./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
	924	+
922	925	PIP405_config: unconfig
923	926	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
924	927
	1	+#
	2	+# (C) Copyright 2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS = $(BOARD).o flash.o
	29	+SOBJS = init.o
	30	+
	31	+$(LIB): $(OBJS) $(SOBJS)
	32	+ $(AR) crv $@ $(OBJS)
	33	+
	34	+clean:
	35	+ rm -f $(SOBJS) $(OBJS)
	36	+
	37	+distclean: clean
	38	+ rm -f $(LIB) core *.bak .depend
	39	+
	40	+#########################################################################
	41	+
	42	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	43	+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	44	+
	45	+sinclude .depend
	46	+
	47	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2006
	3	+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/processor.h>
	26	+
	27	+#ifndef CFG_FLASH_READ0
	28	+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	29	+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	30	+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
	31	+#endif
	32	+
	33	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	34	+
	35	+/*
	36	+ * Functions
	37	+ */
	38	+static int write_word(flash_info_t *info, ulong dest, ulong data);
	39	+static ulong flash_get_size(vu_long addr, flash_info_t info);
	40	+
	41	+unsigned long flash_init(void)
	42	+{
	43	+ unsigned long size_b0, size_b1;
	44	+ int i;
	45	+ unsigned long base_b0, base_b1;
	46	+
	47	+ /* Init: no FLASHes known */
	48	+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
	49	+ flash_info[i].flash_id = FLASH_UNKNOWN;
	50	+ }
	51	+
	52	+ /* Static FLASH Bank configuration here - FIXME XXX */
	53	+
	54	+ base_b0 = FLASH_BASE0_PRELIM;
	55	+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
	56	+
	57	+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
	58	+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
	59	+ size_b0, size_b0 << 20);
	60	+ }
	61	+
	62	+ base_b1 = FLASH_BASE1_PRELIM;
	63	+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
	64	+
	65	+ return (size_b0 + size_b1);
	66	+}
	67	+
	68	+void flash_print_info(flash_info_t *info)
	69	+{
	70	+ int i;
	71	+ int k;
	72	+ int size;
	73	+ int erased;
	74	+ volatile unsigned long *flash;
	75	+
	76	+ if (info->flash_id == FLASH_UNKNOWN) {
	77	+ printf ("missing or unknown FLASH type\n");
	78	+ return;
	79	+ }
	80	+
	81	+ switch (info->flash_id & FLASH_VENDMASK) {
	82	+ case FLASH_MAN_AMD: printf ("AMD "); break;
	83	+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
	84	+ case FLASH_MAN_SST: printf ("SST "); break;
	85	+ case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
	86	+ default: printf ("Unknown Vendor "); break;
	87	+ }
	88	+
	89	+ switch (info->flash_id & FLASH_TYPEMASK) {
	90	+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
	91	+ break;
	92	+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
	93	+ break;
	94	+ case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
	95	+ break;
	96	+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
	97	+ break;
	98	+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
	99	+ break;
	100	+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
	101	+ break;
	102	+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
	103	+ break;
	104	+ case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
	105	+ break;
	106	+ case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
	107	+ break;
	108	+ case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
	109	+ break;
	110	+ case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
	111	+ break;
	112	+ case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
	113	+ break;
	114	+ case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
	115	+ break;
	116	+ case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
	117	+ break;
	118	+ case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
	119	+ break;
	120	+ default: printf ("Unknown Chip Type\n");
	121	+ break;
	122	+ }
	123	+
	124	+ printf (" Size: %ld MB in %d Sectors\n",
	125	+ info->size >> 20, info->sector_count);
	126	+
	127	+ printf (" Sector Start Addresses:");
	128	+ for (i=0; i<info->sector_count; ++i) {
	129	+#ifdef CFG_FLASH_EMPTY_INFO
	130	+ /*
	131	+ * Check if whole sector is erased
	132	+ */
	133	+ if (i != (info->sector_count-1))
	134	+ size = info->start[i+1] - info->start[i];
	135	+ else
	136	+ size = info->start[0] + info->size - info->start[i];
	137	+ erased = 1;
	138	+ flash = (volatile unsigned long *)info->start[i];
	139	+ size = size >> 2; /* divide by 4 for longword access */
	140	+ for (k=0; k<size; k++) {
	141	+ if (*flash++ != 0xffffffff) {
	142	+ erased = 0;
	143	+ break;
	144	+ }
	145	+ }
	146	+
	147	+ if ((i % 5) == 0)
	148	+ printf ("\n ");
	149	+ /* print empty and read-only info */
	150	+ printf (" %08lX%s%s",
	151	+ info->start[i],
	152	+ erased ? " E" : " ",
	153	+ info->protect[i] ? "RO " : " ");
	154	+#else
	155	+ if ((i % 5) == 0)
	156	+ printf ("\n ");
	157	+ printf (" %08lX%s",
	158	+ info->start[i],
	159	+ info->protect[i] ? " (RO)" : " ");
	160	+#endif
	161	+
	162	+ }
	163	+ printf ("\n");
	164	+ return;
	165	+}
	166	+
	167	+/*
	168	+ * The following code cannot be run from FLASH!
	169	+ */
	170	+static ulong flash_get_size(vu_long addr, flash_info_t info)
	171	+{
	172	+ short i;
	173	+ short n;
	174	+ volatile CFG_FLASH_WORD_SIZE value;
	175	+ ulong base = (ulong)addr;
	176	+ volatile CFG_FLASH_WORD_SIZE addr2 = (volatile CFG_FLASH_WORD_SIZE )addr;
	177	+
	178	+ /* Write auto select command: read Manufacturer ID */
	179	+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	180	+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	181	+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
	182	+
	183	+ value = addr2[CFG_FLASH_READ0];
	184	+
	185	+ switch (value) {
	186	+ case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
	187	+ info->flash_id = FLASH_MAN_AMD;
	188	+ break;
	189	+ case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
	190	+ info->flash_id = FLASH_MAN_FUJ;
	191	+ break;
	192	+ case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
	193	+ info->flash_id = FLASH_MAN_SST;
	194	+ break;
	195	+ case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
	196	+ info->flash_id = FLASH_MAN_EXCEL;
	197	+ break;
	198	+ default:
	199	+ info->flash_id = FLASH_UNKNOWN;
	200	+ info->sector_count = 0;
	201	+ info->size = 0;
	202	+ return (0); /* no or unknown flash */
	203	+ }
	204	+
	205	+ value = addr2[CFG_FLASH_READ1]; /* device ID */
	206	+
	207	+ switch (value) {
	208	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
	209	+ info->flash_id += FLASH_AM400T;
	210	+ info->sector_count = 11;
	211	+ info->size = 0x00080000;
	212	+ break; /* => 0.5 MB */
	213	+
	214	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
	215	+ info->flash_id += FLASH_AM400B;
	216	+ info->sector_count = 11;
	217	+ info->size = 0x00080000;
	218	+ break; /* => 0.5 MB */
	219	+
	220	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B:
	221	+ info->flash_id += FLASH_AM040;
	222	+ info->sector_count = 8;
	223	+ info->size = 0x0080000; /* => 512 ko */
	224	+ break;
	225	+
	226	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
	227	+ info->flash_id += FLASH_AM800T;
	228	+ info->sector_count = 19;
	229	+ info->size = 0x00100000;
	230	+ break; /* => 1 MB */
	231	+
	232	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
	233	+ info->flash_id += FLASH_AM800B;
	234	+ info->sector_count = 19;
	235	+ info->size = 0x00100000;
	236	+ break; /* => 1 MB */
	237	+
	238	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
	239	+ info->flash_id += FLASH_AM160T;
	240	+ info->sector_count = 35;
	241	+ info->size = 0x00200000;
	242	+ break; /* => 2 MB */
	243	+
	244	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
	245	+ info->flash_id += FLASH_AM160B;
	246	+ info->sector_count = 35;
	247	+ info->size = 0x00200000;
	248	+ break; /* => 2 MB */
	249	+
	250	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
	251	+ info->flash_id += FLASH_AM320T;
	252	+ info->sector_count = 71;
	253	+ info->size = 0x00400000; break; /* => 4 MB */
	254	+
	255	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
	256	+ info->flash_id += FLASH_AM320B;
	257	+ info->sector_count = 71;
	258	+ info->size = 0x00400000; break; /* => 4 MB */
	259	+
	260	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
	261	+ info->flash_id += FLASH_AMDL322T;
	262	+ info->sector_count = 71;
	263	+ info->size = 0x00400000; break; /* => 4 MB */
	264	+
	265	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
	266	+ info->flash_id += FLASH_AMDL322B;
	267	+ info->sector_count = 71;
	268	+ info->size = 0x00400000; break; /* => 4 MB */
	269	+
	270	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
	271	+ info->flash_id += FLASH_AMDL323T;
	272	+ info->sector_count = 71;
	273	+ info->size = 0x00400000; break; /* => 4 MB */
	274	+
	275	+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
	276	+ info->flash_id += FLASH_AMDL323B;
	277	+ info->sector_count = 71;
	278	+ info->size = 0x00400000; break; /* => 4 MB */
	279	+
	280	+ case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
	281	+ info->flash_id += FLASH_SST020;
	282	+ info->sector_count = 64;
	283	+ info->size = 0x00040000;
	284	+ break; /* => 256 kB */
	285	+
	286	+ case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
	287	+ info->flash_id += FLASH_SST040;
	288	+ info->sector_count = 128;
	289	+ info->size = 0x00080000;
	290	+ break; /* => 512 kB */
	291	+
	292	+ default:
	293	+ info->flash_id = FLASH_UNKNOWN;
	294	+ return (0); /* => no or unknown flash */
	295	+
	296	+ }
	297	+
	298	+ /* set up sector start address table */
	299	+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) \|\|
	300	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
	301	+ for (i = 0; i < info->sector_count; i++)
	302	+ info->start[i] = base + (i * 0x00001000);
	303	+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
	304	+ for (i = 0; i < info->sector_count; i++)
	305	+ info->start[i] = base + (i * 0x00010000);
	306	+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) \|\|
	307	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) \|\|
	308	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) \|\|
	309	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
	310	+ /* set sector offsets for bottom boot block type */
	311	+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
	312	+ info->start[i] = base;
	313	+ base += 8 << 10;
	314	+ }
	315	+ while (i < info->sector_count) { /* 64k regular sectors */
	316	+ info->start[i] = base;
	317	+ base += 64 << 10;
	318	+ ++i;
	319	+ }
	320	+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) \|\|
	321	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) \|\|
	322	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) \|\|
	323	+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
	324	+ /* set sector offsets for top boot block type */
	325	+ base += info->size;
	326	+ i = info->sector_count;
	327	+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
	328	+ base -= 8 << 10;
	329	+ --i;
	330	+ info->start[i] = base;
	331	+ }
	332	+ while (i > 0) { /* 64k regular sectors */
	333	+ base -= 64 << 10;
	334	+ --i;
	335	+ info->start[i] = base;
	336	+ }
	337	+ } else {
	338	+ if (info->flash_id & FLASH_BTYPE) {
	339	+ /* set sector offsets for bottom boot block type */
	340	+ info->start[0] = base + 0x00000000;
	341	+ info->start[1] = base + 0x00004000;
	342	+ info->start[2] = base + 0x00006000;
	343	+ info->start[3] = base + 0x00008000;
	344	+ for (i = 4; i < info->sector_count; i++) {
	345	+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
	346	+ }
	347	+ } else {
	348	+ /* set sector offsets for top boot block type */
	349	+ i = info->sector_count - 1;
	350	+ info->start[i--] = base + info->size - 0x00004000;
	351	+ info->start[i--] = base + info->size - 0x00006000;
	352	+ info->start[i--] = base + info->size - 0x00008000;
	353	+ for (; i >= 0; i--) {
	354	+ info->start[i] = base + i * 0x00010000;
	355	+ }
	356	+ }
	357	+ }
	358	+
	359	+ /* check for protected sectors */
	360	+ for (i = 0; i < info->sector_count; i++) {
	361	+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
	362	+ /* D0 = 1 if protected */
	363	+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
	364	+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
	365	+ info->protect[i] = 0;
	366	+ else
	367	+ info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
	368	+ }
	369	+
	370	+ /*
	371	+ * Prevent writes to uninitialized FLASH.
	372	+ */
	373	+ if (info->flash_id != FLASH_UNKNOWN) {
	374	+ addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
	375	+ addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; / reset bank */
	376	+ }
	377	+
	378	+ return (info->size);
	379	+}
	380	+
	381	+
	382	+int flash_erase(flash_info_t *info, int s_first, int s_last)
	383	+{
	384	+ volatile CFG_FLASH_WORD_SIZE addr = (CFG_FLASH_WORD_SIZE )(info->start[0]);
	385	+ volatile CFG_FLASH_WORD_SIZE *addr2;
	386	+ int flag, prot, sect, l_sect;
	387	+ ulong start, now, last;
	388	+
	389	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	390	+ if (info->flash_id == FLASH_UNKNOWN)
	391	+ printf ("- missing\n");
	392	+ else
	393	+ printf ("- no sectors to erase\n");
	394	+ return 1;
	395	+ }
	396	+
	397	+ if (info->flash_id == FLASH_UNKNOWN) {
	398	+ printf ("Can't erase unknown flash type - aborted\n");
	399	+ return 1;
	400	+ }
	401	+
	402	+ prot = 0;
	403	+ for (sect=s_first; sect<=s_last; ++sect)
	404	+ if (info->protect[sect])
	405	+ prot++;
	406	+
	407	+ if (prot)
	408	+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
	409	+ else
	410	+ printf ("\n");
	411	+
	412	+ l_sect = -1;
	413	+
	414	+ /* Disable interrupts which might cause a timeout here */
	415	+ flag = disable_interrupts();
	416	+
	417	+ /* Start erase on unprotected sectors */
	418	+ for (sect = s_first; sect<=s_last; sect++) {
	419	+ if (info->protect[sect] == 0) { /* not protected */
	420	+ addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
	421	+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
	422	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	423	+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	424	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
	425	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	426	+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	427	+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
	428	+
	429	+ /* re-enable interrupts if necessary */
	430	+ if (flag) {
	431	+ enable_interrupts();
	432	+ flag = 0;
	433	+ }
	434	+
	435	+ /* data polling for D7 */
	436	+ start = get_timer (0);
	437	+ while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
	438	+ (CFG_FLASH_WORD_SIZE)0x00800080) {
	439	+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
	440	+ return (1);
	441	+ }
	442	+ } else {
	443	+ if (sect == s_first) {
	444	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	445	+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	446	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
	447	+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	448	+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	449	+ }
	450	+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
	451	+ }
	452	+ l_sect = sect;
	453	+ }
	454	+ }
	455	+
	456	+ /* re-enable interrupts if necessary */
	457	+ if (flag)
	458	+ enable_interrupts();
	459	+
	460	+ /* wait at least 80us - let's wait 1 ms */
	461	+ udelay (1000);
	462	+
	463	+ /*
	464	+ * We wait for the last triggered sector
	465	+ */
	466	+ if (l_sect < 0)
	467	+ goto DONE;
	468	+
	469	+ start = get_timer (0);
	470	+ last = start;
	471	+ addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
	472	+ while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
	473	+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
	474	+ printf ("Timeout\n");
	475	+ return 1;
	476	+ }
	477	+ /* show that we're waiting */
	478	+ if ((now - last) > 1000) { /* every second */
	479	+ putc ('.');
	480	+ last = now;
	481	+ }
	482	+ }
	483	+
	484	+DONE:
	485	+ /* reset to read mode */
	486	+ addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
	487	+ addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
	488	+
	489	+ printf (" done\n");
	490	+ return 0;
	491	+}
	492	+
	493	+/*
	494	+ * Copy memory to flash, returns:
	495	+ * 0 - OK
	496	+ * 1 - write timeout
	497	+ * 2 - Flash not erased
	498	+ */
	499	+int write_buff(flash_info_t info, uchar src, ulong addr, ulong cnt)
	500	+{
	501	+ ulong cp, wp, data;
	502	+ int i, l, rc;
	503	+
	504	+ wp = (addr & ~3); /* get lower word aligned address */
	505	+
	506	+ /*
	507	+ * handle unaligned start bytes
	508	+ */
	509	+ if ((l = addr - wp) != 0) {
	510	+ data = 0;
	511	+ for (i=0, cp=wp; i<l; ++i, ++cp) {
	512	+ data = (data << 8) \| ((uchar )cp);
	513	+ }
	514	+ for (; i<4 && cnt>0; ++i) {
	515	+ data = (data << 8) \| *src++;
	516	+ --cnt;
	517	+ ++cp;
	518	+ }
	519	+ for (; cnt==0 && i<4; ++i, ++cp) {
	520	+ data = (data << 8) \| ((uchar )cp);
	521	+ }
	522	+
	523	+ if ((rc = write_word(info, wp, data)) != 0) {
	524	+ return (rc);
	525	+ }
	526	+ wp += 4;
	527	+ }
	528	+
	529	+ /*
	530	+ * handle word aligned part
	531	+ */
	532	+ while (cnt >= 4) {
	533	+ data = 0;
	534	+ for (i=0; i<4; ++i)
	535	+ data = (data << 8) \| *src++;
	536	+ if ((rc = write_word(info, wp, data)) != 0)
	537	+ return (rc);
	538	+ wp += 4;
	539	+ cnt -= 4;
	540	+ }
	541	+
	542	+ if (cnt == 0)
	543	+ return (0);
	544	+
	545	+ /*
	546	+ * handle unaligned tail bytes
	547	+ */
	548	+ data = 0;
	549	+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
	550	+ data = (data << 8) \| *src++;
	551	+ --cnt;
	552	+ }
	553	+ for (; i<4; ++i, ++cp)
	554	+ data = (data << 8) \| ((uchar )cp);
	555	+
	556	+ return (write_word(info, wp, data));
	557	+}
	558	+
	559	+/*
	560	+ * Write a word to Flash, returns:
	561	+ * 0 - OK
	562	+ * 1 - write timeout
	563	+ * 2 - Flash not erased
	564	+ */
	565	+static int write_word(flash_info_t *info, ulong dest, ulong data)
	566	+{
	567	+ volatile CFG_FLASH_WORD_SIZE addr2 = (CFG_FLASH_WORD_SIZE )(info->start[0]);
	568	+ volatile CFG_FLASH_WORD_SIZE dest2 = (CFG_FLASH_WORD_SIZE )dest;
	569	+ volatile CFG_FLASH_WORD_SIZE data2 = (CFG_FLASH_WORD_SIZE )&data;
	570	+ ulong start;
	571	+ int flag;
	572	+ int i;
	573	+
	574	+ /* Check if Flash is (sufficiently) erased */
	575	+ if ((((vu_long )dest) & data) != data)
	576	+ return (2);
	577	+
	578	+ /* Disable interrupts which might cause a timeout here */
	579	+ flag = disable_interrupts();
	580	+
	581	+ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
	582	+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
	583	+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
	584	+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
	585	+
	586	+ dest2[i] = data2[i];
	587	+
	588	+ /* re-enable interrupts if necessary */
	589	+ if (flag)
	590	+ enable_interrupts();
	591	+
	592	+ /* data polling for D7 */
	593	+ start = get_timer (0);
	594	+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
	595	+ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
	596	+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
	597	+ return (1);
	598	+ }
	599	+ }
	600	+
	601	+ return (0);
	602	+}
	1	+/*
	2	+ * (C) Copyright 2006
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(powerpc)
	25	+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
	26	+/* Do we need any of these for elf?
	27	+ __DYNAMIC = 0; */
	28	+SECTIONS
	29	+{
	30	+ .resetvec 0xFFFFFFFC :
	31	+ {
	32	+ *(.resetvec)
	33	+ } = 0xffff
	34	+
	35	+ .bootpg 0xFFFFF000 :
	36	+ {
	37	+ cpu/ppc4xx/start.o (.bootpg)
	38	+ } = 0xffff
	39	+
	40	+ /* Read-only sections, merged into text segment: */
	41	+ . = + SIZEOF_HEADERS;
	42	+ .interp : { *(.interp) }
	43	+ .hash : { *(.hash) }
	44	+ .dynsym : { *(.dynsym) }
	45	+ .dynstr : { *(.dynstr) }
	46	+ .rel.text : { *(.rel.text) }
	47	+ .rela.text : { *(.rela.text) }
	48	+ .rel.data : { *(.rel.data) }
	49	+ .rela.data : { *(.rela.data) }
	50	+ .rel.rodata : { *(.rel.rodata) }
	51	+ .rela.rodata : { *(.rela.rodata) }
	52	+ .rel.got : { *(.rel.got) }
	53	+ .rela.got : { *(.rela.got) }
	54	+ .rel.ctors : { *(.rel.ctors) }
	55	+ .rela.ctors : { *(.rela.ctors) }
	56	+ .rel.dtors : { *(.rel.dtors) }
	57	+ .rela.dtors : { *(.rela.dtors) }
	58	+ .rel.bss : { *(.rel.bss) }
	59	+ .rela.bss : { *(.rela.bss) }
	60	+ .rel.plt : { *(.rel.plt) }
	61	+ .rela.plt : { *(.rela.plt) }
	62	+ .init : { *(.init) }
	63	+ .plt : { *(.plt) }
	64	+ .text :
	65	+ {
	66	+ /* WARNING - the following is hand-optimized to fit within */
	67	+ /* the sector layout of our flash chips! XXX FIXME XXX */
	68	+
	69	+ cpu/ppc4xx/start.o (.text)
	70	+ board/pcs440ep/init.o (.text)
	71	+ cpu/ppc4xx/kgdb.o (.text)
	72	+ cpu/ppc4xx/traps.o (.text)
	73	+ cpu/ppc4xx/interrupts.o (.text)
	74	+ cpu/ppc4xx/serial.o (.text)
	75	+ cpu/ppc4xx/cpu_init.o (.text)
	76	+ cpu/ppc4xx/speed.o (.text)
	77	+ common/dlmalloc.o (.text)
	78	+ lib_generic/crc32.o (.text)
	79	+ lib_ppc/extable.o (.text)
	80	+ lib_generic/zlib.o (.text)
	81	+
	82	+/* . = env_offset;*/
	83	+/* common/environment.o(.text)*/
	84	+
	85	+ *(.text)
	86	+ *(.fixup)
	87	+ *(.got1)
	88	+ }
	89	+ _etext = .;
	90	+ PROVIDE (etext = .);
	91	+ .rodata :
	92	+ {
	93	+ *(.rodata)
	94	+ *(.rodata1)
	95	+ *(.rodata.str1.4)
	96	+ *(.eh_frame)
	97	+ }
	98	+ .fini : { *(.fini) } =0
	99	+ .ctors : { *(.ctors) }
	100	+ .dtors : { *(.dtors) }
	101	+
	102	+ /* Read-write section, merged into data segment: */
	103	+ . = (. + 0x00FF) & 0xFFFFFF00;
	104	+ _erotext = .;
	105	+ PROVIDE (erotext = .);
	106	+ .reloc :
	107	+ {
	108	+ *(.got)
	109	+ _GOT2_TABLE_ = .;
	110	+ *(.got2)
	111	+ _FIXUP_TABLE_ = .;
	112	+ *(.fixup)
	113	+ }
	114	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
	115	+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
	116	+
	117	+ .data :
	118	+ {
	119	+ *(.data)
	120	+ *(.data1)
	121	+ *(.sdata)
	122	+ *(.sdata2)
	123	+ *(.dynamic)
	124	+ CONSTRUCTORS
	125	+ }
	126	+ _edata = .;
	127	+ PROVIDE (edata = .);
	128	+
	129	+ . = .;
	130	+ __u_boot_cmd_start = .;
	131	+ .u_boot_cmd : { *(.u_boot_cmd) }
	132	+ __u_boot_cmd_end = .;
	133	+
	134	+
	135	+ . = .;
	136	+ __start___ex_table = .;
	137	+ __ex_table : { *(__ex_table) }
	138	+ __stop___ex_table = .;
	139	+
	140	+ . = ALIGN(256);
	141	+ __init_begin = .;
	142	+ .text.init : { *(.text.init) }
	143	+ .data.init : { *(.data.init) }
	144	+ . = ALIGN(256);
	145	+ __init_end = .;
	146	+
	147	+ __bss_start = .;
	148	+ .bss :
	149	+ {
	150	+ (.sbss) (.scommon)
	151	+ *(.dynbss)
	152	+ *(.bss)
	153	+ *(COMMON)
	154	+ }
	155	+ _end = . ;
	156	+ PROVIDE (end = .);
	157	+}
1	1	/*
2		- * (C) Copyright 2000
	2	+ * (C) Copyright 2000-2006
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
5	5	* See file CREDITS for list of people who contributed to this
6	6
...	...	@@ -101,7 +101,118 @@
101	101	# endif
102	102	#endif /* CFG_INIT_DCACHE_CS */
103	103
	104	+#if defined(CFG_440_GPIO_TABLE)
	105	+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
104	106
	107	+void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
	108	+{
	109	+ unsigned char i=0, j=0, reg_offset = 0, gpio_core;
	110	+ unsigned long gpio_reg, gpio_core_add;
	111	+
	112	+ for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
	113	+ j = 0;
	114	+ reg_offset = 0;
	115	+ /* GPIO config of the GPIOs 0 to 31 */
	116	+ for (i=0; i<GPIO_MAX; i++, j++) {
	117	+ if (i == GPIO_MAX/2) {
	118	+ reg_offset = 4;
	119	+ j = i-16;
	120	+ }
	121	+
	122	+ gpio_core_add = (*gpio_tab)[gpio_core][i].add;
	123	+
	124	+ if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) \|\|
	125	+ ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
	126	+
	127	+ switch ((*gpio_tab)[gpio_core][i].alt_nb) {
	128	+ case GPIO_SEL:
	129	+ break;
	130	+
	131	+ case GPIO_ALT1:
	132	+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
	133	+ & ~(GPIO_MASK >> (j*2));
	134	+ gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	135	+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
	136	+ break;
	137	+
	138	+ case GPIO_ALT2:
	139	+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
	140	+ & ~(GPIO_MASK >> (j*2));
	141	+ gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	142	+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
	143	+ break;
	144	+
	145	+ case GPIO_ALT3:
	146	+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
	147	+ & ~(GPIO_MASK >> (j*2));
	148	+ gpio_reg = gpio_reg \| (GPIO_IN_SEL >> (j*2));
	149	+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
	150	+ break;
	151	+ }
	152	+ }
	153	+
	154	+ if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) \|\|
	155	+ ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
	156	+
	157	+ switch ((*gpio_tab)[gpio_core][i].alt_nb) {
	158	+ case GPIO_SEL:
	159	+ if (gpio_core == GPIO0) {
	160	+ gpio_reg = in32(GPIO0_TCR) \| (0x80000000 >> (j));
	161	+ out32(GPIO0_TCR, gpio_reg);
	162	+ }
	163	+
	164	+ if (gpio_core == GPIO1) {
	165	+ gpio_reg = in32(GPIO1_TCR) \| (0x80000000 >> (j));
	166	+ out32(GPIO1_TCR, gpio_reg);
	167	+ }
	168	+
	169	+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
	170	+ & ~(GPIO_MASK >> (j*2));
	171	+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
	172	+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
	173	+ & ~(GPIO_MASK >> (j*2));
	174	+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
	175	+ break;
	176	+
	177	+ case GPIO_ALT1:
	178	+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
	179	+ & ~(GPIO_MASK >> (j*2));
	180	+ gpio_reg = gpio_reg \| (GPIO_ALT1_SEL >> (j*2));
	181	+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
	182	+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
	183	+ & ~(GPIO_MASK >> (j*2));
	184	+ gpio_reg = gpio_reg \| (GPIO_ALT1_SEL >> (j*2));
	185	+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
	186	+ break;
	187	+
	188	+ case GPIO_ALT2:
	189	+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
	190	+ & ~(GPIO_MASK >> (j*2));
	191	+ gpio_reg = gpio_reg \| (GPIO_ALT2_SEL >> (j*2));
	192	+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
	193	+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
	194	+ & ~(GPIO_MASK >> (j*2));
	195	+ gpio_reg = gpio_reg \| (GPIO_ALT2_SEL >> (j*2));
	196	+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
	197	+ break;
	198	+
	199	+ case GPIO_ALT3:
	200	+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
	201	+ & ~(GPIO_MASK >> (j*2));
	202	+ gpio_reg = gpio_reg \| (GPIO_ALT3_SEL >> (j*2));
	203	+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
	204	+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
	205	+ & ~(GPIO_MASK >> (j*2));
	206	+ gpio_reg = gpio_reg \| (GPIO_ALT3_SEL >> (j*2));
	207	+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
	208	+ break;
	209	+ }
	210	+ }
	211	+ }
	212	+ }
	213	+}
	214	+#endif /* CFG_440_GPIO_TABLE */
	215	+
105	216	/*
106	217	* Breath some life into the CPU...
107	218	*
108	219
...	...	@@ -129,10 +240,16 @@
129	240	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE \| CPC0_EPRCSR_E1NFE);
130	241	#endif /* CONFIG_405EP */
131	242
	243	+#if defined(CFG_440_GPIO_TABLE)
	244	+ set_chip_gpio_configuration(&gpio_tab);
	245	+#endif /* CFG_440_GPIO_TABLE */
	246	+
132	247	/*
133	248	* External Bus Controller (EBC) Setup
134	249	*/
135	250	#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
	251	+#if (defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
	252	+ defined(CONFIG_405EP) \|\| defined(CONFIG_405))
136	253	/*
137	254	* Move the next instructions into icache, since these modify the flash
138	255	* we are running from!
...	...	@@ -148,6 +265,7 @@
148	265	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
149	266	asm volatile(" mtctr 3" ::: "ctr");
150	267	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
	268	+#endif
151	269
152	270	mtebc(pb0ap, CFG_EBC_PB0AP);
153	271	mtebc(pb0cr, CFG_EBC_PB0CR);
...	...	@@ -1198,12 +1198,19 @@
1198	1198	.globl relocate_code
1199	1199	relocate_code:
1200	1200	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
1201		- dccci 0,0 /* Invalidate data cache, now no longer our stack */
	1201	+ /*
	1202	+ * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
	1203	+ * to speed up the boot process. Now this cache needs to be disabled.
	1204	+ */
	1205	+ iccci 0,0 /* Invalidate inst cache */
	1206	+ dccci 0,0 /* Invalidate data cache, now no longer our stack */
1202	1207	sync
	1208	+ isync
1203	1209	addi r1,r0,0x0000 /* TLB entry #0 */
1204	1210	tlbre r0,r1,0x0002 /* Read contents */
1205	1211	ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1206	1212	tlbwe r0,r1,0x0002 /* Save it out */
	1213	+ sync
1207	1214	isync
1208	1215	#endif
1209	1216	mr r1, r3 /* Set new stack pointer */
...	...	@@ -1357,55 +1357,105 @@
1357	1357	/******************************************************************************
1358	1358	* GPIO macro register defines
1359	1359	******************************************************************************/
	1360	+#define GPIO0 0
	1361	+#define GPIO1 1
	1362	+
1360	1363	#if defined(CONFIG_440GP)
1361		-#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
	1364	+#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
1362	1365
1363		-#define GPIO0_OR (GPIO_BASE0+0x0)
1364		-#define GPIO0_TCR (GPIO_BASE0+0x4)
1365		-#define GPIO0_ODR (GPIO_BASE0+0x18)
1366		-#define GPIO0_IR (GPIO_BASE0+0x1C)
	1366	+#define GPIO0_OR (GPIO0_BASE+0x0)
	1367	+#define GPIO0_TCR (GPIO0_BASE+0x4)
	1368	+#define GPIO0_ODR (GPIO0_BASE+0x18)
	1369	+#define GPIO0_IR (GPIO0_BASE+0x1C)
1367	1370	#endif /* CONFIG_440GP */
1368	1371
1369	1372	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
1370		-#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
1371		-#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
	1373	+#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
	1374	+#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
1372	1375
1373		-#define GPIO0_OR (GPIO_BASE0+0x0)
1374		-#define GPIO0_TCR (GPIO_BASE0+0x4)
1375		-#define GPIO0_OSRL (GPIO_BASE0+0x8)
1376		-#define GPIO0_OSRH (GPIO_BASE0+0xC)
1377		-#define GPIO0_TSRL (GPIO_BASE0+0x10)
1378		-#define GPIO0_TSRH (GPIO_BASE0+0x14)
1379		-#define GPIO0_ODR (GPIO_BASE0+0x18)
1380		-#define GPIO0_IR (GPIO_BASE0+0x1C)
1381		-#define GPIO0_RR1 (GPIO_BASE0+0x20)
1382		-#define GPIO0_RR2 (GPIO_BASE0+0x24)
1383		-#define GPIO0_RR3 (GPIO_BASE0+0x28)
1384		-#define GPIO0_ISR1L (GPIO_BASE0+0x30)
1385		-#define GPIO0_ISR1H (GPIO_BASE0+0x34)
1386		-#define GPIO0_ISR2L (GPIO_BASE0+0x38)
1387		-#define GPIO0_ISR2H (GPIO_BASE0+0x3C)
1388		-#define GPIO0_ISR3L (GPIO_BASE0+0x40)
1389		-#define GPIO0_ISR3H (GPIO_BASE0+0x44)
	1376	+/* Offsets */
	1377	+#define GPIOx_OR 0x00 /* GPIO Output Register */
	1378	+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
	1379	+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
	1380	+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
	1381	+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
	1382	+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
	1383	+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
	1384	+#define GPIOx_IR 0x1C /* GPIO Input Register */
	1385	+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
	1386	+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
	1387	+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
	1388	+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
	1389	+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
	1390	+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
	1391	+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
	1392	+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
	1393	+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
1390	1394
1391		-#define GPIO1_OR (GPIO_BASE1+0x0)
1392		-#define GPIO1_TCR (GPIO_BASE1+0x4)
1393		-#define GPIO1_OSRL (GPIO_BASE1+0x8)
1394		-#define GPIO1_OSRH (GPIO_BASE1+0xC)
1395		-#define GPIO1_TSRL (GPIO_BASE1+0x10)
1396		-#define GPIO1_TSRH (GPIO_BASE1+0x14)
1397		-#define GPIO1_ODR (GPIO_BASE1+0x18)
1398		-#define GPIO1_IR (GPIO_BASE1+0x1C)
1399		-#define GPIO1_RR1 (GPIO_BASE1+0x20)
1400		-#define GPIO1_RR2 (GPIO_BASE1+0x24)
1401		-#define GPIO1_RR3 (GPIO_BASE1+0x28)
1402		-#define GPIO1_ISR1L (GPIO_BASE1+0x30)
1403		-#define GPIO1_ISR1H (GPIO_BASE1+0x34)
1404		-#define GPIO1_ISR2L (GPIO_BASE1+0x38)
1405		-#define GPIO1_ISR2H (GPIO_BASE1+0x3C)
1406		-#define GPIO1_ISR3L (GPIO_BASE1+0x40)
1407		-#define GPIO1_ISR3H (GPIO_BASE1+0x44)
	1395	+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
	1396	+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
	1397	+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
	1398	+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
	1399	+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
	1400	+
	1401	+#define GPIO0_OR (GPIO0_BASE+0x0)
	1402	+#define GPIO0_TCR (GPIO0_BASE+0x4)
	1403	+#define GPIO0_OSRL (GPIO0_BASE+0x8)
	1404	+#define GPIO0_OSRH (GPIO0_BASE+0xC)
	1405	+#define GPIO0_TSRL (GPIO0_BASE+0x10)
	1406	+#define GPIO0_TSRH (GPIO0_BASE+0x14)
	1407	+#define GPIO0_ODR (GPIO0_BASE+0x18)
	1408	+#define GPIO0_IR (GPIO0_BASE+0x1C)
	1409	+#define GPIO0_RR1 (GPIO0_BASE+0x20)
	1410	+#define GPIO0_RR2 (GPIO0_BASE+0x24)
	1411	+#define GPIO0_RR3 (GPIO0_BASE+0x28)
	1412	+#define GPIO0_ISR1L (GPIO0_BASE+0x30)
	1413	+#define GPIO0_ISR1H (GPIO0_BASE+0x34)
	1414	+#define GPIO0_ISR2L (GPIO0_BASE+0x38)
	1415	+#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
	1416	+#define GPIO0_ISR3L (GPIO0_BASE+0x40)
	1417	+#define GPIO0_ISR3H (GPIO0_BASE+0x44)
	1418	+
	1419	+#define GPIO1_OR (GPIO1_BASE+0x0)
	1420	+#define GPIO1_TCR (GPIO1_BASE+0x4)
	1421	+#define GPIO1_OSRL (GPIO1_BASE+0x8)
	1422	+#define GPIO1_OSRH (GPIO1_BASE+0xC)
	1423	+#define GPIO1_TSRL (GPIO1_BASE+0x10)
	1424	+#define GPIO1_TSRH (GPIO1_BASE+0x14)
	1425	+#define GPIO1_ODR (GPIO1_BASE+0x18)
	1426	+#define GPIO1_IR (GPIO1_BASE+0x1C)
	1427	+#define GPIO1_RR1 (GPIO1_BASE+0x20)
	1428	+#define GPIO1_RR2 (GPIO1_BASE+0x24)
	1429	+#define GPIO1_RR3 (GPIO1_BASE+0x28)
	1430	+#define GPIO1_ISR1L (GPIO1_BASE+0x30)
	1431	+#define GPIO1_ISR1H (GPIO1_BASE+0x34)
	1432	+#define GPIO1_ISR2L (GPIO1_BASE+0x38)
	1433	+#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
	1434	+#define GPIO1_ISR3L (GPIO1_BASE+0x40)
	1435	+#define GPIO1_ISR3H (GPIO1_BASE+0x44)
1408	1436	#endif
	1437	+
	1438	+#define GPIO_GROUP_MAX 2
	1439	+#define GPIO_MAX 32
	1440	+#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
	1441	+#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
	1442	+#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
	1443	+#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
	1444	+#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
	1445	+ /* For the other GPIO number, you must shift */
	1446	+
	1447	+#ifndef __ASSEMBLY__
	1448	+
	1449	+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
	1450	+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
	1451	+
	1452	+typedef struct { unsigned long add; /* gpio core base address */
	1453	+ gpio_driver_t in_out; /* Driver Setting */
	1454	+ gpio_select_t alt_nb; /* Selected Alternate */
	1455	+} gpio_param_s;
	1456	+
	1457	+
	1458	+#endif /* __ASSEMBLY__ */
1409	1459
1410	1460	/*
1411	1461	* Macros for accessing the indirect EBC registers