Eric Lee / smarc-uboot

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Commit a56bd92289298bde16306bcc754277db45315d2f

Authored by wdenk
1 parent 5ca2679933
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Dave Peverley, 30 Apr 2004: 

Add support for OMAP730 Perseus2 Development board

* Patch by Alan J. Luse, 29 Apr 2004:
  Fix flash chip-select (OR0) option register setting on FADS boards.

* Patch by Alan J. Luse, 29 Apr 2004:
  Report MII network speed and duplex setting properly when
  auto-negotiate is not enabled.

* Patch by Jarrett Redd, 29 Apr 2004:
  Fix hang on reset on Ocotea board due to flash in wrong mode.

Showing 23 changed files with 2115 additions and 16 deletions Side-by-side Diff

... ... @@ -2,6 +2,19 @@
2 2 Changes since U-Boot 1.1.1:
3 3 ======================================================================
4 4  
  5 +* Patch by Dave Peverley, 30 Apr 2004:
  6 + Add support for OMAP730 Perseus2 Development board
  7 +
  8 +* Patch by Alan J. Luse, 29 Apr 2004:
  9 + Fix flash chip-select (OR0) option register setting on FADS boards.
  10 +
  11 +* Patch by Alan J. Luse, 29 Apr 2004:
  12 + Report MII network speed and duplex setting properly when
  13 + auto-negotiate is not enabled.
  14 +
  15 +* Patch by Jarrett Redd, 29 Apr 2004:
  16 + Fix hang on reset on Ocotea board due to flash in wrong mode.
  17 +
5 18 * Patch by Dave Peverley, 29 Apr 2004:
6 19 add MAC address detection to smc91111 driver
7 20  
... ... @@ -285,6 +285,11 @@
285 285 D: Support for PIP405 board
286 286 D: Support for MIP405 board
287 287  
  288 +N: Dave Peverley
  289 +E: dpeverley@mpc-data.co.uk
  290 +W: http://www.mpc-data.co.uk
  291 +D: OMAP730 P2 board support
  292 +
288 293 N: Bill Pitts
289 294 E: wlp@mindspring.com
290 295 D: BedBug embedded debugger code
... ... @@ -340,6 +340,9 @@
340 340 omap1510inn ARM925T
341 341 omap1610inn ARM926EJS
342 342  
  343 +Dave Peverley <dpeverley@mpc-data.co.uk>
  344 + omap730p2 ARM926EJS
  345 +
343 346 Nishant Kamat <nskamat@ti.com>
344 347  
345 348 omap1610h2 ARM926EJS
... ... @@ -139,8 +139,8 @@
139 139 LIST_ARM9=" \
140 140 at91rm9200dk integratorcp integratorap \
141 141 omap1510inn omap1610h2 omap1610inn \
142   - smdk2400 smdk2410 trab \
143   - VCMA9 versatile \
  142 + omap730p2 smdk2400 smdk2410 \
  143 + trab VCMA9 versatile \
144 144 "
145 145  
146 146 #########################################################################
... ... @@ -981,6 +981,8 @@
981 981  
982 982 xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
983 983  
  984 +xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
  985 +
984 986 SX1_config : unconfig
985 987 @./mkconfig $(@:_config=) arm arm925t sx1
986 988  
... ... @@ -1010,6 +1012,18 @@
1010 1012 echo "... configured for CS3 boot"; \
1011 1013 fi;
1012 1014 @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
  1015 +
  1016 +omap730p2_config \
  1017 +omap730p2_cs0boot_config \
  1018 +omap730p2_cs3boot_config : unconfig
  1019 + @if [ "$(findstring _cs0boot_, $@)" ] ; then \
  1020 + echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
  1021 + echo "... configured for CS0 boot"; \
  1022 + else \
  1023 + echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
  1024 + echo "... configured for CS3 boot"; \
  1025 + fi;
  1026 + @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
1013 1027  
1014 1028 smdk2400_config : unconfig
1015 1029 @./mkconfig $(@:_config=) arm arm920t smdk2400
... ... @@ -294,8 +294,9 @@
294 294 CONFIG_AT91RM9200DK, CONFIG_DNP1110, CONFIG_EP7312,
295 295 CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7,
296 296 CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_LART,
297   - CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_SMDK2400,
298   - CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9,
  297 + CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_P2_OMAP730,
  298 + CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
  299 + CONFIG_VCMA9
299 300  
300 301 MicroBlaze based boards:
301 302 ------------------------
... ... @@ -2074,6 +2075,7 @@
2074 2075 FADS823_config NETVIA_config TQM860L_config
2075 2076 FADS850SAR_config omap1510inn_config WALNUT405_config
2076 2077 FADS860T_config omap1610h2_config ZPC1900_config
  2078 + omap730p2_config
2077 2079  
2078 2080 Note: for some board special configuration names may exist; check if
2079 2081 additional information is available from the board vendor; for
... ... @@ -94,7 +94,7 @@
94 94  
95 95 /* Remap FLASH according to real size */
96 96 memctl->memc_or0 =
97   - ((((unsigned long) ~1) << i) & OR_AM_MSK) |
  97 + ((((unsigned long) ~0) << i) & OR_AM_MSK) |
98 98 CFG_OR_TIMING_FLASH;
99 99 memctl->memc_br0 = CFG_BR0_PRELIM;
100 100  
board/ocotea/flash.c
Diff comments   View file @ a56bd92
... ... @@ -349,10 +349,14 @@
349 349 info->protect[i] = addr2[2] & 1;
350 350 }
351 351  
  352 + /* issue bank reset to return to read mode */
  353 + addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
  354 +
352 355 /*
353 356 * Prevent writes to uninitialized FLASH.
354 357 */
355 358 if (info->flash_id != FLASH_UNKNOWN) {
  359 + /* ? ? ? */
356 360 }
357 361  
358 362 return (info->size);
board/omap730p2/Makefile
Diff comments   View file @ a56bd92
  1 +#
  2 +# (C) Copyright 2000, 2001, 2002
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := omap730p2.o flash.o
  29 +SOBJS := platform.o
  30 +
  31 +$(LIB): $(OBJS) $(SOBJS)
  32 + $(AR) crv $@ $^
  33 +
  34 +clean:
  35 + rm -f $(SOBJS) $(OBJS)
  36 +
  37 +distclean: clean
  38 + rm -f $(LIB) core *.bak .depend
  39 +
  40 +#########################################################################
  41 +
  42 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  43 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  44 +
  45 +-include .depend
  46 +
  47 +#########################################################################
board/omap730p2/config.mk
Diff comments   View file @ a56bd92
  1 +#
  2 +# (C) Copyright 2002
  3 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  5 +#
  6 +# (C) Copyright 2003
  7 +# Texas Instruments, <www.ti.com>
  8 +# Kshitij Gupta <Kshitij@ti.com>
  9 +#
  10 +# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
  11 +# see http://www.ti.com/ for more information on Texas Instruments
  12 +#
  13 +# Innovator has 1 bank of 256 MB SDRAM
  14 +# Physical Address:
  15 +# 1000'0000 to 2000'0000
  16 +#
  17 +#
  18 +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
  19 +# (mem base + reserved)
  20 +#
  21 +# we load ourself to 1108'0000
  22 +#
  23 +#
  24 +
  25 +TEXT_BASE = 0x11080000
board/omap730p2/flash.c
Diff comments   View file @ a56bd92
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  4 + *
  5 + * (C) Copyright 2001
  6 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 + *
  8 + * (C) Copyright 2003
  9 + * Texas Instruments, <www.ti.com>
  10 + * Kshitij Gupta <Kshitij@ti.com>
  11 + *
  12 + * See file CREDITS for list of people who contributed to this
  13 + * project.
  14 + *
  15 + * This program is free software; you can redistribute it and/or
  16 + * modify it under the terms of the GNU General Public License as
  17 + * published by the Free Software Foundation; either version 2 of
  18 + * the License, or (at your option) any later version.
  19 + *
  20 + * This program is distributed in the hope that it will be useful,
  21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23 + * GNU General Public License for more details.
  24 + *
  25 + * You should have received a copy of the GNU General Public License
  26 + * along with this program; if not, write to the Free Software
  27 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 + * MA 02111-1307 USA
  29 + */
  30 +
  31 +#include <common.h>
  32 +#include <linux/byteorder/swab.h>
  33 +
  34 +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
  35 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  36 +
  37 +/* Board support for 1 or 2 flash devices */
  38 +#undef FLASH_PORT_WIDTH32
  39 +#define FLASH_PORT_WIDTH16
  40 +
  41 +#ifdef FLASH_PORT_WIDTH16
  42 +#define FLASH_PORT_WIDTH ushort
  43 +#define FLASH_PORT_WIDTHV vu_short
  44 +#define SWAP(x) __swab16(x)
  45 +#else
  46 +#define FLASH_PORT_WIDTH ulong
  47 +#define FLASH_PORT_WIDTHV vu_long
  48 +#define SWAP(x) __swab32(x)
  49 +#endif
  50 +
  51 +#define FPW FLASH_PORT_WIDTH
  52 +#define FPWV FLASH_PORT_WIDTHV
  53 +
  54 +#define mb() __asm__ __volatile__ ("" : : : "memory")
  55 +
  56 +
  57 +/* Flash Organization Structure */
  58 +typedef struct OrgDef {
  59 + unsigned int sector_number;
  60 + unsigned int sector_size;
  61 +} OrgDef;
  62 +
  63 +
  64 +/* Flash Organizations */
  65 +OrgDef OrgIntel_28F256L18T[] = {
  66 + {4, 32 * 1024}, /* 4 * 32kBytes sectors */
  67 + {255, 128 * 1024}, /* 255 * 128kBytes sectors */
  68 +};
  69 +
  70 +
  71 +/*-----------------------------------------------------------------------
  72 + * Functions
  73 + */
  74 +unsigned long flash_init (void);
  75 +static ulong flash_get_size (FPW * addr, flash_info_t * info);
  76 +static int write_data (flash_info_t * info, ulong dest, FPW data);
  77 +static void flash_get_offsets (ulong base, flash_info_t * info);
  78 +void inline spin_wheel (void);
  79 +void flash_print_info (flash_info_t * info);
  80 +void flash_unprotect_sectors (FPWV * addr);
  81 +int flash_erase (flash_info_t * info, int s_first, int s_last);
  82 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
  83 +
  84 +/*-----------------------------------------------------------------------
  85 + */
  86 +
  87 +unsigned long flash_init (void)
  88 +{
  89 + int i;
  90 + ulong size = 0;
  91 + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
  92 + switch (i) {
  93 + case 0:
  94 + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
  95 + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
  96 + break;
  97 + default:
  98 + panic ("configured too many flash banks!\n");
  99 + break;
  100 + }
  101 + size += flash_info[i].size;
  102 + }
  103 +
  104 + /* Protect monitor and environment sectors
  105 + */
  106 + flash_protect (FLAG_PROTECT_SET,
  107 + CFG_FLASH_BASE,
  108 + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
  109 +
  110 + flash_protect (FLAG_PROTECT_SET,
  111 + CFG_ENV_ADDR,
  112 + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
  113 +
  114 + return size;
  115 +}
  116 +
  117 +/*-----------------------------------------------------------------------
  118 + */
  119 +static void flash_get_offsets (ulong base, flash_info_t * info)
  120 +{
  121 + int i;
  122 + OrgDef *pOrgDef;
  123 +
  124 + pOrgDef = OrgIntel_28F256L18T;
  125 + if (info->flash_id == FLASH_UNKNOWN) {
  126 + return;
  127 + }
  128 +
  129 + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
  130 + for (i = 0; i < info->sector_count; i++) {
  131 + if (i > 255) {
  132 + info->start[i] = base + (i * 0x8000);
  133 + info->protect[i] = 0;
  134 + } else {
  135 + info->start[i] = base +
  136 + (i * PHYS_FLASH_SECT_SIZE);
  137 + info->protect[i] = 0;
  138 + }
  139 + }
  140 + }
  141 +}
  142 +
  143 +/*-----------------------------------------------------------------------
  144 + */
  145 +void flash_print_info (flash_info_t * info)
  146 +{
  147 + int i;
  148 +
  149 + if (info->flash_id == FLASH_UNKNOWN) {
  150 + printf ("missing or unknown FLASH type\n");
  151 + return;
  152 + }
  153 +
  154 + switch (info->flash_id & FLASH_VENDMASK) {
  155 + case FLASH_MAN_INTEL:
  156 + printf ("INTEL ");
  157 + break;
  158 + default:
  159 + printf ("Unknown Vendor ");
  160 + break;
  161 + }
  162 +
  163 + switch (info->flash_id & FLASH_TYPEMASK) {
  164 + case FLASH_28F256L18T:
  165 + printf ("FLASH 28F256L18T\n");
  166 + break;
  167 + default:
  168 + printf ("Unknown Chip Type\n");
  169 + break;
  170 + }
  171 +
  172 + printf (" Size: %ld MB in %d Sectors\n",
  173 + info->size >> 20, info->sector_count);
  174 +
  175 + printf (" Sector Start Addresses:");
  176 + for (i = 0; i < info->sector_count; ++i) {
  177 + if ((i % 5) == 0)
  178 + printf ("\n ");
  179 + printf (" %08lX%s",
  180 + info->start[i], info->protect[i] ? " (RO)" : " ");
  181 + }
  182 + printf ("\n");
  183 + return;
  184 +}
  185 +
  186 +/*
  187 + * The following code cannot be run from FLASH!
  188 + */
  189 +static ulong flash_get_size (FPW * addr, flash_info_t * info)
  190 +{
  191 + volatile FPW value;
  192 +
  193 + /* Write auto select command: read Manufacturer ID */
  194 + addr[0x5555] = (FPW) 0x00AA00AA;
  195 + addr[0x2AAA] = (FPW) 0x00550055;
  196 + addr[0x5555] = (FPW) 0x00900090;
  197 +
  198 + mb ();
  199 + value = addr[0];
  200 +
  201 + switch (value) {
  202 +
  203 + case (FPW) INTEL_MANUFACT:
  204 + info->flash_id = FLASH_MAN_INTEL;
  205 + break;
  206 +
  207 + default:
  208 + info->flash_id = FLASH_UNKNOWN;
  209 + info->sector_count = 0;
  210 + info->size = 0;
  211 + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  212 + return (0); /* no or unknown flash */
  213 + }
  214 +
  215 + mb ();
  216 + value = addr[1]; /* device ID */
  217 + switch (value) {
  218 +
  219 + case (FPW) (INTEL_ID_28F256L18T):
  220 + info->flash_id += FLASH_28F256L18T;
  221 + info->sector_count = 259;
  222 + info->size = 0x02000000;
  223 + break; /* => 32 MB */
  224 +
  225 + default:
  226 + info->flash_id = FLASH_UNKNOWN;
  227 + break;
  228 + }
  229 +
  230 + if (info->sector_count > CFG_MAX_FLASH_SECT) {
  231 + printf ("** ERROR: sector count %d > max (%d) **\n",
  232 + info->sector_count, CFG_MAX_FLASH_SECT);
  233 + info->sector_count = CFG_MAX_FLASH_SECT;
  234 + }
  235 +
  236 + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  237 +
  238 + return (info->size);
  239 +}
  240 +
  241 +
  242 +/* unprotects a sector for write and erase
  243 + * on some intel parts, this unprotects the entire chip, but it
  244 + * wont hurt to call this additional times per sector...
  245 + */
  246 +void flash_unprotect_sectors (FPWV * addr)
  247 +{
  248 +#define PD_FINTEL_WSMS_READY_MASK 0x0080
  249 +
  250 + *addr = (FPW) 0x00500050; /* clear status register */
  251 +
  252 + /* this sends the clear lock bit command */
  253 + *addr = (FPW) 0x00600060;
  254 + *addr = (FPW) 0x00D000D0;
  255 +}
  256 +
  257 +
  258 +/*-----------------------------------------------------------------------
  259 + */
  260 +
  261 +int flash_erase (flash_info_t * info, int s_first, int s_last)
  262 +{
  263 + int flag, prot, sect;
  264 + ulong type, start, last;
  265 + int rcode = 0;
  266 +
  267 + if ((s_first < 0) || (s_first > s_last)) {
  268 + if (info->flash_id == FLASH_UNKNOWN) {
  269 + printf ("- missing\n");
  270 + } else {
  271 + printf ("- no sectors to erase\n");
  272 + }
  273 + return 1;
  274 + }
  275 +
  276 + type = (info->flash_id & FLASH_VENDMASK);
  277 + if ((type != FLASH_MAN_INTEL)) {
  278 + printf ("Can't erase unknown flash type %08lx - aborted\n",
  279 + info->flash_id);
  280 + return 1;
  281 + }
  282 +
  283 + prot = 0;
  284 + for (sect = s_first; sect <= s_last; ++sect) {
  285 + if (info->protect[sect]) {
  286 + prot++;
  287 + }
  288 + }
  289 +
  290 + if (prot) {
  291 + printf ("- Warning: %d protected sectors will not be erased!\n",
  292 + prot);
  293 + } else {
  294 + printf ("\n");
  295 + }
  296 +
  297 +
  298 + start = get_timer (0);
  299 + last = start;
  300 +
  301 + /* Disable interrupts which might cause a timeout here */
  302 + flag = disable_interrupts ();
  303 +
  304 + /* Start erase on unprotected sectors */
  305 + for (sect = s_first; sect <= s_last; sect++) {
  306 + if (info->protect[sect] == 0) { /* not protected */
  307 + FPWV *addr = (FPWV *) (info->start[sect]);
  308 + FPW status;
  309 +
  310 + printf ("Erasing sector %2d ... ", sect);
  311 +
  312 + flash_unprotect_sectors (addr);
  313 +
  314 + /* arm simple, non interrupt dependent timer */
  315 + reset_timer_masked ();
  316 +
  317 + *addr = (FPW) 0x00500050;/* clear status register */
  318 + *addr = (FPW) 0x00200020;/* erase setup */
  319 + *addr = (FPW) 0x00D000D0;/* erase confirm */
  320 +
  321 + while (((status =
  322 + *addr) & (FPW) 0x00800080) !=
  323 + (FPW) 0x00800080) {
  324 + if (get_timer_masked () >
  325 + CFG_FLASH_ERASE_TOUT) {
  326 + printf ("Timeout\n");
  327 + /* suspend erase */
  328 + *addr = (FPW) 0x00B000B0;
  329 + /* reset to read mode */
  330 + *addr = (FPW) 0x00FF00FF;
  331 + rcode = 1;
  332 + break;
  333 + }
  334 + }
  335 +
  336 + /* clear status register cmd. */
  337 + *addr = (FPW) 0x00500050;
  338 + *addr = (FPW) 0x00FF00FF;/* resest to read mode */
  339 + printf (" done\n");
  340 + }
  341 + }
  342 + return rcode;
  343 +}
  344 +
  345 +/*-----------------------------------------------------------------------
  346 + * Copy memory to flash, returns:
  347 + * 0 - OK
  348 + * 1 - write timeout
  349 + * 2 - Flash not erased
  350 + * 4 - Flash not identified
  351 + */
  352 +
  353 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  354 +{
  355 + ulong cp, wp;
  356 + FPW data;
  357 + int count, i, l, rc, port_width;
  358 +
  359 + if (info->flash_id == FLASH_UNKNOWN) {
  360 + return 4;
  361 + }
  362 +/* get lower word aligned address */
  363 +#ifdef FLASH_PORT_WIDTH16
  364 + wp = (addr & ~1);
  365 + port_width = 2;
  366 +#else
  367 + wp = (addr & ~3);
  368 + port_width = 4;
  369 +#endif
  370 +
  371 + /*
  372 + * handle unaligned start bytes
  373 + */
  374 + if ((l = addr - wp) != 0) {
  375 + data = 0;
  376 + for (i = 0, cp = wp; i < l; ++i, ++cp) {
  377 + data = (data << 8) | (*(uchar *) cp);
  378 + }
  379 + for (; i < port_width && cnt > 0; ++i) {
  380 + data = (data << 8) | *src++;
  381 + --cnt;
  382 + ++cp;
  383 + }
  384 + for (; cnt == 0 && i < port_width; ++i, ++cp) {
  385 + data = (data << 8) | (*(uchar *) cp);
  386 + }
  387 +
  388 + if ((rc = write_data (info, wp, SWAP (data))) != 0) {
  389 + return (rc);
  390 + }
  391 + wp += port_width;
  392 + }
  393 +
  394 + /*
  395 + * handle word aligned part
  396 + */
  397 + count = 0;
  398 + while (cnt >= port_width) {
  399 + data = 0;
  400 + for (i = 0; i < port_width; ++i) {
  401 + data = (data << 8) | *src++;
  402 + }
  403 + if ((rc = write_data (info, wp, SWAP (data))) != 0) {
  404 + return (rc);
  405 + }
  406 + wp += port_width;
  407 + cnt -= port_width;
  408 + if (count++ > 0x800) {
  409 + spin_wheel ();
  410 + count = 0;
  411 + }
  412 + }
  413 +
  414 + if (cnt == 0) {
  415 + return (0);
  416 + }
  417 +
  418 + /*
  419 + * handle unaligned tail bytes
  420 + */
  421 + data = 0;
  422 + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
  423 + data = (data << 8) | *src++;
  424 + --cnt;
  425 + }
  426 + for (; i < port_width; ++i, ++cp) {
  427 + data = (data << 8) | (*(uchar *) cp);
  428 + }
  429 +
  430 + return (write_data (info, wp, SWAP (data)));
  431 +}
  432 +
  433 +/*-----------------------------------------------------------------------
  434 + * Write a word or halfword to Flash, returns:
  435 + * 0 - OK
  436 + * 1 - write timeout
  437 + * 2 - Flash not erased
  438 + */
  439 +static int write_data (flash_info_t * info, ulong dest, FPW data)
  440 +{
  441 + FPWV *addr = (FPWV *) dest;
  442 + ulong status;
  443 + int flag;
  444 +
  445 + /* Check if Flash is (sufficiently) erased */
  446 + if ((*addr & data) != data) {
  447 + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
  448 + return (2);
  449 + }
  450 + flash_unprotect_sectors (addr);
  451 + /* Disable interrupts which might cause a timeout here */
  452 + flag = disable_interrupts ();
  453 + *addr = (FPW) 0x00400040; /* write setup */
  454 + *addr = data;
  455 +
  456 + /* arm simple, non interrupt dependent timer */
  457 + reset_timer_masked ();
  458 +
  459 + /* wait while polling the status register */
  460 + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
  461 + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
  462 + *addr = (FPW) 0x00FF00FF; /* restore read mode */
  463 + return (1);
  464 + }
  465 + }
  466 + *addr = (FPW) 0x00FF00FF; /* restore read mode */
  467 + return (0);
  468 +}
  469 +
  470 +void inline spin_wheel (void)
  471 +{
  472 + static int p = 0;
  473 + static char w[] = "\\/-";
  474 +
  475 + printf ("\010%c", w[p]);
  476 + (++p == 3) ? (p = 0) : 0;
  477 +}
board/omap730p2/omap730p2.c
Diff comments   View file @ a56bd92
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4 + * Marius Groeger <mgroeger@sysgo.de>
  5 + *
  6 + * (C) Copyright 2002
  7 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  8 + *
  9 + * (C) Copyright 2003
  10 + * Texas Instruments, <www.ti.com>
  11 + * Kshitij Gupta <Kshitij@ti.com>
  12 + *
  13 + * See file CREDITS for list of people who contributed to this
  14 + * project.
  15 + *
  16 + * This program is free software; you can redistribute it and/or
  17 + * modify it under the terms of the GNU General Public License as
  18 + * published by the Free Software Foundation; either version 2 of
  19 + * the License, or (at your option) any later version.
  20 + *
  21 + * This program is distributed in the hope that it will be useful,
  22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24 + * GNU General Public License for more details.
  25 + *
  26 + * You should have received a copy of the GNU General Public License
  27 + * along with this program; if not, write to the Free Software
  28 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 + * MA 02111-1307 USA
  30 + */
  31 +
  32 +#include <common.h>
  33 +#if defined(CONFIG_OMAP730)
  34 +#include <./configs/omap730.h>
  35 +#endif
  36 +
  37 +int test_boot_mode(void);
  38 +void spin_up_leds(void);
  39 +void flash__init (void);
  40 +void ether__init (void);
  41 +void set_muxconf_regs (void);
  42 +void peripheral_power_enable (void);
  43 +
  44 +#define FLASH_ON_CS0 1
  45 +#define FLASH_ON_CS3 0
  46 +
  47 +static inline void delay (unsigned long loops)
  48 +{
  49 + __asm__ volatile ("1:\n"
  50 + "subs %0, %1, #1\n"
  51 + "bne 1b":"=r" (loops):"0" (loops));
  52 +}
  53 +
  54 +int test_boot_mode(void)
  55 +{
  56 + /* Check for CS0 and CS3 address decode swapping */
  57 + if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
  58 + return(FLASH_ON_CS3);
  59 + else
  60 + return(FLASH_ON_CS0);
  61 +}
  62 +
  63 +/* Toggle backup LED indication */
  64 +void toggle_backup_led(void)
  65 +{
  66 + static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
  67 + volatile unsigned int *IOConfReg;
  68 +
  69 +
  70 + IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
  71 +
  72 + if (backupLEDState != 0) {
  73 + *IOConfReg &= (0xFFFFEFFF);
  74 + backupLEDState = 0;
  75 + } else {
  76 + *IOConfReg |= (0x00001000);
  77 + backupLEDState = 1;
  78 + }
  79 +}
  80 +
  81 +/*
  82 + * Miscellaneous platform dependent initialisations
  83 + */
  84 +
  85 +int board_init (void)
  86 +{
  87 + volatile unsigned int *IOConfReg;
  88 +
  89 +
  90 + DECLARE_GLOBAL_DATA_PTR;
  91 +
  92 + /* arch number of OMAP 730 P2 Board - Same as the Innovator! */
  93 + gd->bd->bi_arch_number = 491;
  94 +
  95 + /* adress of boot parameters */
  96 + gd->bd->bi_boot_params = 0x10000100;
  97 +
  98 + /* Configure MUX settings */
  99 + set_muxconf_regs ();
  100 +
  101 + peripheral_power_enable ();
  102 +
  103 +
  104 + /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
  105 + toggle_backup_led();
  106 +
  107 + /* Hold GSM in reset until needed */
  108 + *((volatile unsigned short *)M_CTL) &= ~1;
  109 +
  110 +
  111 + /*
  112 + * CSx timings, GPIO Mux ... setup
  113 + */
  114 +
  115 + /* Flash: CS0 timings setup */
  116 + *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
  117 + *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
  118 +
  119 + /* Ethernet support trough the debug board */
  120 + /* CS1 timings setup */
  121 + *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
  122 + *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
  123 +
  124 + /* this speeds up your boot a quite a bit. However to make it
  125 + * work, you need make sure your kernel startup flush bug is fixed.
  126 + * ... rkw ...
  127 + */
  128 + icache_enable ();
  129 +
  130 + flash__init ();
  131 + ether__init ();
  132 +
  133 + return 0;
  134 +}
  135 +
  136 +int misc_init_r (void)
  137 +{
  138 + /* currently empty */
  139 + return (0);
  140 +}
  141 +
  142 +/******************************
  143 + Routine:
  144 + Description:
  145 +******************************/
  146 +void flash__init (void)
  147 +{
  148 + unsigned int regval;
  149 +
  150 + regval = *((volatile unsigned int *) EMIFS_CONFIG);
  151 + /* Turn off write protection for flash devices. */
  152 + regval = regval | 0x0001;
  153 + *((volatile unsigned int *) EMIFS_CONFIG) = regval;
  154 +}
  155 +
  156 +/*************************************************************
  157 + Routine:ether__init
  158 + Description: take the Ethernet controller out of reset and wait
  159 + for the EEPROM load to complete.
  160 +*************************************************************/
  161 +void ether__init (void)
  162 +{
  163 +#define LAN_RESET_REGISTER 0x0400001c
  164 +
  165 + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
  166 + do {
  167 + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
  168 + udelay (100);
  169 + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
  170 +
  171 + do {
  172 + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
  173 + udelay (100);
  174 + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
  175 +
  176 +#define ETH_CONTROL_REG 0x0400030b
  177 +
  178 + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
  179 + udelay (100);
  180 +}
  181 +
  182 +/******************************
  183 + Routine:
  184 + Description:
  185 +******************************/
  186 +int dram_init (void)
  187 +{
  188 + DECLARE_GLOBAL_DATA_PTR;
  189 +
  190 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  191 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  192 +
  193 + return 0;
  194 +}
  195 +
  196 +/******************************************************
  197 + Routine: set_muxconf_regs
  198 + Description: Setting up the configuration Mux registers
  199 + specific to the hardware
  200 +*******************************************************/
  201 +void set_muxconf_regs (void)
  202 +{
  203 + volatile unsigned int *MuxConfReg;
  204 + /* set each registers to its reset value; */
  205 +
  206 + /*
  207 + * Backup LED Indication
  208 + */
  209 +
  210 + /* Configure MUXed pin. Mode 6: GPIO_140 */
  211 + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
  212 + *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
  213 + *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
  214 +
  215 + /* Configure GPIO_140 as output */
  216 + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
  217 + *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
  218 +
  219 + /*
  220 + * Configure GPIOs for battery charge & feedback
  221 + */
  222 +
  223 + /* Configure MUXed pin. Mode 6: GPIO_35 */
  224 + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
  225 + *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
  226 + *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
  227 +
  228 + /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
  229 + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
  230 + *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
  231 + *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
  232 +
  233 + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
  234 + *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
  235 + *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
  236 +
  237 + /*
  238 + * Allow battery charge
  239 + */
  240 +
  241 + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
  242 + *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
  243 +
  244 + /*
  245 + * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
  246 + * It is used as the Ethernet controller interrupt
  247 + */
  248 + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
  249 + *MuxConfReg &= 0x1FFFFFFF;
  250 +}
  251 +
  252 +/******************************************************
  253 + Routine: peripheral_power_enable
  254 + Description: Enable the power for UART1
  255 +*******************************************************/
  256 +void peripheral_power_enable (void)
  257 +{
  258 + volatile unsigned int *MuxConfReg;
  259 +
  260 +
  261 + /* Set up pins used by UART */
  262 +
  263 + /* Start UART clock (48MHz) */
  264 + MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
  265 + *MuxConfReg &= (0xFFFFFFF7);
  266 + *MuxConfReg |= (0x00000008);
  267 +
  268 + /* Get the UART pin in mode0 */
  269 + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
  270 + *MuxConfReg &= (0xFF1FFFFF);
  271 + *MuxConfReg &= (0xF1FFFFFF);
  272 +}
board/omap730p2/platform.S
Diff comments   View file @ a56bd92
  1 +/*
  2 + * Board specific setup info
  3 + *
  4 + * (C) Copyright 2003-2004
  5 + *
  6 + * Texas Instruments, <www.ti.com>
  7 + * Kshitij Gupta <Kshitij@ti.com>
  8 + *
  9 + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
  10 + *
  11 + * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
  12 + * (http://www.mpc-data.co.uk)
  13 + *
  14 + * TODO : Tidy up and change to use system register defines
  15 + * from omap730.h where possible.
  16 + *
  17 + * See file CREDITS for list of people who contributed to this
  18 + * project.
  19 + *
  20 + * This program is free software; you can redistribute it and/or
  21 + * modify it under the terms of the GNU General Public License as
  22 + * published by the Free Software Foundation; either version 2 of
  23 + * the License, or (at your option) any later version.
  24 + *
  25 + * This program is distributed in the hope that it will be useful,
  26 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28 + * GNU General Public License for more details.
  29 + *
  30 + * You should have received a copy of the GNU General Public License
  31 + * along with this program; if not, write to the Free Software
  32 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33 + * MA 02111-1307 USA
  34 + */
  35 +
  36 +#include <config.h>
  37 +#include <version.h>
  38 +
  39 +#if defined(CONFIG_OMAP730)
  40 +#include <./configs/omap730.h>
  41 +#endif
  42 +
  43 +_TEXT_BASE:
  44 + .word TEXT_BASE /* sdram load addr from config.mk */
  45 +
  46 +.globl platformsetup
  47 +platformsetup:
  48 + /* Save callers address in r11 - r11 must never be modified */
  49 + mov r11, lr
  50 +
  51 + /*------------------------------------------------------*
  52 + *mask all IRQs by setting all bits in the INTMR default*
  53 + *------------------------------------------------------*/
  54 + mov r1, #0xffffffff
  55 + ldr r0, =REG_IHL1_MIR
  56 + str r1, [r0]
  57 + ldr r0, =REG_IHL2_MIR
  58 + str r1, [r0]
  59 +
  60 + /*------------------------------------------------------*
  61 + * Set up ARM CLM registers (IDLECT1) *
  62 + *------------------------------------------------------*/
  63 + ldr r0, REG_ARM_IDLECT1
  64 + ldr r1, VAL_ARM_IDLECT1
  65 + str r1, [r0]
  66 +
  67 + /*------------------------------------------------------*
  68 + * Set up ARM CLM registers (IDLECT2) *
  69 + *------------------------------------------------------*/
  70 + ldr r0, REG_ARM_IDLECT2
  71 + ldr r1, VAL_ARM_IDLECT2
  72 + str r1, [r0]
  73 +
  74 + /*------------------------------------------------------*
  75 + * Set up ARM CLM registers (IDLECT3) *
  76 + *------------------------------------------------------*/
  77 + ldr r0, REG_ARM_IDLECT3
  78 + ldr r1, VAL_ARM_IDLECT3
  79 + str r1, [r0]
  80 +
  81 +
  82 + mov r1, #0x01 /* PER_EN bit */
  83 + ldr r0, REG_ARM_RSTCT2
  84 + strh r1, [r0] /* CLKM; Peripheral reset. */
  85 +
  86 + /* Set CLKM to Sync-Scalable */
  87 + /* I supposedly need to enable the dsp clock before switching */
  88 + mov r1, #0x1000
  89 + ldr r0, REG_ARM_SYSST
  90 + strh r1, [r0]
  91 + mov r0, #0x400
  92 +1:
  93 + subs r0, r0, #0x1 /* wait for any bubbles to finish */
  94 + bne 1b
  95 + ldr r1, VAL_ARM_CKCTL
  96 + ldr r0, REG_ARM_CKCTL
  97 + strh r1, [r0]
  98 +
  99 + /* a few nops to let settle */
  100 + nop
  101 + nop
  102 + nop
  103 + nop
  104 + nop
  105 + nop
  106 + nop
  107 + nop
  108 + nop
  109 + nop
  110 +
  111 + /* setup DPLL 1 */
  112 + /* Ramp up the clock to 96Mhz */
  113 + ldr r1, VAL_DPLL1_CTL
  114 + ldr r0, REG_DPLL1_CTL
  115 + strh r1, [r0]
  116 + ands r1, r1, #0x10 /* Check if PLL is enabled. */
  117 + beq lock_end /* Do not look for lock if BYPASS selected */
  118 +2:
  119 + ldrh r1, [r0]
  120 + ands r1, r1, #0x01 /* Check the LOCK bit.*/
  121 + beq 2b /* loop until bit goes hi. */
  122 +lock_end:
  123 +
  124 + /*------------------------------------------------------*
  125 + * Turn off the watchdog during init... *
  126 + *------------------------------------------------------*/
  127 + ldr r0, REG_WATCHDOG
  128 + ldr r1, WATCHDOG_VAL1
  129 + str r1, [r0]
  130 + ldr r1, WATCHDOG_VAL2
  131 + str r1, [r0]
  132 + ldr r0, REG_WSPRDOG
  133 + ldr r1, WSPRDOG_VAL1
  134 + str r1, [r0]
  135 + ldr r0, REG_WWPSDOG
  136 +
  137 +watch1Wait:
  138 + ldr r1, [r0]
  139 + tst r1, #0x10
  140 + bne watch1Wait
  141 +
  142 + ldr r0, REG_WSPRDOG
  143 + ldr r1, WSPRDOG_VAL2
  144 + str r1, [r0]
  145 + ldr r0, REG_WWPSDOG
  146 +watch2Wait:
  147 + ldr r1, [r0]
  148 + tst r1, #0x10
  149 + bne watch2Wait
  150 +
  151 + /* Set memory timings corresponding to the new clock speed */
  152 +
  153 + /* Check execution location to determine current execution location
  154 + * and branch to appropriate initialization code.
  155 + */
  156 + /* Compare physical SDRAM base & current execution location. */
  157 + and r0, pc, #0xF0000000
  158 + /* Compare. */
  159 + cmp r0, #0
  160 + /* Skip over EMIF-fast initialization if running from SDRAM. */
  161 + bne skip_sdram
  162 +
  163 + /*
  164 + * Delay for SDRAM initialization.
  165 + */
  166 + mov r3, #0x1800 /* value should be checked */
  167 +3:
  168 + subs r3, r3, #0x1 /* Decrement count */
  169 + bne 3b
  170 +
  171 + ldr r0, REG_SDRAM_CONFIG
  172 + ldr r1, SDRAM_CONFIG_VAL
  173 + str r1, [r0]
  174 +
  175 + ldr r0, REG_SDRAM_MRS_LEGACY
  176 + ldr r1, SDRAM_MRS_VAL
  177 + str r1, [r0]
  178 +
  179 +skip_sdram:
  180 +
  181 +common_tc:
  182 + /* slow interface */
  183 + ldr r1, VAL_TC_EMIFS_CS0_CONFIG
  184 + ldr r0, REG_TC_EMIFS_CS0_CONFIG
  185 + str r1, [r0] /* Chip Select 0 */
  186 +
  187 + ldr r1, VAL_TC_EMIFS_CS1_CONFIG
  188 + ldr r0, REG_TC_EMIFS_CS1_CONFIG
  189 + str r1, [r0] /* Chip Select 1 */
  190 + ldr r1, VAL_TC_EMIFS_CS2_CONFIG
  191 + ldr r0, REG_TC_EMIFS_CS2_CONFIG
  192 + str r1, [r0] /* Chip Select 2 */
  193 + ldr r1, VAL_TC_EMIFS_CS3_CONFIG
  194 + ldr r0, REG_TC_EMIFS_CS3_CONFIG
  195 + str r1, [r0] /* Chip Select 3 */
  196 +
  197 + /* 48MHz clock request for UART1 */
  198 + ldr r1, PERSEUS2_CONFIG_BASE
  199 + ldrh r0, [r1, #CONFIG_PCC_CONF]
  200 + orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
  201 + strh r0, [r1, #CONFIG_PCC_CONF]
  202 +
  203 + /* Initialize public and private rheas
  204 + * - set access factor 2 on both rhea / strobe
  205 + * - disable write buffer on strb0, enable write buffer on strb1
  206 + */
  207 +
  208 + ldr R0, REG_RHEA_PUB_CTL
  209 + ldr R1, REG_RHEA_PRIV_CTL
  210 + ldr R2, VAL_RHEA_CTL
  211 + strh R2, [R0]
  212 + strh R2, [R1]
  213 + mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
  214 + strh R3, [R0, #0x08] /* arm rhea control reg */
  215 + strh R3, [R1, #0x08]
  216 +
  217 + /* enable IRQ and FIQ */
  218 +
  219 + mrs r4, CPSR
  220 + bic r4, r4, #IRQ_MASK
  221 + bic r4, r4, #FIQ_MASK
  222 + msr CPSR, r4
  223 +
  224 + /* set TAP CONF to TRI EMULATION */
  225 +
  226 + ldr r1, [r0, #CONFIG_MODE2]
  227 + bic r1, r1, #0x18
  228 + orr r1, r1, #0x10
  229 + str r1, [r0, #CONFIG_MODE2]
  230 +
  231 + /* set tdbgen to 1 */
  232 +
  233 + ldr r0, PERSEUS2_CONFIG_BASE
  234 + ldr r1, [r0, #CONFIG_MODE1]
  235 + mov r2, #0x10000
  236 + orr r1, r1, r2
  237 + str r1, [r0, #CONFIG_MODE1]
  238 +
  239 +#ifdef CONFIG_P2_OMAP1610
  240 + /* inserting additional 2 clock cycle hold time for LAN */
  241 + ldr r0, REG_TC_EMIFS_CS1_ADVANCED
  242 + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
  243 + str r1, [r0]
  244 +#endif
  245 + /* Start MPU Timer 1 */
  246 + ldr r0, REG_MPU_LOAD_TIMER
  247 + ldr r1, VAL_MPU_LOAD_TIMER
  248 + str r1, [r0]
  249 +
  250 + ldr r0, REG_MPU_CNTL_TIMER
  251 + ldr r1, VAL_MPU_CNTL_TIMER
  252 + str r1, [r0]
  253 +
  254 + /* back to arch calling code */
  255 + mov pc, r11
  256 +
  257 + /* the literal pools origin */
  258 + .ltorg
  259 +
  260 +REG_TC_EMIFS_CONFIG: /* 32 bits */
  261 + .word 0xfffecc0c
  262 +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
  263 + .word 0xfffecc10
  264 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
  265 + .word 0xfffecc14
  266 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
  267 + .word 0xfffecc18
  268 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
  269 + .word 0xfffecc1c
  270 +
  271 +#ifdef CONFIG_P2_OMAP730
  272 +REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
  273 + .word 0xfffecc54
  274 +#endif
  275 +
  276 +/* MPU clock/reset/power mode control registers */
  277 +REG_ARM_CKCTL: /* 16 bits */
  278 + .word 0xfffece00
  279 +
  280 +REG_ARM_IDLECT3: /* 16 bits */
  281 + .word 0xfffece24
  282 +REG_ARM_IDLECT2: /* 16 bits */
  283 + .word 0xfffece08
  284 +REG_ARM_IDLECT1: /* 16 bits */
  285 + .word 0xfffece04
  286 +
  287 +REG_ARM_RSTCT2: /* 16 bits */
  288 + .word 0xfffece14
  289 +REG_ARM_SYSST: /* 16 bits */
  290 + .word 0xfffece18
  291 +/* DPLL control registers */
  292 +REG_DPLL1_CTL: /* 16 bits */
  293 + .word 0xfffecf00
  294 +
  295 +/* Watch Dog register */
  296 +/* secure watchdog stop */
  297 +REG_WSPRDOG:
  298 + .word 0xfffeb048
  299 +/* watchdog write pending */
  300 +REG_WWPSDOG:
  301 + .word 0xfffeb034
  302 +
  303 +WSPRDOG_VAL1:
  304 + .word 0x0000aaaa
  305 +WSPRDOG_VAL2:
  306 + .word 0x00005555
  307 +
  308 +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
  309 + counter @8192 rows, 10 ns, 8 burst */
  310 +REG_SDRAM_CONFIG:
  311 + .word 0xfffecc20
  312 +
  313 +REG_SDRAM_MRS_LEGACY:
  314 + .word 0xfffecc24
  315 +
  316 +REG_WATCHDOG:
  317 + .word 0xfffec808
  318 +
  319 +REG_MPU_LOAD_TIMER:
  320 + .word 0xfffec600
  321 +REG_MPU_CNTL_TIMER:
  322 + .word 0xfffec500
  323 +
  324 +/* Public and private rhea bridge registers definition */
  325 +
  326 +REG_RHEA_PUB_CTL:
  327 + .word 0xFFFECA00
  328 +
  329 +REG_RHEA_PRIV_CTL:
  330 + .word 0xFFFED300
  331 +
  332 +/* EMIFF SDRAM Configuration register
  333 + - self refresh disable
  334 + - auto refresh enabled
  335 + - SDRAM type 64 Mb, 16 bits bus 4 banks
  336 + - power down enabled
  337 + - SDRAM clock disabled
  338 + */
  339 +SDRAM_CONFIG_VAL:
  340 + .word 0x0C017DF4
  341 +
  342 +/* Burst full page length ; cas latency = 3 */
  343 +SDRAM_MRS_VAL:
  344 + .word 0x00000037
  345 +
  346 +VAL_ARM_CKCTL:
  347 + .word 0x6505
  348 +VAL_DPLL1_CTL:
  349 + .word 0x3412
  350 +
  351 +#ifdef CONFIG_P2_OMAP730
  352 +VAL_TC_EMIFS_CS0_CONFIG:
  353 + .word 0x0000FFF3
  354 +VAL_TC_EMIFS_CS1_CONFIG:
  355 + .word 0x00004278
  356 +VAL_TC_EMIFS_CS2_CONFIG:
  357 + .word 0x00004278
  358 +VAL_TC_EMIFS_CS3_CONFIG:
  359 + .word 0x00004278
  360 +VAL_TC_EMIFS_CS1_ADVANCED:
  361 + .word 0x00000022
  362 +#endif
  363 +
  364 +VAL_ARM_IDLECT1:
  365 + .word 0x00000400
  366 +VAL_ARM_IDLECT2:
  367 + .word 0x00000886
  368 +VAL_ARM_IDLECT3:
  369 + .word 0x00000015
  370 +
  371 +WATCHDOG_VAL1:
  372 + .word 0x000000f5
  373 +WATCHDOG_VAL2:
  374 + .word 0x000000a0
  375 +
  376 +VAL_MPU_LOAD_TIMER:
  377 + .word 0xffffffff
  378 +VAL_MPU_CNTL_TIMER:
  379 + .word 0xffffffa1
  380 +
  381 +VAL_RHEA_CTL:
  382 + .word 0xFF22
  383 +
  384 +/* Config Register vals */
  385 +PERSEUS2_CONFIG_BASE:
  386 + .word 0xFFFE1000
  387 +
  388 +.equ CONFIG_PCC_CONF, 0xB4
  389 +.equ CONFIG_MODE1, 0x10
  390 +.equ CONFIG_MODE2, 0x14
  391 +.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
  392 +
  393 +/* misc values */
  394 +.equ IRQ_MASK, 0x80 // IRQ mask value
  395 +.equ FIQ_MASK, 0x40 // FIQ mask value
board/omap730p2/u-boot.lds
Diff comments   View file @ a56bd92
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  25 +OUTPUT_ARCH(arm)
  26 +ENTRY(_start)
  27 +SECTIONS
  28 +{
  29 + . = 0x00000000;
  30 + . = ALIGN(4);
  31 + .text :
  32 + {
  33 + cpu/arm926ejs/start.o (.text)
  34 + *(.text)
  35 + }
  36 + . = ALIGN(4);
  37 + .rodata : { *(.rodata) }
  38 + . = ALIGN(4);
  39 + .data : { *(.data) }
  40 + . = ALIGN(4);
  41 + .got : { *(.got) }
  42 +
  43 + __u_boot_cmd_start = .;
  44 + .u_boot_cmd : { *(.u_boot_cmd) }
  45 + __u_boot_cmd_end = .;
  46 +
  47 + . = ALIGN(4);
  48 + __bss_start = .;
  49 + .bss : { *(.bss) }
  50 + _end = .;
  51 +}
... ... @@ -147,15 +147,31 @@
147 147 }
148 148 #endif /* CONFIG_PHY_GIGE */
149 149  
150   - if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
151   - puts ("PHY speed1 read failed, assuming 10bT\n");
  150 + /* Check Basic Management Control Register first. */
  151 + if (miiphy_read (addr, PHY_BMCR, &reg)) {
  152 + puts ("PHY speed read failed, assuming 10bT\n");
152 153 return (_10BASET);
153 154 }
154   - if ((reg & PHY_ANLPAR_100) != 0) {
  155 + /* Check if auto-negotiation is on. */
  156 + if ((reg & PHY_BMCR_AUTON) != 0) {
  157 + /* Get auto-negotiation results. */
  158 + if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  159 + puts ("PHY AN speed read failed, assuming 10bT\n");
  160 + return (_10BASET);
  161 + }
  162 + if ((reg & PHY_ANLPAR_100) != 0) {
  163 + return (_100BASET);
  164 + } else {
  165 + return (_10BASET);
  166 + }
  167 + }
  168 + /* Get speed from basic control settings. */
  169 + else if (reg & PHY_BMCR_100MB) {
155 170 return (_100BASET);
156 171 } else {
157 172 return (_10BASET);
158 173 }
  174 +
159 175 }
160 176  
161 177  
162 178  
163 179  
164 180  
... ... @@ -182,16 +198,32 @@
182 198 }
183 199 #endif /* CONFIG_PHY_GIGE */
184 200  
185   - if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  201 + /* Check Basic Management Control Register first. */
  202 + if (miiphy_read (addr, PHY_BMCR, &reg)) {
186 203 puts ("PHY duplex read failed, assuming half duplex\n");
187 204 return (HALF);
188 205 }
  206 + /* Check if auto-negotiation is on. */
  207 + if ((reg & PHY_BMCR_AUTON) != 0) {
  208 + /* Get auto-negotiation results. */
  209 + if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
  210 + puts ("PHY AN duplex read failed, assuming half duplex\n");
  211 + return (HALF);
  212 + }
189 213  
190   - if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
  214 + if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
  215 + return (FULL);
  216 + } else {
  217 + return (HALF);
  218 + }
  219 + }
  220 + /* Get speed from basic control settings. */
  221 + else if (reg & PHY_BMCR_DPLX) {
191 222 return (FULL);
192 223 } else {
193 224 return (HALF);
194 225 }
  226 +
195 227 }
196 228  
197 229 #ifdef CFG_FAULT_ECHO_LINK_DOWN
cpu/arm926ejs/start.S
Diff comments   View file @ a56bd92
... ... @@ -3,7 +3,7 @@
3 3 *
4 4 * Copyright (c) 2003 Texas Instruments
5 5 *
6   - * ----- Adapted for OMAP1610 from ARM925t code ------
  6 + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 7 *
8 8 * Copyright (c) 2001 Marius Grรถger <mag@sysgo.de>
9 9 * Copyright (c) 2002 Alex Zรผpke <azu@sysgo.de>
... ... @@ -36,6 +36,8 @@
36 36  
37 37 #if defined(CONFIG_OMAP1610)
38 38 #include <./configs/omap1510.h>
  39 +#elif defined(CONFIG_OMAP730)
  40 +#include <./configs/omap730.h>
39 41 #endif
40 42  
41 43 /*
doc/README.omap730p2
Diff comments   View file @ a56bd92
  1 +
  2 + u-boot for the TI OMAP730 Perseus2
  3 +
  4 + Dave Peverley, MPC-Data Limited
  5 + http://www.mpc-data.co.uk
  6 +
  7 +
  8 +Overview :
  9 +
  10 + As the OMAP730 is similar to the OMAP1610 in many ways, this port was based
  11 +on the u-boot port to the OMAP1610 Innovator. Supported features are :
  12 +
  13 + - Serial terminal support
  14 + - Onboard NOR Flash
  15 + - Ethernet via the seperate debug board
  16 + - Tested on Rev4 and Rev5 boards
  17 +
  18 + It has also been tested to work correctly when built with a 'standard' GCC
  19 +3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain.
  20 +
  21 +
  22 +
  23 +Hardware Configuration :
  24 +
  25 + The main dips on the P2 board should be set to 2,3,7 and 9 on with all
  26 +others off. On the debug board, dips 1 and 7 should be on with the rest off.
  27 +The serial console has been set up to run from the DB9 connector on the
  28 +P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit.
  29 +
  30 + It should be noted that the P2 board has NOR flash that is addressable via
  31 +either CS0 or CS3. This mode can be changed via DIP9 on the P2 board.
  32 +
  33 +
  34 +
  35 +Installing u-boot for the P2 :
  36 +
  37 + You can simply build u-boot for the Perseus by following the instructions
  38 +in the main readme file. The target configuration is "omap730p2_config".
  39 +Once u-boot has been built, you should strip the executable so it can be
  40 +loaded via CCS (which cant cope with the symbols in the ELF binary) :
  41 + $ cp u-boot u-boot.out
  42 + $ arm-linux-strip u-boot.out
  43 +
  44 + The method we've used for installing u-boot the first time on a P2 is
  45 +as follows :
  46 +
  47 +1) Configure TI Code Composer Studio to connect to the P2 board via JTAG
  48 + as described in the Users Guide.
  49 +
  50 +2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU
  51 + and run the "init_mmu" GEL script.
  52 +
  53 +3) Use the "Load Program" option to send the u-boot.out file to the P2 and
  54 + run.
  55 +
  56 + At this point, u-boot should run and you will see the boot menu on your
  57 +serial terminal. You can then load the u-boot image to memory :
  58 +
  59 + # loadb 0x10000000
  60 +
  61 + Send the "u-boot.bin" binary via the serial using Kermit. Once loaded
  62 +you can self-flash u-boot :
  63 +
  64 + # protect off 1:0
  65 + # erase 1:0
  66 + # cp.b 0x10000000 0x0 0x20000
  67 +
  68 + You should now be able to reset the board and run u-boot from flash.
  69 +
  70 +
  71 +
  72 +Alternative flash option :
  73 +
  74 + Sometimes, if you've been silly, you can get the board into a state where
  75 +whats in flash has upset the board so much that you can no longer connect
  76 +to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode
  77 +of the P2 so that you boot from RAM instead of NOR flash. This moves NOR
  78 +flash up to 0x0C000000. You can build a special version of u-boot to
  79 +utilise this by the following config :
  80 +
  81 + $ make omap730p2_cs0boot_config
  82 +
  83 + If you load this up via CCS it will detect flash at its alternate location
  84 +and allow you to programme your u-boot image (which, remember must be built
  85 +for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work
  86 +fine again.
  87 +
  88 +
  89 +
  90 +Errata :
  91 +
  92 +1) It's been observed that sometimes the tftp transfer of kernels to the
  93 + board can have checksum errors or stall. This appears to be an issue
  94 + with the lan91c96.c driver, and can normally be worked around by
  95 + resetting the board and trying again.
... ... @@ -620,7 +620,7 @@
620 620 address |= smc_mac_addr[i];
621 621 SMC_outw (address, LAN91C96_IA0 + i);
622 622 }
623   -#else
  623 +#else
624 624 for (i = 0; i < 6; i++)
625 625 SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i);
626 626 #endif
... ... @@ -937,7 +937,7 @@
937 937 return (0);
938 938 }
939 939  
940   -/*
  940 +/*
941 941 * get_rom_mac()
942 942 * Note, this has omly been tested for the OMAP730 P2.
943 943 */
... ... @@ -959,8 +959,6 @@
959 959 return (1);
960 960 #endif
961 961 }
962   -
963   -
964 962  
965 963 #endif /* CONFIG_DRIVER_LAN91C96 */
... ... @@ -26,7 +26,7 @@
26 26 com_port->lcr = LCRVAL;
27 27 com_port->mcr = MCRVAL;
28 28 com_port->fcr = FCRVAL;
29   -#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
  29 +#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610) || defined(CONFIG_OMAP730)
30 30 com_port->mdr1 = 0; /* select uart mode */
31 31 #endif
32 32 }
include/configs/h2_p2_dbg_board.h
Diff comments   View file @ a56bd92
  1 +/*
  2 + *
  3 + * BRIEF MODULE DESCRIPTION
  4 + * TI H2 and P2 Debug Board hardware map
  5 + *
  6 + * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
  7 + * Author: MPC-Data Limited
  8 + * Dave Peverley
  9 + *
  10 + * This program is free software; you can redistribute it and/or modify it
  11 + * under the terms of the GNU General Public License as published by the
  12 + * Free Software Foundation; either version 2 of the License, or (at your
  13 + * option) any later version.
  14 + *
  15 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  21 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25 + *
  26 + * You should have received a copy of the GNU General Public License along
  27 + * with this program; if not, write to the Free Software Foundation, Inc.,
  28 + * 675 Mass Ave, Cambridge, MA 02139, USA.
  29 + */
  30 +
  31 +#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
  32 +#define __INCLUDED_H2_P2_DBH_BOARD_H
  33 +
  34 +
  35 +#include <asm/arch/sizes.h>
  36 +
  37 +
  38 +/*
  39 + * The Debug board is designed to function with the P2 Sample, H2
  40 + * Sample and 1610 Innovator boards. The main difference AFAICT is
  41 + * the chip selects used with each system ;
  42 + *
  43 + * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
  44 + * H2 Sample : CS1a is used to select the CPLD registers.
  45 + *
  46 + */
  47 +
  48 +
  49 +
  50 +/***************************************************************************
  51 + * CPLD Registers
  52 + **************************************************************************/
  53 +
  54 +#define H2DBG_CPLD_REVISION 0x04000010
  55 +#define H2DBG_BOARD_REVISION 0x04000012
  56 +#define H2DBG_GPIO_REGISTER 0x04000014
  57 +#define H2DBG_LED_CONTROL 0x04000016
  58 +#define H2DBG_MISC_INPUT 0x04000018
  59 +#define H2DBG_LAN_STATUS 0x0400001A
  60 +#define H2DBG_LAN_RESET 0x0400001C
  61 +#define H2DBG_ETH_REG_BASE 0x04000300
  62 +
  63 +
  64 +
  65 +/***************************************************************************
  66 + * Ethernet Control Registers
  67 + * These are for the LAN91C96 on the debug board
  68 + **************************************************************************/
  69 +
  70 +/* Bank 0 in IO space */
  71 +
  72 +#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */
  73 +#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */
  74 +#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */
  75 +#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */
  76 +#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */
  77 +#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */
  78 +
  79 +/* Bank 1 in IO space */
  80 +
  81 +#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */
  82 +#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */
  83 +#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */
  84 +#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */
  85 +#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */
  86 +#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */
  87 +#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */
  88 +#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */
  89 +#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */
  90 +#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */
  91 +
  92 +/* Bank 2 in IO space */
  93 +
  94 +#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */
  95 +#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */
  96 +#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */
  97 +#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */
  98 +#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */
  99 +#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */
  100 +#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */
  101 +#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */
  102 +#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */
  103 +#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */
  104 +#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */
  105 +
  106 +
  107 +#ifndef __ASSEMBLY__
  108 +
  109 +/*
  110 + * A couple of utility inlines to aid debugging using the LED's on the
  111 + * debug board.
  112 + */
  113 +
  114 +static inline void set_led_state(int state)
  115 +{
  116 + static unsigned long hw_led_state = 0;
  117 + volatile unsigned short *led_address = 0x04000016;
  118 +
  119 + hw_led_state = ((unsigned long)state);
  120 + *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
  121 +}
  122 +
  123 +
  124 +static inline void spin_up_leds()
  125 +{
  126 + volatile int i, j, k;
  127 +
  128 + for (k = 0; k < 2; k++) {
  129 + for (i = 0; i < 16; i++) {
  130 + for (j = 0; j < 5000; j++) {
  131 + set_led_state(1 << i);
  132 + }
  133 + }
  134 + for (i = 15; i >= 0; i--) {
  135 + for (j = 0; j < 5000; j++) {
  136 + set_led_state(1 << i);
  137 + }
  138 + }
  139 + }
  140 +}
  141 +
  142 +#endif /* ! __ASSEMBLY__ */
  143 +
  144 +#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */
include/configs/omap730.h
Diff comments   View file @ a56bd92
  1 +/*
  2 + *
  3 + * BRIEF MODULE DESCRIPTION
  4 + * OMAP730 hardware map
  5 + *
  6 + * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
  7 + * Author: MPC-Data Limited
  8 + * Dave Peverley
  9 + *
  10 + * This program is free software; you can redistribute it and/or modify it
  11 + * under the terms of the GNU General Public License as published by the
  12 + * Free Software Foundation; either version 2 of the License, or (at your
  13 + * option) any later version.
  14 + *
  15 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  21 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25 + *
  26 + * You should have received a copy of the GNU General Public License along
  27 + * with this program; if not, write to the Free Software Foundation, Inc.,
  28 + * 675 Mass Ave, Cambridge, MA 02139, USA.
  29 + */
  30 +
  31 +
  32 +#ifndef __INCLUDED_OMAP730_H
  33 +#define __INCLUDED_OMAP730_H
  34 +
  35 +#include <asm/arch/sizes.h>
  36 +
  37 +
  38 +
  39 +
  40 +/***************************************************************************
  41 + * OMAP730 Configuration Registers
  42 + **************************************************************************/
  43 +
  44 +#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
  45 +#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
  46 +#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
  47 +#define DSP_CONF ((unsigned int)(0xFFFE1004))
  48 +#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
  49 +#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
  50 +#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
  51 +#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
  52 +#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
  53 +#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
  54 +#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
  55 +#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
  56 +#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
  57 +#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
  58 +#define SPECCTL ((unsigned int)(0xFFFE101C))
  59 +#define SPARE1 ((unsigned int)(0xFFFE1020))
  60 +#define SPARE2 ((unsigned int)(0xFFFE1024))
  61 +#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
  62 +#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
  63 +#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
  64 +#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
  65 +#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
  66 +#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
  67 +#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
  68 +#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
  69 +#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
  70 +#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
  71 +#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
  72 +#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
  73 +#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
  74 +#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
  75 +#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
  76 +#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
  77 +#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
  78 +#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
  79 +#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
  80 +#define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
  81 +#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
  82 +#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
  83 +#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
  84 +#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
  85 +#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
  86 +#define DEBUG1 ((unsigned int)(0xFFFE10E0))
  87 +#define DEBUG2 ((unsigned int)(0xFFFE10E4))
  88 +#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
  89 +
  90 +
  91 +
  92 +
  93 +/***************************************************************************
  94 + * OMAP730 EMIFS Registers (TRM 2.5.7)
  95 + **************************************************************************/
  96 +
  97 +#define TCMIF_BASE 0xFFFECC00
  98 +
  99 +#define EMIFS_LRUREG (TCMIF_BASE + 0x04)
  100 +#define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
  101 +#define FLASH_CFG_0 (TCMIF_BASE + 0x10)
  102 +#define FLASH_CFG_1 (TCMIF_BASE + 0x14)
  103 +#define FLASH_CFG_2 (TCMIF_BASE + 0x18)
  104 +#define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
  105 +#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
  106 +#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
  107 +#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
  108 +#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
  109 +#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
  110 +#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
  111 +#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
  112 +#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
  113 +#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
  114 +#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
  115 +#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
  116 +
  117 +
  118 +
  119 +/***************************************************************************
  120 + * OMAP730 Interrupt handlers
  121 + **************************************************************************/
  122 +
  123 +#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
  124 +#define OMAP_IH2_BASE 0xfffe0000
  125 +
  126 +
  127 +
  128 +/***************************************************************************
  129 + * OMAP730 Timers
  130 + *
  131 + * There are three general purpose OS timers in the 730 that can be
  132 + * configured in autoreload or one-shot modes.
  133 + **************************************************************************/
  134 +
  135 +#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
  136 +
  137 +/* 32k Timer Registers */
  138 +#define TIMER32k_CR 0x08
  139 +#define TIMER32k_TVR 0x00
  140 +#define TIMER32k_TCR 0x04
  141 +
  142 +/* 32k Timer Control Register definition */
  143 +#define TIMER32k_TSS (1<<0)
  144 +#define TIMER32k_TRB (1<<1)
  145 +#define TIMER32k_INT (1<<2)
  146 +#define TIMER32k_ARL (1<<3)
  147 +
  148 +/* MPU Timer base addresses */
  149 +#define OMAP730_MPUTIMER_BASE 0xfffec500
  150 +#define OMAP730_MPUTIMER_OFF 0x00000100
  151 +
  152 +#define OMAP730_TIMER1_BASE 0xFFFEC500
  153 +#define OMAP730_TIMER2_BASE 0xFFFEC600
  154 +#define OMAP730_TIMER3_BASE 0xFFFEC700
  155 +
  156 +/* MPU Timer Register offsets */
  157 +#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
  158 +#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
  159 +#define READ_TIM 0x08 /* MPU_READ_TIMER */
  160 +
  161 +/* MPU_CNTL_TIMER register bits */
  162 +#define MPUTIM_FREE (1<<6)
  163 +#define MPUTIM_CLOCK_ENABLE (1<<5)
  164 +#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
  165 +#define MPUTIM_PTV_BIT 2
  166 +#define MPUTIM_AR (1<<1)
  167 +#define MPUTIM_ST (1<<0)
  168 +
  169 +
  170 +
  171 +/***************************************************************************
  172 + * OMAP730 GPIO
  173 + *
  174 + * The GPIO control is split over 6 register bases in the OMAP730 to allow
  175 + * access to all the (6 x 32) GPIO pins!
  176 + **************************************************************************/
  177 +
  178 +#define OMAP730_GPIO_BASE_1 0xFFFBC000
  179 +#define OMAP730_GPIO_BASE_2 0xFFFBC800
  180 +#define OMAP730_GPIO_BASE_3 0xFFFBD000
  181 +#define OMAP730_GPIO_BASE_4 0xFFFBD800
  182 +#define OMAP730_GPIO_BASE_5 0xFFFBE000
  183 +#define OMAP730_GPIO_BASE_6 0xFFFBE800
  184 +
  185 +#define GPIO_DATA_INPUT 0x00
  186 +#define GPIO_DATA_OUTPUT 0x04
  187 +#define GPIO_DIRECTION_CONTROL 0x08
  188 +#define GPIO_INTERRUPT_CONTROL 0x0C
  189 +#define GPIO_INTERRUPT_MASK 0x10
  190 +#define GPIO_INTERRUPT_STATUS 0x14
  191 +
  192 +#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
  193 +#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
  194 +#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
  195 +#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
  196 +#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
  197 +#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
  198 +
  199 +#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
  200 +#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
  201 +#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
  202 +#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
  203 +#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
  204 +#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
  205 +
  206 +#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
  207 +#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
  208 +#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
  209 +#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
  210 +#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
  211 +#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
  212 +
  213 +#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
  214 +#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
  215 +#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
  216 +#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
  217 +#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
  218 +#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
  219 +
  220 +#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
  221 +#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
  222 +#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
  223 +#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
  224 +#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
  225 +#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
  226 +
  227 +#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
  228 +#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
  229 +#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
  230 +#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
  231 +#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
  232 +#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
  233 +
  234 +
  235 +
  236 +
  237 +/***************************************************************************
  238 + * OMAP730 Watchdog timers
  239 + **************************************************************************/
  240 +
  241 +#define WDTIM_BASE 0xFFFEC800
  242 +#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
  243 +#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
  244 +#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
  245 +#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
  246 +
  247 +
  248 +
  249 +
  250 +/***************************************************************************
  251 + * OMAP730 Interrupt Registers
  252 + **************************************************************************/
  253 +
  254 +/* Interrupt Register offsets */
  255 +
  256 +#define IRQ_ITR 0x00
  257 +#define IRQ_MIR 0x04
  258 +#define IRQ_SIR_IRQ 0x10
  259 +#define IRQ_SIR_FIQ 0x14
  260 +#define IRQ_CONTROL_REG 0x18
  261 +#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
  262 +#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
  263 +#define IRQ_GMIR 0xA0
  264 +
  265 +#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
  266 +#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
  267 +
  268 +
  269 +/***************************************************************************
  270 + * OMAP730 Intersystem Communication Register (TRM 4.5)
  271 + **************************************************************************/
  272 +
  273 +
  274 +#define ICR_BASE 0xFFFBB800
  275 +
  276 +#define M_ICR (ICR_BASE + 0x00)
  277 +#define G_ICR (ICR_BASE + 0x02)
  278 +#define M_CTL (ICR_BASE + 0x04)
  279 +#define G_CTL (ICR_BASE + 0x06)
  280 +#define PM_BA (ICR_BASE + 0x0A)
  281 +#define DM_BA (ICR_BASE + 0x0C)
  282 +#define RM_BA (ICR_BASE + 0x0E)
  283 +#define SSPI_TAS (ICR_BASE + 0x12)
  284 +
  285 +
  286 +
  287 +#endif /* ! __INCLUDED_OMAP730_H */
include/configs/omap730p2.h
Diff comments   View file @ a56bd92
  1 +/*
  2 + * (C) Copyright 2003-2004
  3 + * MPC Data Limited (http://www.mpc-data.co.uk)
  4 + * Dave Peverley <dpeverley at mpc-data.co.uk>
  5 + *
  6 + * Configuation settings for the TI OMAP Perseus 2 board.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#ifndef __CONFIG_H
  28 +#define __CONFIG_H
  29 +
  30 +
  31 +/*
  32 + * If we are developing, we might want to start armboot from ram
  33 + * so we MUST NOT initialize critical regs like mem-timing ...
  34 + */
  35 +
  36 +#define CONFIG_INIT_CRITICAL /* undef for developing */
  37 +
  38 +
  39 +/* allow to overwrite serial and ethaddr */
  40 +#define CONFIG_ENV_OVERWRITE
  41 +
  42 +
  43 +/*
  44 + * High Level Configuration Options
  45 + * (easy to change)
  46 + */
  47 +
  48 +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
  49 +#define CONFIG_OMAP 1 /* in a TI OMAP core */
  50 +#define CONFIG_OMAP730 1 /* which is in a 730 */
  51 +#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
  52 +
  53 +
  54 +/*
  55 + * Input clock of PLL
  56 + * The OMAP730 Perseus 2 has 13MHz input clock
  57 + */
  58 +
  59 +#define CONFIG_SYS_CLK_FREQ 13000000
  60 +
  61 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  62 +
  63 +#define CONFIG_MISC_INIT_R
  64 +
  65 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  66 +#define CONFIG_SETUP_MEMORY_TAGS 1
  67 +
  68 +
  69 +/*
  70 + * Size of malloc() pool
  71 + */
  72 +
  73 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  74 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  75 +
  76 +
  77 +/*
  78 + * Hardware drivers
  79 + */
  80 +
  81 +#define CONFIG_DRIVER_LAN91C96
  82 +#define CONFIG_LAN91C96_BASE 0x04000300
  83 +#define CONFIG_LAN91C96_EXT_PHY
  84 +
  85 +
  86 +/*
  87 + * NS16550 Configuration
  88 + */
  89 +
  90 +#define CFG_NS16550
  91 +#define CFG_NS16550_SERIAL
  92 +#define CFG_NS16550_REG_SIZE (1)
  93 +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
  94 +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
  95 + * on perseus */
  96 +
  97 +/*
  98 + * select serial console configuration
  99 + */
  100 +
  101 +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
  102 +
  103 +
  104 +#define CONFIG_CONS_INDEX 1
  105 +#define CONFIG_BAUDRATE 115200
  106 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  107 +
  108 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
  109 +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
  110 +
  111 +/*
  112 + * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  113 + */
  114 +
  115 +#include <cmd_confdefs.h>
  116 +#include <configs/omap730.h>
  117 +#include <configs/h2_p2_dbg_board.h>
  118 +
  119 +#define CONFIG_BOOTDELAY 3
  120 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
  121 +
  122 +#define CONFIG_LOADADDR 0x10000000
  123 +
  124 +#define CONFIG_ETHADDR
  125 +#define CONFIG_NETMASK 255.255.255.0
  126 +#define CONFIG_IPADDR 192.168.0.23
  127 +#define CONFIG_SERVERIP 192.150.0.100
  128 +#define CONFIG_BOOTFILE "uImage" /* File to load */
  129 +
  130 +#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
  131 +#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
  132 +#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
  133 +#endif
  134 +
  135 +
  136 +/*
  137 + * Miscellaneous configurable options
  138 + */
  139 +
  140 +#define CFG_LONGHELP /* undef to save memory */
  141 +#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
  142 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  143 +/* Print Buffer Size */
  144 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
  145 +#define CFG_MAXARGS 16 /* max number of command args */
  146 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  147 +
  148 +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
  149 +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
  150 +
  151 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  152 +
  153 +#define CFG_LOAD_ADDR 0x10000000 /* default load address */
  154 +
  155 +
  156 +/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
  157 + * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
  158 + * local divisor.
  159 + */
  160 +
  161 +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
  162 +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
  163 +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
  164 +
  165 +
  166 +/*-----------------------------------------------------------------------
  167 + * Stack sizes
  168 + *
  169 + * The stack sizes are set up in start.S using the settings below
  170 + */
  171 +
  172 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
  173 +#ifdef CONFIG_USE_IRQ
  174 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  175 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  176 +#endif
  177 +
  178 +
  179 +/*-----------------------------------------------------------------------
  180 + * Physical Memory Map
  181 + */
  182 +
  183 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  184 +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
  185 +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  186 +
  187 +#if defined(CONFIG_CS0_BOOT)
  188 +#define PHYS_FLASH_1 0x0C000000
  189 +#elif defined(CONFIG_CS3_BOOT)
  190 +#define PHYS_FLASH_1 0x00000000
  191 +#else
  192 +#error Unknown Boot Chip-Select number
  193 +#endif
  194 +
  195 +#define CFG_FLASH_BASE PHYS_FLASH_1
  196 +
  197 +
  198 +
  199 +/*-----------------------------------------------------------------------
  200 + * FLASH and environment organization
  201 + */
  202 +
  203 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  204 +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
  205 +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
  206 +/* addr of environment */
  207 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
  208 +
  209 +
  210 +/* timeout values are in ticks */
  211 +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
  212 +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
  213 +
  214 +#define CFG_ENV_IS_IN_FLASH 1
  215 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
  216 +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
  217 +
  218 +
  219 +
  220 +#endif /* ! __CONFIG_H */
... ... @@ -19,6 +19,18 @@
19 19 unsigned char lsr; /* 5 */
20 20 unsigned char msr; /* 6 */
21 21 unsigned char scr; /* 7 */
  22 +#if defined(CONFIG_OMAP730)
  23 + unsigned char mdr1; /* 8 */
  24 + unsigned char reg9; /* 9 */
  25 + unsigned char regA; /* A */
  26 + unsigned char regB; /* B */
  27 + unsigned char regC; /* C */
  28 + unsigned char regD; /* D */
  29 + unsigned char regE; /* E */
  30 + unsigned char regF; /* F */
  31 + unsigned char reg10; /* 10 */
  32 + unsigned char ssr; /* 11*/
  33 +#endif
22 34 } __attribute__ ((packed));
23 35 #elif (CFG_NS16550_REG_SIZE == 2)
24 36 struct NS16550 {